From mboxrd@z Thu Jan 1 00:00:00 1970 From: Michael Nazzareno Trimarchi Subject: Re: [PATCH 1/2] clk: imx6ul: add GPIO clock gates Date: Sat, 2 Jun 2018 16:12:11 +0200 Message-ID: References: <1526959560-6014-1-git-send-email-Anson.Huang@nxp.com> <1439344955.9677.1526991935718@email.1und1.de> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Fabio Estevam Cc: Stefan Wahren , Rob Herring , Fabio Estevam , Mark Rutland , Anson Huang , Matteo Lisi , Shawn Guo , Sascha Hauer , Michael Turquette , Stephen Boyd , linux-clk , NXP Linux Team , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , linux-kernel , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" List-Id: devicetree@vger.kernel.org Hi Fabio On Sat, Jun 2, 2018 at 4:07 PM, Fabio Estevam wrote: > Hi Michael, > > On Sat, Jun 2, 2018 at 11:04 AM, Michael Nazzareno Trimarchi > wrote: > >> ull is a preatty new platform so one board was listed. Are you sure >> that we need? > > There are several imx6ul based dts in mainline and it is better if we > can avoid dtb breakage when possible. > > In this case we can avoid the dtb breakage by adding the new clock > definitions at the end of the file, just like we do for all the other > imx devices. Yes, when I add new ul clock I move down ull (that is new), but agree that this is not possible in general. Michael