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* [PATCH v3 00/15] Tegra124 CL-DVFS / DFLL clocksource, plus cpufreq
@ 2014-08-19  3:33 Tuomas Tynkkynen
  2014-08-19  3:33 ` [PATCH v3 01/15] clk: tegra: Add binding for the Tegra124 DFLL clocksource Tuomas Tynkkynen
                   ` (14 more replies)
  0 siblings, 15 replies; 32+ messages in thread
From: Tuomas Tynkkynen @ 2014-08-19  3:33 UTC (permalink / raw)
  To: linux-tegra, linux-kernel, linux-arm-kernel, linux-pm
  Cc: devicetree, Prashant Gaikwad, Mike Turquette, Vince Hsu,
	Stephen Warren, Viresh Kumar, Peter De Schrijver,
	Rafael J. Wysocki, Thierry Reding, Tuomas Tynkkynen,
	Paul Walmsley

From: Tuomas Tynkkynen <ttynkkynen@nvidia.com>

v3 changes:
- Fix incorrect order of arguments to dfll_scale_dvco_rate
- Fix accidental commas at end-of-statement to semicolons
- Some cpufreq changes:
    - rename cpufreq-tegra to cpufreq-tegra20
    - have separate Kconfig entries for Tegra20/Tegra124 support
    - use 'select GENERIC_CPUFREQ_CPU0', not depends
    - support unbinding of the platform device
        - requires adding the vdd_cpu regulator to the DT so
          the old voltage can be restored when switching to PLLX
    - allocate a state structure instead of globals
    - use of_match_machine()
    - various style nits fixed

The cpufreq part is dependant on the of_match_machine() series.

Original cover letter:

This series implements the DFLL/CL-DVFS clock source for the fast CPU
cluster on Tegra124, and a cpufreq driver that uses the DFLL for
clocking the CPU. Most of this is based on Paul Walmsley's public patch
set from December 2013, which is available at
http://comments.gmane.org/gmane.linux.ports.tegra/15273

The DFLL clock hardware is a voltage-controlled oscillator plus
control logic that compares the generated output clock with a
51 MHz reference clock, and can make decisions to either lower
or raise the DFLL voltage to keep the output rate close to the
software-requested rate. The voltage changes are done by
communicating with an off-chip PMIC via either I2C or PWM.
As the DFLL oscillator is powered via the CPU rail, using
the DFLL as the CPU clocksource also gives us dynamic CPU
voltage scaling.

This series has been tested on the Jetson TK1 (Rev C). Porting this to
the Venice2 should be simple, though do note that it does not have
active cooling.

Thanks,
Tuomas


Paul Walmsley (1):
  clk: tegra: Add DFLL DVCO reset control for Tegra124

Tuomas Tynkkynen (14):
  clk: tegra: Add binding for the Tegra124 DFLL clocksource
  clk: tegra: Add library for the DFLL clock source (open-loop mode)
  clk: tegra: Add closed loop support for the DFLL
  clk: tegra: Add functions for parsing CVB tables
  clk: tegra: Add Tegra124 DFLL clocksource platform driver
  clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend
  clk: tegra: Add the DFLL as a possible parent of the cclk_g clock
  ARM: tegra: Add the DFLL to Tegra124 device tree
  ARM: tegra: Enable the DFLL on the Jetson TK1
  cpufreq: tegra124: Add device tree bindings
  cpufreq: tegra: Rename tegra-cpufreq to tegra20-cpufreq
  cpufreq: Add cpufreq driver for Tegra124
  ARM: tegra: Add entries for cpufreq on Tegra124
  ARM: tegra: Add CPU regulator to the Jetson TK1 device tree

 .../bindings/clock/nvidia,tegra124-dfll.txt        |   69 +
 .../bindings/cpufreq/tegra124-cpufreq.txt          |   44 +
 arch/arm/boot/dts/tegra124-jetson-tk1.dts          |   12 +-
 arch/arm/boot/dts/tegra124.dtsi                    |   33 +-
 arch/arm/mach-tegra/Kconfig                        |    1 +
 drivers/clk/tegra/Makefile                         |    3 +
 drivers/clk/tegra/clk-dfll.c                       | 1735 ++++++++++++++++++++
 drivers/clk/tegra/clk-dfll.h                       |   55 +
 drivers/clk/tegra/clk-tegra-super-gen4.c           |    4 +-
 drivers/clk/tegra/clk-tegra124-dfll-fcpu.c         |  165 ++
 drivers/clk/tegra/clk-tegra124.c                   |   61 +
 drivers/clk/tegra/clk.h                            |    3 +
 drivers/clk/tegra/cvb.c                            |  133 ++
 drivers/clk/tegra/cvb.h                            |   67 +
 drivers/cpufreq/Kconfig.arm                        |   14 +-
 drivers/cpufreq/Makefile                           |    3 +-
 drivers/cpufreq/tegra124-cpufreq.c                 |  206 +++
 .../cpufreq/{tegra-cpufreq.c => tegra20-cpufreq.c} |    0
 18 files changed, 2601 insertions(+), 7 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/nvidia,tegra124-dfll.txt
 create mode 100644 Documentation/devicetree/bindings/cpufreq/tegra124-cpufreq.txt
 create mode 100644 drivers/clk/tegra/clk-dfll.c
 create mode 100644 drivers/clk/tegra/clk-dfll.h
 create mode 100644 drivers/clk/tegra/clk-tegra124-dfll-fcpu.c
 create mode 100644 drivers/clk/tegra/cvb.c
 create mode 100644 drivers/clk/tegra/cvb.h
 create mode 100644 drivers/cpufreq/tegra124-cpufreq.c
 rename drivers/cpufreq/{tegra-cpufreq.c => tegra20-cpufreq.c} (100%)

-- 
1.8.1.5

^ permalink raw reply	[flat|nested] 32+ messages in thread

end of thread, other threads:[~2014-08-21 10:49 UTC | newest]

Thread overview: 32+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2014-08-19  3:33 [PATCH v3 00/15] Tegra124 CL-DVFS / DFLL clocksource, plus cpufreq Tuomas Tynkkynen
2014-08-19  3:33 ` [PATCH v3 01/15] clk: tegra: Add binding for the Tegra124 DFLL clocksource Tuomas Tynkkynen
2014-08-19  3:33 ` [PATCH v3 02/15] clk: tegra: Add library for the DFLL clock source (open-loop mode) Tuomas Tynkkynen
2014-08-19  3:33 ` [PATCH v3 03/15] clk: tegra: Add closed loop support for the DFLL Tuomas Tynkkynen
2014-08-19  4:36   ` Vince Hsu
2014-08-19 19:52     ` Tuomas Tynkkynen
2014-08-20  3:01   ` Vince Hsu
2014-08-19  3:33 ` [PATCH v3 04/15] clk: tegra: Add functions for parsing CVB tables Tuomas Tynkkynen
2014-08-19  3:33 ` [PATCH v3 05/15] clk: tegra: Add DFLL DVCO reset control for Tegra124 Tuomas Tynkkynen
2014-08-19  3:33 ` [PATCH v3 06/15] clk: tegra: Add Tegra124 DFLL clocksource platform driver Tuomas Tynkkynen
2014-08-19  3:33 ` [PATCH v3 07/15] clk: tegra: Save/restore CCLKG_BURST_POLICY on suspend Tuomas Tynkkynen
2014-08-19  3:33 ` [PATCH v3 08/15] clk: tegra: Add the DFLL as a possible parent of the cclk_g clock Tuomas Tynkkynen
2014-08-19  3:33 ` [PATCH v3 09/15] ARM: tegra: Add the DFLL to Tegra124 device tree Tuomas Tynkkynen
2014-08-19  3:33 ` [PATCH v3 10/15] ARM: tegra: Enable the DFLL on the Jetson TK1 Tuomas Tynkkynen
2014-08-19  3:33 ` [PATCH v3 11/15] cpufreq: tegra124: Add device tree bindings Tuomas Tynkkynen
2014-08-19  3:33 ` [PATCH v3 12/15] cpufreq: tegra: Rename tegra-cpufreq to tegra20-cpufreq Tuomas Tynkkynen
2014-08-19  3:47   ` Viresh Kumar
2014-08-19  3:33 ` [PATCH v3 13/15] cpufreq: Add cpufreq driver for Tegra124 Tuomas Tynkkynen
     [not found]   ` <1408419205-10048-14-git-send-email-tuomas.tynkkynen-X3B1VOXEql0@public.gmane.org>
2014-08-19  5:55     ` Viresh Kumar
     [not found]       ` <CAKohpokQOALPH13Ykz4nTBOby8J1X6_F30LNKz=gsC4wN3=3vg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-08-19 19:44         ` Tuomas Tynkkynen
     [not found]           ` <53F3A900.8010805-DDmLM1+adcrQT0dZR+AlfA@public.gmane.org>
2014-08-20  6:39             ` Viresh Kumar
2014-08-20 15:39               ` Javier Martinez Canillas
2014-08-20 20:02                 ` Handling commit change logs (was: [PATCH v3 13/15] cpufreq: Add cpufreq driver for Tegra124) Andreas Färber
2014-08-20 20:30                   ` Handling commit change logs Stephen Warren
     [not found]                     ` <53F50554.3050505-3lzwWm7+Weoh9ZMKESR00Q@public.gmane.org>
2014-08-21  4:26                       ` Viresh Kumar
2014-08-21  6:13                         ` Heiko Schocher
2014-08-21 10:35                           ` Javier Martinez Canillas
     [not found]                             ` <CABxcv=kJixq0WW5YEX-LvBfU-e9_0pkPw5JeHFOWz8h-_eSjyg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2014-08-21 10:49                               ` Heiko Schocher
2014-08-21 10:43                       ` Andreas Färber
     [not found]                   ` <53F4FED4.7060408-l3A5Bk7waGM@public.gmane.org>
2014-08-21 10:34                     ` Handling commit change logs (was: [PATCH v3 13/15] cpufreq: Add cpufreq driver for Tegra124) Javier Martinez Canillas
2014-08-19  3:33 ` [PATCH v3 14/15] ARM: tegra: Add entries for cpufreq on Tegra124 Tuomas Tynkkynen
2014-08-19  3:33 ` [PATCH v3 15/15] ARM: tegra: Add CPU regulator to the Jetson TK1 device tree Tuomas Tynkkynen

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