From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-il1-f173.google.com (mail-il1-f173.google.com [209.85.166.173]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 54428299928 for ; Mon, 16 Jun 2025 10:45:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.166.173 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750070703; cv=none; b=YOme21xCnblLrtlo0PqOmAHwMfzjVvyBLbJ555vnrue+AX92LaK5eR3ahEZyNWvqpqIaQz8VFUmni8UkejT8MqVwJOlVItTmKJni8dsoOXwwb8EZP2Gsvql8Hxxycli/6uZ80JHxgiXx1J9BcohqSloSXbotKocQyyefLKDQwzI= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1750070703; c=relaxed/simple; bh=J6R6SWEsvDm+66dPzlD87SecGN7m0uU0XfqGXWlTaok=; h=MIME-Version:References:In-Reply-To:From:Date:Message-ID:Subject: To:Cc:Content-Type; b=TIKZSV5nOBDbwQSqHn9RxvRRC8n33UbzDpoeDZlnhGtkXspficjKlC1gXM1CDW+VuJFKpYh++HqshqkLctGR6DOhGS93rsIfRP3cO3MNhthMwgwaZT0VqmNAxYzV18odernoXNpMkXMKmjBfMma9k5plOGneuGYT299E8FEMoNI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com; spf=pass smtp.mailfrom=google.com; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b=QL2l8BCu; arc=none smtp.client-ip=209.85.166.173 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=google.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=google.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=google.com header.i=@google.com header.b="QL2l8BCu" Received: by mail-il1-f173.google.com with SMTP id e9e14a558f8ab-3da76aea6d5so284645ab.1 for ; Mon, 16 Jun 2025 03:45:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20230601; t=1750070701; x=1750675501; darn=vger.kernel.org; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=J6R6SWEsvDm+66dPzlD87SecGN7m0uU0XfqGXWlTaok=; b=QL2l8BCuuqGwweka0fNcZGQ5qz/9RCBbGooX/S6U1RIabI326JTQ5xK+3h6djPMSJq UT3zG4OgsvH+ZQzdoh5BNpK3oFAORbdbRPu/SIWo1aiBXT4TUPC/bVH+kTFVCD3Kk1Jl LU4SI78z25ymBzjV2cDW4J/lrLbh+fiTLsOCyfbXcXVleC0qQlxxYZCD9W5C45cg/kQZ CBxNSgIdg+moJRABEQPxJPKwqWoWy7iNC7k0KmzOozhqlHpxGiJoHIH85SdgTZ5tj//n iYFmVqSf3FvSFLONeW3dOXATl41GJbNZk+Mbl9CKTPvfr6wfxaI5q3SDLTYJR+DIe3UB h8Lg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1750070701; x=1750675501; h=content-transfer-encoding:cc:to:subject:message-id:date:from :in-reply-to:references:mime-version:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J6R6SWEsvDm+66dPzlD87SecGN7m0uU0XfqGXWlTaok=; b=wJt+2LdVKahZtd4hKChqUAoCCMkF0fYUVBt5vuFlOnYzI7Gp9DpxAfgCwCL9y7Krmi nWEcXEWDGPuyOdu6owGYIBfgWHpX17wqy4799yRmFMQJYKlTg0aQbSP6vYSCz3ouClW4 P6R1UZJqpQuTj8e1GrGUjVYCBPsz6dsJ79PkHgJFSrE2Fyg2q4l10nkM88O4W2yi63Lk rZv/FzWdORAhmK08vbeZgWpjYxYnQdA/75NgW/yiSrIfJWQ+68QLqO9RmABUd5/xIRfQ s5peISlMBalSUHj2smuStwXjZ34AjJlcFfjcv88q9wNxrnchBystYJFwFl8qxeqrHhCZ 133w== X-Forwarded-Encrypted: i=1; AJvYcCWWwINME7p0TXk2L7zG0dzofXXbw/BndXNKLaP3Mo8Dd0SBeK2bOU+ZJR9BtiJZIOdkzjJt5Re5tgbV@vger.kernel.org X-Gm-Message-State: AOJu0YwQAy2r4I61R3VjvsmegoCAafF6tHhwbBpO4uWWrm7YdNFGf1bq 8gTz+WbQ/1HDBzcIaKectXeDrQX5B1H9TK1y7NfzAi26XAmwofTvlvWeyYkW2O3aObI1dZwjYUp YXeLxQtvY0+OZa9aejup0gd61/G7rNYzTpMd7hJgz X-Gm-Gg: ASbGnct8KnSPFhFYaeZBq3vb/KAdxPswge5OI3a2OhpqPqMUnO1s5Owbxr4evEmuwyj YhtzOpTL2zpl1DDK59hp5ilNc5hXn0mBitkIBYsRdjtTlwqG+uROFAnyOsPhLbBmy2g6NATznpc O0erHhPEsNIFFw72V7a9TbsqUyMUeVDqjOKIHKD3t0kg6V X-Google-Smtp-Source: AGHT+IGZ5j8v3Ocn8ObEJWFaqu0zHRUBhHJbRBl19pWYIGlLXaQ5CvYChKdFLMs6JM1wUgSUPI1j2DL9dy/hVkqNSNo= X-Received: by 2002:a05:6e02:1d9b:b0:3dd:a4b7:c737 with SMTP id e9e14a558f8ab-3de09fc2b9emr4525975ab.19.1750070701158; Mon, 16 Jun 2025 03:45:01 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250616-apple-cpmu-v7-0-df2778a44d5c@gmail.com> <20250616102945.GA17431@willie-the-truck> In-Reply-To: <20250616102945.GA17431@willie-the-truck> From: Ian Rogers Date: Mon, 16 Jun 2025 03:44:49 -0700 X-Gm-Features: AX0GCFsxy4AselWH-HXbNdNUVS0F-38THElPX6b9gGbKXhJTBrfP3qqVF_lXcMI Message-ID: Subject: Re: [PATCH RESEND v7 00/21] drivers/perf: apple_m1: Add Apple A7-A11, T2 SoC support To: Will Deacon Cc: Nick Chan , Mark Rutland , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Janne Grunau , Alyssa Rosenzweig , Neal Gompa , Sven Peter , Marc Zyngier , linux-arm-kernel@lists.infradead.org, linux-perf-users@vger.kernel.org, devicetree@vger.kernel.org, asahi@lists.linux.dev, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Mon, Jun 16, 2025 at 3:29=E2=80=AFAM Will Deacon wrote= : > > On Mon, Jun 16, 2025 at 02:36:18AM -0700, Ian Rogers wrote: > > On Sun, Jun 15, 2025 at 6:32=E2=80=AFPM Nick Chan wrote: > > > > > > This series adds support for the CPU PMU in the older Apple A7-A11, T= 2 > > > SoCs. These PMUs may have a different event layout, less counters, or > > > deliver their interrupts via IRQ instead of a FIQ. Since some of thos= e > > > older SoCs support 32-bit EL0, counting for 32-bit EL0 also need to > > > be enabled by the driver where applicable. > > > > > > Patch 1 adds the DT bindings. > > > Patch 2-7 prepares the driver to allow adding support for those > > > older SoCs. > > > Patch 8-12 adds support for the older SoCs. > > > Patch 13-21 are the DT changes. > > > > > > Signed-off-by: Nick Chan > > > > Hi Nick, > > > > This is substantial work and it looks good to me. Do you know why > > there's been little progress on landing these patches? Buggy Apple ARM > > PMU support in the kernel has led to reworking the perf tool. It seems > > best that we can have the best drivers possible. > > You reworked the perf tool to support these things? Why? These changes > are targetting chips in old iPhones afaict (as opposed to "Apple Silicon"= ). > I think that (a) most people don't particularly care about them and (b) > they're not fully supported _anyway_ because of crazy stuff like [1]. I was meaning that we reworked the perf tool to work around the Apple ARM PMU driver expecting to work as if it were an uncore rather than a core PMU driver. More context here: "[REGRESSION] Perf (userspace) broken on big.LITTLE systems since v6.5" https://lore.kernel.org/lkml/08f1f185-e259-4014-9ca4-6411d5c1bc65@marcan.st= / But in general it would be nice Apple ARM PMU support were well loved. I think we went 2 or 3 minor releases with the perf tool not working, threats of substantial reverts to avoid the PMU driver bug being exposed, etc. As for which Apple ARM devices should have perf support, it seems the more the merrier. Thanks, Ian > Will > > [1] https://lore.kernel.org/r/20240909091425.16258-1-towinchenmi@gmail.co= m