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[209.85.210.45]) by smtp.gmail.com with ESMTPSA id x32sm2692431ota.50.2020.06.09.23.46.31 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 09 Jun 2020 23:46:32 -0700 (PDT) Received: by mail-ot1-f45.google.com with SMTP id 97so894489otg.3 for ; Tue, 09 Jun 2020 23:46:31 -0700 (PDT) X-Received: by 2002:a05:6830:242e:: with SMTP id k14mr1533456ots.36.1591771590799; Tue, 09 Jun 2020 23:46:30 -0700 (PDT) MIME-Version: 1.0 References: <1590826218-23653-1-git-send-email-yong.wu@mediatek.com> <1590826218-23653-2-git-send-email-yong.wu@mediatek.com> <20200609212102.GA1416099@bogus> In-Reply-To: <20200609212102.GA1416099@bogus> From: Alexandre Courbot Date: Wed, 10 Jun 2020 15:46:18 +0900 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH v4 01/17] media: dt-binding: mtk-vcodec: Separating mtk-vcodec encode node. To: Rob Herring , Tiffany Lin Cc: Yong Wu , Matthias Brugger , Joerg Roedel , Evan Green , Robin Murphy , Tomasz Figa , Will Deacon , "moderated list:ARM/Mediatek SoC support" , srv_heupstream@mediatek.com, devicetree@vger.kernel.org, LKML , "moderated list:ARM/Mediatek SoC support" , iommu@lists.linux-foundation.org, youlin.pei@mediatek.com, Nicolas Boichat , Matthias Kaehlcke , anan.sun@mediatek.com, cui.zhang@mediatek.com, chao.hao@mediatek.com, ming-fan.chen@mediatek.com, eizan@chromium.org, Maoguang Meng , Hsin-Yi Wang , Irui Wang Content-Type: text/plain; charset="UTF-8" Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Jun 10, 2020 at 6:21 AM Rob Herring wrote: > > On Sat, May 30, 2020 at 04:10:02PM +0800, Yong Wu wrote: > > From: Maoguang Meng > > > > Update binding document since the avc and vp8 hardware encoder in > > mt8173 are now separated. Separate "mediatek,mt8173-vcodec-enc" to > > "mediatek,mt8173-vcodec-vp8-enc" and "mediatek,mt8173-vcodec-avc-enc". > > The h/w suddenly split in 2? You are breaking compatibility. Up to the > Mediatek maintainers to decide if that's okay, but you need to state you > are breaking compatibility (here and in the driver) and why that is > okay. In my understanding there is no real hardware using the old bindings at the moment, and the split is indeed a reflection of the actual hardware layout. Tiffany, can you give your acked-by if this change is ok with you? > > > > > This is a preparing patch for smi cleaning up "mediatek,larb". > > > > Signed-off-by: Maoguang Meng > > Signed-off-by: Hsin-Yi Wang > > Signed-off-by: Irui Wang > > Signed-off-by: Yong Wu > > --- > > .../devicetree/bindings/media/mediatek-vcodec.txt | 58 ++++++++++++---------- > > 1 file changed, 31 insertions(+), 27 deletions(-) > > > > diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > > index 8093335..1023740 100644 > > --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > > +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt > > @@ -4,7 +4,9 @@ Mediatek Video Codec is the video codec hw present in Mediatek SoCs which > > supports high resolution encoding and decoding functionalities. > > > > Required properties: > > -- compatible : "mediatek,mt8173-vcodec-enc" for MT8173 encoder > > +- compatible : must be one of the following string: > > + "mediatek,mt8173-vcodec-vp8-enc" for mt8173 vp8 encoder. > > + "mediatek,mt8173-vcodec-avc-enc" for mt8173 avc encoder. > > "mediatek,mt8183-vcodec-enc" for MT8183 encoder. > > "mediatek,mt8173-vcodec-dec" for MT8173 decoder. > > - reg : Physical base address of the video codec registers and length of > > @@ -13,10 +15,11 @@ Required properties: > > - mediatek,larb : must contain the local arbiters in the current Socs. > > - clocks : list of clock specifiers, corresponding to entries in > > the clock-names property. > > -- clock-names: encoder must contain "venc_sel_src", "venc_sel",, > > - "venc_lt_sel_src", "venc_lt_sel", decoder must contain "vcodecpll", > > - "univpll_d2", "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll", > > - "venc_lt_sel", "vdec_bus_clk_src". > > +- clock-names: > > + avc venc must contain "venc_sel"; > > + vp8 venc must contain "venc_lt_sel"; > > + decoder must contain "vcodecpll", "univpll_d2", "clk_cci400_sel", > > + "vdec_sel", "vdecpll", "vencpll", "venc_lt_sel", "vdec_bus_clk_src". > > - iommus : should point to the respective IOMMU block with master port as > > argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt > > for details. > > @@ -80,14 +83,10 @@ vcodec_dec: vcodec@16000000 { > > assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; > > }; > > > > - vcodec_enc: vcodec@18002000 { > > - compatible = "mediatek,mt8173-vcodec-enc"; > > - reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/ > > - <0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/ > > - interrupts = , > > - ; > > - mediatek,larb = <&larb3>, > > - <&larb5>; > > +vcodec_enc: vcodec@18002000 { > > + compatible = "mediatek,mt8173-vcodec-avc-enc"; > > + reg = <0 0x18002000 0 0x1000>; > > + interrupts = ; > > iommus = <&iommu M4U_PORT_VENC_RCPU>, > > <&iommu M4U_PORT_VENC_REC>, > > <&iommu M4U_PORT_VENC_BSDMA>, > > @@ -98,8 +97,20 @@ vcodec_dec: vcodec@16000000 { > > <&iommu M4U_PORT_VENC_REF_LUMA>, > > <&iommu M4U_PORT_VENC_REF_CHROMA>, > > <&iommu M4U_PORT_VENC_NBM_RDMA>, > > - <&iommu M4U_PORT_VENC_NBM_WDMA>, > > - <&iommu M4U_PORT_VENC_RCPU_SET2>, > > + <&iommu M4U_PORT_VENC_NBM_WDMA>; > > + mediatek,larb = <&larb3>; > > + mediatek,vpu = <&vpu>; > > + clocks = <&topckgen CLK_TOP_VENC_SEL>; > > + clock-names = "venc_sel"; > > + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>; > > + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>; > > + }; > > + > > +vcodec_enc_lt: vcodec@19002000 { > > + compatible = "mediatek,mt8173-vcodec-vp8-enc"; > > + reg = <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ > > + interrupts = ; > > + iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, > > <&iommu M4U_PORT_VENC_REC_FRM_SET2>, > > <&iommu M4U_PORT_VENC_BSDMA_SET2>, > > <&iommu M4U_PORT_VENC_SV_COMA_SET2>, > > @@ -108,17 +119,10 @@ vcodec_dec: vcodec@16000000 { > > <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, > > <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, > > <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; > > + mediatek,larb = <&larb5>; > > mediatek,vpu = <&vpu>; > > - clocks = <&topckgen CLK_TOP_VENCPLL_D2>, > > - <&topckgen CLK_TOP_VENC_SEL>, > > - <&topckgen CLK_TOP_UNIVPLL1_D2>, > > - <&topckgen CLK_TOP_VENC_LT_SEL>; > > - clock-names = "venc_sel_src", > > - "venc_sel", > > - "venc_lt_sel_src", > > - "venc_lt_sel"; > > - assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, > > - <&topckgen CLK_TOP_VENC_LT_SEL>; > > - assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>, > > - <&topckgen CLK_TOP_UNIVPLL1_D2>; > > + clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; > > + clock-names = "venc_lt_sel"; > > + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>; > > + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>; > > }; > > -- > > 1.9.1