From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ulf Hansson Subject: Re: [PATCH v1 1/2] mmc: dt-bindings: add "bus-clk" for MT2712 Date: Mon, 8 Oct 2018 13:51:20 +0200 Message-ID: References: <1538188195-3608-1-git-send-email-chaotian.jing@mediatek.com> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: <1538188195-3608-1-git-send-email-chaotian.jing@mediatek.com> Sender: linux-kernel-owner@vger.kernel.org To: Chaotian Jing Cc: Rob Herring , Mark Rutland , Matthias Brugger , Ryder Lee , Wolfram Sang , Sean Wang , "linux-mmc@vger.kernel.org" , DTML , Linux ARM , linux-mediatek@lists.infradead.org, Linux Kernel Mailing List , srv_heupstream List-Id: devicetree@vger.kernel.org On 29 September 2018 at 04:29, Chaotian Jing wrote: > On MT2712 MSDC0/3, HCLK/bus-clk need gate/ungate together, > or will hang when access MSDC register. > > Signed-off-by: Chaotian Jing Applied for next, thanks! Kind regards Uffe > --- > Documentation/devicetree/bindings/mmc/mtk-sd.txt | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.txt b/Documentation/devicetree/bindings/mmc/mtk-sd.txt > index f33467a..f2208f4 100644 > --- a/Documentation/devicetree/bindings/mmc/mtk-sd.txt > +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.txt > @@ -22,6 +22,7 @@ Required properties: > "source" - source clock (required) > "hclk" - HCLK which used for host (required) > "source_cg" - independent source clock gate (required for MT2712) > + "bus_clk" - bus clock used for internal register access (required for MT2712 MSDC0/3) > - pinctrl-names: should be "default", "state_uhs" > - pinctrl-0: should contain default/high speed pin ctrl > - pinctrl-1: should contain uhs mode pin ctrl > -- > 1.8.1.1.dirty >