From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ulf Hansson Subject: Re: [PATCH RESEND 02/12] mmc: sdhci-pxav3: Respect MMC_DDR52 timing on uhs signaling Date: Mon, 27 Oct 2014 14:38:49 +0100 Message-ID: References: <1413883364-681-1-git-send-email-sebastian.hesselbarth@gmail.com> <1413883364-681-3-git-send-email-sebastian.hesselbarth@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <1413883364-681-3-git-send-email-sebastian.hesselbarth@gmail.com> Sender: linux-mmc-owner@vger.kernel.org To: Sebastian Hesselbarth Cc: Chris Ball , =?UTF-8?Q?Antoine_T=C3=A9nart?= , linux-mmc , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" List-Id: devicetree@vger.kernel.org On 21 October 2014 11:22, Sebastian Hesselbarth wrote: > commit bb8175a8aa42d731a840cd474e348ac3367eb5a0 > ("mmc: sdhci: clarify DDR timing mode between SD-UHS and eMMC") > added MMC_DDR52 as eMMC's DDR mode to be distinguished from SD-UHS. > > While the differentation may be useful, pxav3 SDHCI controller lacks > a corresponding check in its custom .set_uhs_signaling callback for > MMC_DDR52. This patch adds a new switch case for MMC_TIMING_MMC_DDR52 > to MMC_TIMING_UHS_DDR50 case. > > Signed-off-by: Sebastian Hesselbarth Thanks! Applied for next! Kind regards Uffe > --- > Cc: Chris Ball > Cc: Ulf Hansson > Cc: "Antoine T=C3=A9nart" > Cc: linux-mmc@vger.kernel.org > Cc: devicetree@vger.kernel.org > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > --- > drivers/mmc/host/sdhci-pxav3.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/mmc/host/sdhci-pxav3.c b/drivers/mmc/host/sdhci-= pxav3.c > index 5036d7d39529..b55c807982fe 100644 > --- a/drivers/mmc/host/sdhci-pxav3.c > +++ b/drivers/mmc/host/sdhci-pxav3.c > @@ -211,6 +211,7 @@ static void pxav3_set_uhs_signaling(struct sdhci_= host *host, unsigned int uhs) > case MMC_TIMING_UHS_SDR104: > ctrl_2 |=3D SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_18= 0; > break; > + case MMC_TIMING_MMC_DDR52: > case MMC_TIMING_UHS_DDR50: > ctrl_2 |=3D SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180= ; > break; > -- > 2.1.1 >