Re: [PATCH v2 1/3] dt-bindings: mmc: arasan: Add compatible strings for Intel Keem Bay

[Ulf Hansson <ulf.hansson@linaro.org>]

On Tue, 26 May 2020 at 08:29, Wan Ahmad Zainie
<wan.ahmad.zainie.wan.mohamad@intel.com> wrote:
>
> Add new compatible strings in sdhci-of-arasan.c to support Intel Keem Bay
> eMMC/SD/SDIO controller, based on Arasan SDHCI 5.1.
>
> Signed-off-by: Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com>

Applied for next, thanks!

Kind regards
Uffe


> ---
>  .../devicetree/bindings/mmc/arasan,sdhci.txt  | 42 +++++++++++++++++++
>  1 file changed, 42 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> index 630fe707f5c4..f29bf7dd2ece 100644
> --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
> @@ -27,6 +27,12 @@ Required Properties:
>        For this device it is strongly suggested to include arasan,soc-ctl-syscon.
>      - "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1": Intel LGM SDXC PHY
>        For this device it is strongly suggested to include arasan,soc-ctl-syscon.
> +    - "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel Keem Bay eMMC
> +      For this device it is strongly suggested to include arasan,soc-ctl-syscon.
> +    - "intel,keembay-sdhci-5.1-sd": Intel Keem Bay SD controller
> +      For this device it is strongly suggested to include arasan,soc-ctl-syscon.
> +    - "intel,keembay-sdhci-5.1-sdio": Intel Keem Bay SDIO controller
> +      For this device it is strongly suggested to include arasan,soc-ctl-syscon.
>
>    [5] Documentation/devicetree/bindings/mmc/sdhci-am654.txt
>
> @@ -148,3 +154,39 @@ Example:
>                 phy-names = "phy_arasan";
>                 arasan,soc-ctl-syscon = <&sysconf>;
>         };
> +
> +       mmc: mmc@33000000 {
> +               compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
> +               interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
> +               reg = <0x0 0x33000000 0x0 0x300>;
> +               clock-names = "clk_xin", "clk_ahb";
> +               clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
> +                        <&scmi_clk KEEM_BAY_PSS_EMMC>;
> +               phys = <&emmc_phy>;
> +               phy-names = "phy_arasan";
> +               assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
> +               assigned-clock-rates = <200000000>;
> +               clock-output-names = "emmc_cardclock";
> +               #clock-cells = <0>;
> +               arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
> +       };
> +
> +       sd0: mmc@31000000 {
> +               compatible = "intel,keembay-sdhci-5.1-sd";
> +               interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> +               reg = <0x0 0x31000000 0x0 0x300>;
> +               clock-names = "clk_xin", "clk_ahb";
> +               clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
> +                        <&scmi_clk KEEM_BAY_PSS_SD0>;
> +               arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
> +       };
> +
> +       sd1: mmc@32000000 {
> +               compatible = "intel,keembay-sdhci-5.1-sdio";
> +               interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
> +               reg = <0x0 0x32000000 0x0 0x300>;
> +               clock-names = "clk_xin", "clk_ahb";
> +               clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD1>,
> +                        <&scmi_clk KEEM_BAY_PSS_SD1>;
> +               arasan,soc-ctl-syscon = <&sd1_phy_syscon>;
> +       };
> --
> 2.17.1
>