From: Svyatoslav Ryhel <clamor95@gmail.com>
To: Mikko Perttunen <mperttunen@nvidia.com>
Cc: "Thierry Reding" <thierry.reding@gmail.com>,
"Thierry Reding" <treding@nvidia.com>,
"Jonathan Hunter" <jonathanh@nvidia.com>,
"Sowjanya Komatineni" <skomatineni@nvidia.com>,
"Luca Ceresoli" <luca.ceresoli@bootlin.com>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
"Maxime Ripard" <mripard@kernel.org>,
"Thomas Zimmermann" <tzimmermann@suse.de>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Prashant Gaikwad" <pgaikwad@nvidia.com>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Mauro Carvalho Chehab" <mchehab@kernel.org>,
"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
"Dmitry Osipenko" <digetx@gmail.com>,
"Jonas Schwöbel" <jonasschwoebel@yahoo.de>,
"Charan Pedumuru" <charan.pedumuru@gmail.com>,
dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-media@vger.kernel.org, linux-clk@vger.kernel.org,
linux-staging@lists.linux.dev
Subject: Re: [PATCH v2 16/23] staging: media: tegra-video: tegra20: simplify format align calculations
Date: Mon, 22 Sep 2025 08:13:35 +0300 [thread overview]
Message-ID: <CAPVz0n1Tur0YY7yOYAyUFvyTxie4OteyzGhzv487L+aA-YY+wQ@mail.gmail.com> (raw)
In-Reply-To: <25240767.ouqheUzb2q@senjougahara>
пн, 22 вер. 2025 р. о 07:44 Mikko Perttunen <mperttunen@nvidia.com> пише:
>
> On Saturday, September 6, 2025 10:53 PM Svyatoslav Ryhel wrote:
> > Simplify format align calculations by slightly modifying supported formats
> > structure.
> >
> > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> > ---
> > drivers/staging/media/tegra-video/tegra20.c | 41 ++++++++-------------
> > 1 file changed, 16 insertions(+), 25 deletions(-)
> >
> > diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/staging/media/tegra-video/tegra20.c
> > index 6e0b3b728623..781c4e8ec856 100644
> > --- a/drivers/staging/media/tegra-video/tegra20.c
> > +++ b/drivers/staging/media/tegra-video/tegra20.c
> > @@ -280,20 +280,8 @@ static void tegra20_fmt_align(struct v4l2_pix_format *pix, unsigned int bpp)
> > pix->width = clamp(pix->width, TEGRA20_MIN_WIDTH, TEGRA20_MAX_WIDTH);
> > pix->height = clamp(pix->height, TEGRA20_MIN_HEIGHT, TEGRA20_MAX_HEIGHT);
> >
> > - switch (pix->pixelformat) {
> > - case V4L2_PIX_FMT_UYVY:
> > - case V4L2_PIX_FMT_VYUY:
> > - case V4L2_PIX_FMT_YUYV:
> > - case V4L2_PIX_FMT_YVYU:
> > - pix->bytesperline = roundup(pix->width, 2) * 2;
> > - pix->sizeimage = roundup(pix->width, 2) * 2 * pix->height;
> > - break;
> > - case V4L2_PIX_FMT_YUV420:
> > - case V4L2_PIX_FMT_YVU420:
> > - pix->bytesperline = roundup(pix->width, 8);
> > - pix->sizeimage = roundup(pix->width, 8) * pix->height * 3 / 2;
> > - break;
> > - }
> > + pix->bytesperline = DIV_ROUND_UP(pix->width * bpp, 8);
>
> Assuming the bpp is coming from the format table below, this changes the value of bytesperline for planar formats. With this it'll be (width * 12) / 8 i.e. width * 3/2, which doesn't sound right.
>
Downstream uses soc_mbus_bytes_per_line for this calculation which was
deprecated some time ago, here is a fragment
s32 soc_mbus_bytes_per_line(u32 width, const struct soc_mbus_pixelfmt *mf)
{
if (mf->fourcc == V4L2_PIX_FMT_JPEG)
return 0;
if (mf->layout != SOC_MBUS_LAYOUT_PACKED)
return width * mf->bits_per_sample / 8;
switch (mf->packing) {
case SOC_MBUS_PACKING_NONE:
return width * mf->bits_per_sample / 8;
case SOC_MBUS_PACKING_2X8_PADHI:
case SOC_MBUS_PACKING_2X8_PADLO:
case SOC_MBUS_PACKING_EXTEND16:
return width * 2;
case SOC_MBUS_PACKING_1_5X8:
return width * 3 / 2;
case SOC_MBUS_PACKING_VARIABLE:
return 0;
}
return -EINVAL;
}
V4L2_PIX_FMT_YUV420 and V4L2_PIX_FMT_YVU420 are classified as
SOC_MBUS_PACKING_1_5X8 hence we get width * 3/2
> > + pix->sizeimage = pix->bytesperline * pix->height;
> > }
> >
> > /*
> > @@ -576,20 +564,23 @@ static const struct tegra_vi_ops tegra20_vi_ops = {
> > .vi_stop_streaming = tegra20_vi_stop_streaming,
> > };
> >
> > -#define TEGRA20_VIDEO_FMT(MBUS_CODE, BPP, FOURCC) \
> > -{ \
> > - .code = MEDIA_BUS_FMT_##MBUS_CODE, \
> > - .bpp = BPP, \
> > - .fourcc = V4L2_PIX_FMT_##FOURCC, \
> > +#define TEGRA20_VIDEO_FMT(DATA_TYPE, BIT_WIDTH, MBUS_CODE, BPP, FOURCC) \
> > +{ \
> > + .img_dt = TEGRA_IMAGE_DT_##DATA_TYPE, \
> > + .bit_width = BIT_WIDTH, \
> > + .code = MEDIA_BUS_FMT_##MBUS_CODE, \
> > + .bpp = BPP, \
> > + .fourcc = V4L2_PIX_FMT_##FOURCC, \
> > }
> >
> > static const struct tegra_video_format tegra20_video_formats[] = {
> > - TEGRA20_VIDEO_FMT(UYVY8_2X8, 2, UYVY),
> > - TEGRA20_VIDEO_FMT(VYUY8_2X8, 2, VYUY),
> > - TEGRA20_VIDEO_FMT(YUYV8_2X8, 2, YUYV),
> > - TEGRA20_VIDEO_FMT(YVYU8_2X8, 2, YVYU),
> > - TEGRA20_VIDEO_FMT(UYVY8_2X8, 1, YUV420),
> > - TEGRA20_VIDEO_FMT(UYVY8_2X8, 1, YVU420),
> > + /* YUV422 */
> > + TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 16, UYVY),
> > + TEGRA20_VIDEO_FMT(YUV422_8, 16, VYUY8_2X8, 16, VYUY),
> > + TEGRA20_VIDEO_FMT(YUV422_8, 16, YUYV8_2X8, 16, YUYV),
> > + TEGRA20_VIDEO_FMT(YUV422_8, 16, YVYU8_2X8, 16, YVYU),
> > + TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 12, YUV420),
> > + TEGRA20_VIDEO_FMT(YUV422_8, 16, UYVY8_2X8, 12, YVU420),
> > };
> >
> > const struct tegra_vi_soc tegra20_vi_soc = {
> >
>
>
>
>
next prev parent reply other threads:[~2025-09-22 5:13 UTC|newest]
Thread overview: 71+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-06 13:53 [PATCH v2 00/23] tegra-video: add CSI support for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 01/23] clk: tegra: set CSUS as vi_sensors gate for Tegra20, Tegra30 and Tegra114 Svyatoslav Ryhel
2025-09-19 6:29 ` Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 02/23] dt-bindings: clock: tegra30: Add IDs for CSI pad clocks Svyatoslav Ryhel
2025-09-07 9:34 ` Krzysztof Kozlowski
2025-09-07 9:43 ` Svyatoslav Ryhel
2025-09-07 18:25 ` Krzysztof Kozlowski
2025-09-06 13:53 ` [PATCH v2 03/23] clk: tegra30: add CSI pad clock gates Svyatoslav Ryhel
2025-09-19 6:33 ` Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 04/23] dt-bindings: display: tegra: document Tegra30 VI and VIP Svyatoslav Ryhel
2025-09-06 19:17 ` Rob Herring (Arm)
2025-09-06 13:53 ` [PATCH v2 05/23] staging: media: tegra-video: expand VI and VIP support to Tegra30 Svyatoslav Ryhel
2025-09-17 7:52 ` Luca Ceresoli
2025-09-06 13:53 ` [PATCH v2 06/23] staging: media: tegra-video: vi: adjust get_selection op check Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 07/23] staging: media: tegra-video: vi: add flip controls only if no source controls are provided Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 08/23] staging: media: tegra-video: csi: move CSI helpers to header Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 09/23] gpu: host1x: convert MIPI to use operations Svyatoslav Ryhel
2025-09-19 6:47 ` Mikko Perttunen
2025-09-19 7:58 ` Svyatoslav Ryhel
2025-09-19 8:56 ` Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 10/23] staging: media: tegra-video: csi: add support for SoCs with integrated MIPI calibration Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 11/23] staging: media: tegra-video: csi: add a check to tegra_channel_get_remote_csi_subdev Svyatoslav Ryhel
2025-09-16 16:04 ` Luca Ceresoli
2025-09-16 16:24 ` Svyatoslav Ryhel
2025-09-17 7:25 ` Luca Ceresoli
2025-09-17 7:49 ` Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 12/23] dt-bindings: display: tegra: move avdd-dsi-csi-supply from VI to CSI Svyatoslav Ryhel
2025-09-09 0:49 ` Rob Herring (Arm)
2025-09-09 0:57 ` Rob Herring
2025-09-09 5:00 ` Svyatoslav Ryhel
2025-09-09 16:03 ` Rob Herring
2025-09-06 13:53 ` [PATCH v2 13/23] staging: media: tegra-video: csi: " Svyatoslav Ryhel
2025-09-17 7:52 ` Luca Ceresoli
2025-09-22 4:11 ` Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 14/23] staging: media: tegra-video: tegra20: set correct maximum width and height Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 15/23] staging: media: tegra-video: tegra20: add support for second output of VI Svyatoslav Ryhel
2025-09-22 4:29 ` Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 16/23] staging: media: tegra-video: tegra20: simplify format align calculations Svyatoslav Ryhel
2025-09-22 4:44 ` Mikko Perttunen
2025-09-22 5:13 ` Svyatoslav Ryhel [this message]
2025-09-22 6:23 ` Mikko Perttunen
2025-09-22 6:30 ` Svyatoslav Ryhel
2025-09-22 7:27 ` Mikko Perttunen
2025-09-22 7:36 ` Svyatoslav Ryhel
2025-09-23 6:03 ` Mikko Perttunen
2025-09-23 6:11 ` Svyatoslav Ryhel
2025-09-23 6:50 ` Svyatoslav Ryhel
2025-09-24 4:47 ` Mikko Perttunen
2025-09-24 10:24 ` Svyatoslav Ryhel
2025-09-24 23:20 ` Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 17/23] staging: media: tegra-video: tegra20: set VI HW revision Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 18/23] staging: media: tegra-video: tegra20: increase maximum VI clock frequency Svyatoslav Ryhel
2025-09-22 4:54 ` Mikko Perttunen
2025-09-22 4:58 ` Svyatoslav Ryhel
2025-09-22 6:23 ` Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 19/23] staging: media: tegra-video: tegra20: expand format support with RAW8/10 and YUV422 1X16 Svyatoslav Ryhel
2025-09-22 5:00 ` Mikko Perttunen
2025-09-06 13:53 ` [PATCH v2 20/23] staging: media: tegra-video: tegra20: adjust luma buffer stride Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 21/23] dt-bindings: display: tegra: document Tegra20 and Tegra30 CSI Svyatoslav Ryhel
2025-09-09 16:26 ` Rob Herring
2025-09-09 16:39 ` Svyatoslav Ryhel
2025-09-10 2:13 ` Rob Herring
2025-09-06 13:53 ` [PATCH v2 22/23] ARM: tegra: add CSI nodes for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-09-06 13:53 ` [PATCH v2 23/23] staging: media: tegra-video: add CSI support " Svyatoslav Ryhel
2025-09-15 5:46 ` kernel test robot
2025-09-22 5:15 ` Mikko Perttunen
2025-09-22 5:19 ` Svyatoslav Ryhel
2025-09-22 5:38 ` Mikko Perttunen
2025-09-22 6:16 ` Svyatoslav Ryhel
2025-09-22 6:36 ` Mikko Perttunen
2025-09-11 16:03 ` (subset) [PATCH v2 00/23] " Thierry Reding
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