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AJvYcCWFLO3XTs/Fup10nyp7yvBX562XWtXGlAtZV78CHJ0QkrJRP7PDf30fHSHSpESMWy2JAKyBx38Blfd1@vger.kernel.org X-Gm-Message-State: AOJu0YzVZyUB+/xmsU4oLIklUSMSxRA2V/2XXKjeR67u6RNqWKoqtRiU FHFMKGkgi0pb2M+4QlcMmqE0JzYAMOKuRihApxCmHcddaugAFteEW36WP9K+I7iyDZNMnD7QPRw wB3lhjQCnXiBOvTRDDQl21KuNcPrdT9c= X-Gm-Gg: ASbGnctztgC2s3gq0Sw21RLOomWZS9gDgQ1Tmlf0FKVIS+Xxl4mdcELvO9Y4XdRcBe7 FdaCncufPmy9i6ELEQk9QUHTaCNFpDq3E61PBpxtQQlC8ENfWjiG2JzTtNwbEmSJ+28D0Pg9pKM ZC0TIRKGdGEDFOUxO7QXgfzPl7HCW1WzNV8gtVXhccGm4QfzyzLi8Ko1MoXkdos5baZALsEvTaZ dVUynoR X-Google-Smtp-Source: AGHT+IEqpf+fahmlNxfcBD+gdZTresTyKx8zIRWfM243PFo4NiJuTkwOy4u6cIIp5K/YP1nuLHVN24tHIMe3nvhD4kQ= X-Received: by 2002:a05:600c:1f90:b0:45d:d609:1199 with SMTP id 5b1f17b1804b1-467f06887b5mr105306365e9.30.1758517120934; Sun, 21 Sep 2025 21:58:40 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250906135345.241229-1-clamor95@gmail.com> <20250906135345.241229-19-clamor95@gmail.com> <2331830.3VsfAaAtOV@senjougahara> In-Reply-To: <2331830.3VsfAaAtOV@senjougahara> From: Svyatoslav Ryhel Date: Mon, 22 Sep 2025 07:58:28 +0300 X-Gm-Features: AS18NWAi5iIH6gMmyrHteYV1m4FMyO6_CjTfEQzBzZCFo1CBmqpAnZAs7VssVwE Message-ID: Subject: Re: [PATCH v2 18/23] staging: media: tegra-video: tegra20: increase maximum VI clock frequency To: Mikko Perttunen Cc: Thierry Reding , Thierry Reding , Jonathan Hunter , Sowjanya Komatineni , Luca Ceresoli , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Prashant Gaikwad , Michael Turquette , Stephen Boyd , Mauro Carvalho Chehab , Greg Kroah-Hartman , Dmitry Osipenko , =?UTF-8?Q?Jonas_Schw=C3=B6bel?= , Charan Pedumuru , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-clk@vger.kernel.org, linux-staging@lists.linux.dev Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable =D0=BF=D0=BD, 22 =D0=B2=D0=B5=D1=80. 2025=E2=80=AF=D1=80. =D0=BE 07:54 Mikk= o Perttunen =D0=BF=D0=B8=D1=88=D0=B5: > > On Saturday, September 6, 2025 10:53=E2=80=AFPM Svyatoslav Ryhel wrote: > > Increase maximum VI clock frequency to 450MHz to allow correct work wit= h > > high resolution camera sensors. > > > > Signed-off-by: Svyatoslav Ryhel > > --- > > drivers/staging/media/tegra-video/tegra20.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/staging/media/tegra-video/tegra20.c b/drivers/stag= ing/media/tegra-video/tegra20.c > > index e0da496bb50f..3c5bafebfcd8 100644 > > --- a/drivers/staging/media/tegra-video/tegra20.c > > +++ b/drivers/staging/media/tegra-video/tegra20.c > > @@ -590,7 +590,7 @@ const struct tegra_vi_soc tegra20_vi_soc =3D { > > .ops =3D &tegra20_vi_ops, > > .hw_revision =3D 1, > > .vi_max_channels =3D 2, /* TEGRA_VI_OUT_1 and TEGRA_VI_OUT_2 */ > > - .vi_max_clk_hz =3D 150000000, > > + .vi_max_clk_hz =3D 450000000, > > .has_h_v_flip =3D true, > > }; > > > > > > Where does the 450MHz come from? Instead of hardcoding this value for eac= h SoC, could we just clk_set_rate(ULONG_MAX) like e.g. the vic driver does,= or does that get a too high rate? > This values comes from downstream 3.1 tegra30 sources and setting it higher breaks VI, I have tried. If it is set lower (150MHz as it was) it breaks VI for cameras with resolution higher then 2MP >