From: Xu Lu <luxu.kernel@bytedance.com>
To: Andrea Parri <parri.andrea@gmail.com>
Cc: corbet@lwn.net, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr,
will@kernel.org, peterz@infradead.org, boqun.feng@gmail.com,
mark.rutland@arm.com, ajones@ventanamicro.com, brs@rivosinc.com,
anup@brainfault.org, atish.patra@linux.dev, pbonzini@redhat.com,
shuah@kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
apw@canonical.com, joe@perches.com, linux-doc@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-kselftest@vger.kernel.org
Subject: Re: [External] Re: [PATCH v3 0/8] riscv: Add Zalasr ISA extension support
Date: Fri, 19 Sep 2025 20:12:14 +0800 [thread overview]
Message-ID: <CAPYmKFunbrughXdG9Fpum6bxHVu9jmjQdgLVSJ_JA9z+GDsZbA@mail.gmail.com> (raw)
In-Reply-To: <aM05J6FU0xG3SBzR@andrea>
On Fri, Sep 19, 2025 at 7:06 PM Andrea Parri <parri.andrea@gmail.com> wrote:
>
> > > > (not a review, just looking at this diff stat) is changing the fastpath
> > > >
> > > > read_unlock()
> > > > read_lock()
> > > >
> > > > from something like
> > > >
> > > > fence rw,w
> > > > amodadd.w
> > > > amoadd.w
> > > > fence r,rw
> > > >
> > > > to
> > > >
> > > > fence rw,rw
> > > > amoadd.w
> > > > amoadd.w
> > > > fence rw,rw
> > > >
> > > > no matter Zalasr or !Zalasr. Similarly for other atomic operations with
> > > > release or acquire semantics. I guess the change was not intentional?
> > > > If it was intentional, it should be properly mentioned in the changelog.
> > >
> > > Sorry about that. It is intended. The atomic operation before
> > > __atomic_acquire_fence or operation after __atomic_release_fence can
> > > be just a single ld or sd instruction instead of amocas or amoswap. In
> > > such cases, when the store release operation becomes 'sd.rl', the
> > > __atomic_acquire_fence via 'fence r, rw' can not ensure FENCE.TSO
> > > anymore. Thus I replace it with 'fence rw, rw'.
>
> But you could apply similar changes you performed for xchg & cmpxchg: use
> .AQ and .RL for other atomic RMW operations as well, no? AFAICS, that is
> what arm64 actually does in arch/arm64/include/asm/atomic_{ll_sc,lse}.h .
I see. I will study the implementation of ARM and refine my patch. Thanks a lot.
Best regards,
Xu Lu
>
> Andrea
>
>
> > This is also the common implementation on other architectures who use
> > aq/rl instructions like ARM. And you certainly already knew it~
prev parent reply other threads:[~2025-09-19 12:12 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-19 7:37 [PATCH v3 0/8] riscv: Add Zalasr ISA extension support Xu Lu
2025-09-19 7:37 ` [PATCH v3 1/8] riscv: add ISA extension parsing for Zalasr Xu Lu
2025-09-19 7:37 ` [PATCH v3 2/8] dt-bindings: riscv: Add Zalasr ISA extension description Xu Lu
2025-09-19 7:37 ` [PATCH v3 3/8] riscv: hwprobe: Export Zalasr extension Xu Lu
2025-09-19 7:37 ` [PATCH v3 4/8] riscv: Introduce Zalasr instructions Xu Lu
2025-09-19 7:37 ` [PATCH v3 5/8] riscv: Use Zalasr for smp_load_acquire/smp_store_release Xu Lu
2025-09-19 7:37 ` [PATCH v3 6/8] riscv: Apply acquire/release semantics to arch_xchg/arch_cmpxchg operations Xu Lu
2025-09-20 14:52 ` kernel test robot
2025-09-19 7:37 ` [PATCH v3 7/8] RISC-V: KVM: Allow Zalasr extensions for Guest/VM Xu Lu
2025-09-19 7:37 ` [PATCH v3 8/8] KVM: riscv: selftests: Add Zalasr extensions to get-reg-list test Xu Lu
2025-09-19 10:04 ` [PATCH v3 0/8] riscv: Add Zalasr ISA extension support Andrea Parri
2025-09-19 10:39 ` [External] " Xu Lu
2025-09-19 10:53 ` Xu Lu
2025-09-19 11:06 ` Andrea Parri
2025-09-19 12:12 ` Xu Lu [this message]
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