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AJvYcCWOOU6Uj+eUjVduy+j70780G7MMay2D5gmx2+xdk5b3ou7kmJJAaJPLujPRM9RFZUAW+VLMz8UsVNWw@vger.kernel.org X-Gm-Message-State: AOJu0Yyb2KkxZOC7EGtUoxuECDLSQTG271ml54Vf/FxMKNu0HbxP+PLq 1YoyrDgMOsmayCTwXfdpZE4h7S5l85dERmPu6CbSaZSRO3dqmg0+HNOVZxLe8mVqCL2OfTlIB9Q h6zoYp5Gd8pAKZqifnvpCkRaswxCEaNJ7Nu/f/oxJVQ== X-Gm-Gg: ASbGncu97rWG59vdACMpe77BWee0BycK7xhFe9cB6p8uRflgbORPyJZOGgsZk7dgif4 wBl5/Xge24gXwMTqlq73mGru4SWmj9BQr4du8JPQ+2phF2vm/URkL+6vF6nbaqopEjV8VoKPCpJ R0FQW30HZqr6wjBppKoLjAbYQx5t0unm+FXpS8MoBfOCV/E7sHxfw0rFVwkpWfwOy2VXal0dsZD 4q3HUpgPBNqymh3MTu5SM0UFLw8vcR6lTaD3jpEo44HkQfY/RcX X-Google-Smtp-Source: AGHT+IGm4y1poVxGUSiB4FXU7penSJROWpZ9IBJ4RsACGtjYuoj82wxnXamn8PKPxeWN3xAf3wDL9CKqcfW9WQHchPw= X-Received: by 2002:a17:90a:d40d:b0:32e:3f93:69f5 with SMTP id 98e67ed59e1d1-3309836a969mr3636748a91.26.1758283945619; Fri, 19 Sep 2025 05:12:25 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 References: <20250919073714.83063-1-luxu.kernel@bytedance.com> In-Reply-To: From: Xu Lu Date: Fri, 19 Sep 2025 20:12:14 +0800 X-Gm-Features: AS18NWC1LrBbaCsNeBFlqUXUWaqY8b6JknWKL06v5j39bQDtG4KDuo4wYFErj1E Message-ID: Subject: Re: [External] Re: [PATCH v3 0/8] riscv: Add Zalasr ISA extension support To: Andrea Parri Cc: corbet@lwn.net, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, will@kernel.org, peterz@infradead.org, boqun.feng@gmail.com, mark.rutland@arm.com, ajones@ventanamicro.com, brs@rivosinc.com, anup@brainfault.org, atish.patra@linux.dev, pbonzini@redhat.com, shuah@kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, apw@canonical.com, joe@perches.com, linux-doc@vger.kernel.org, kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-kselftest@vger.kernel.org Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable On Fri, Sep 19, 2025 at 7:06=E2=80=AFPM Andrea Parri wrote: > > > > > (not a review, just looking at this diff stat) is changing the fast= path > > > > > > > > read_unlock() > > > > read_lock() > > > > > > > > from something like > > > > > > > > fence rw,w > > > > amodadd.w > > > > amoadd.w > > > > fence r,rw > > > > > > > > to > > > > > > > > fence rw,rw > > > > amoadd.w > > > > amoadd.w > > > > fence rw,rw > > > > > > > > no matter Zalasr or !Zalasr. Similarly for other atomic operations= with > > > > release or acquire semantics. I guess the change was not intention= al? > > > > If it was intentional, it should be properly mentioned in the chang= elog. > > > > > > Sorry about that. It is intended. The atomic operation before > > > __atomic_acquire_fence or operation after __atomic_release_fence can > > > be just a single ld or sd instruction instead of amocas or amoswap. I= n > > > such cases, when the store release operation becomes 'sd.rl', the > > > __atomic_acquire_fence via 'fence r, rw' can not ensure FENCE.TSO > > > anymore. Thus I replace it with 'fence rw, rw'. > > But you could apply similar changes you performed for xchg & cmpxchg: use > .AQ and .RL for other atomic RMW operations as well, no? AFAICS, that is > what arm64 actually does in arch/arm64/include/asm/atomic_{ll_sc,lse}.h . I see. I will study the implementation of ARM and refine my patch. Thanks a= lot. Best regards, Xu Lu > > Andrea > > > > This is also the common implementation on other architectures who use > > aq/rl instructions like ARM. And you certainly already knew it~