Re: [PATCH 5/5] clk/exynos5420: assign sclk_pixel id to pixel clock divider

Re: [PATCH 5/5] clk/exynos5420: assign sclk_pixel id to pixel clock divider

[Rahul Sharma]

With this patch, it is at par with Exynos5250 and Exynos4 clocks
where sclk_pixel ID is assigned to a divider clock but in real,
sclk_pixel is listed under gate clocks (enum value).

Alternate to this, I can allocate a new ID, div_pixel, listed under
new category of Divider Clocks for Exyno4, 5250 and 5420.
div_pixel ID can be assigned to pixel clock dividers for all 3 SoCs.
This ID can be accessed by hdmi driver as usual. While sclk_pixel
ID can be left unused for Exyno4, 5250 as there are no pixel clock
gates. And, For 5420, sclk_pixel can optionally be used to
enable/disable the pixel clock gate.

Regards,
Rahul Sharma.

On Tue, Jun 18, 2013 at 8:03 PM, Rahul Sharma <rahul.sharma@samsung.com> wrote:
> sclk_pixel is used to represent pixel clock divider on all exynos
> SoCs not as a gate clock. It is queried in driver to pass as the
> parent to hdmi clock while switching between parents. A new ID can
> be asssigned Pixel gate clock which is currently not in use. Pixel
> clock gate is default 'on'.
>
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5420.c |    4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 59cf177..edd0696 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -434,7 +434,7 @@ struct samsung_div_clock exynos5420_div_clks[] __initdata = {
>         DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
>         DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
>         DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
> -       DIV(none, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
> +       DIV(sclk_pixel, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
>
>         /* Audio Block */
>         DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
> @@ -570,7 +570,7 @@ struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
>                 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
>         GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
>                 GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0),
> -       GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel",
> +       GATE(none, "sclk_pixel", "dout_hdmi_pixel",
>                 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
>         GATE(sclk_dp1, "sclk_dp1", "dout_dp1",
>                 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
> --
> 1.7.10.4
>

[PATCH 0/5] clk/exynos5420: add clocks for hdmi subsystem

[Rahul Sharma]

Add clock changes for hdmi subsystem for exynos5250 SoC. These
include addition of new clocks like mout_hdmi and smmu_tv, associating
ID to clk_hdmiphy and some essential corrections.

This set is based on kukjin's for-next branch at
http://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git.

This set dependents on the following patches which add support for Exynos5420
http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg19264.html

Rahul Sharma (5):
  clk/exynos5420: add sclk_hdmiphy to the list of special clocks
  clk/exynos5420: add gate clock for tv sysmmu
  clk/exynos5420: fix the order of parents of hdmi mux
  clk/exynos5420: add hdmi mux to change parents in hdmi driver
  clk/exynos5420: assign sclk_pixel id to pixel clock divider

 .../devicetree/bindings/clock/exynos5420-clock.txt   |    7 +++++++
 drivers/clk/samsung/clk-exynos5420.c                 |   18 +++++++++++-------
 2 files changed, 18 insertions(+), 7 deletions(-)

-- 
1.7.10.4

[PATCH 1/5] clk/exynos5420: add sclk_hdmiphy to the list of special clocks

[Rahul Sharma]

Add sclk_hdmiphy to the list of exposed clocks. This is required
by hdmi driver to change the parent of hdmi clock.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
 Documentation/devicetree/bindings/clock/exynos5420-clock.txt |    1 +
 drivers/clk/samsung/clk-exynos5420.c                         |    4 ++--
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index 9bcc4b1..596a368 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -59,6 +59,7 @@ clock which they consume.
   sclk_pwm		155
   sclk_gscl_wa		156
   sclk_gscl_wb		157
+  sclk_hdmiphy		158
 
    [Peripheral Clock Gates]
 
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 68a96cb..0945435 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -91,7 +91,7 @@ enum exynos5420_clks {
 	sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel,
 	sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0,
 	sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro,
-	sclk_pwm, sclk_gscl_wa, sclk_gscl_wb,
+	sclk_pwm, sclk_gscl_wa, sclk_gscl_wb, sclk_hdmiphy,
 
 	/* gate clocks */
 	aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3,
@@ -268,7 +268,7 @@ struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
 
 /* fixed rate clocks generated inside the soc */
 struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = {
-	FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
+	FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
 	FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
 	FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
 	FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
-- 
1.7.10.4

[PATCH 2/5] clk/exynos5420: add gate clock for tv sysmmu

[Rahul Sharma]

Adding sysmmu clock for tv for exynos5420.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
 Documentation/devicetree/bindings/clock/exynos5420-clock.txt |    1 +
 drivers/clk/samsung/clk-exynos5420.c                         |    3 ++-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index 596a368..f0b1ce0 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -180,6 +180,7 @@ clock which they consume.
   fimc_lite3		495
   aclk_g3d		500
   g3d			501
+  smmu_tv		502
 
 Example 1: An example of a clock controller node is listed below.
 
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 0945435..e8be481 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -109,7 +109,7 @@ enum exynos5420_clks {
 	aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0,
 	gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0,
 	aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
-	smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d,
+	smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_tv,
 
 	nr_clks,
 };
@@ -696,6 +696,7 @@ struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
 	GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0),
 	GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0),
 	GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0),
+	GATE(smmu_tv, "smmu_tv", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 0),
 };
 
 static __initdata struct of_device_id ext_clk_match[] = {
-- 
1.7.10.4

[PATCH 3/5] clk/exynos5420: fix the order of parents of hdmi mux

[Rahul Sharma]

Listing sclk_hdmiphy at 0th position in the list of parents is
causing wrong configuration in reg SRC_DISP10.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index e8be481..193d25e 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -257,7 +257,7 @@ PNAME(audio2_p)	= { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll",
 		  "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
 PNAME(spdif_p)	= { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2",
 		  "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" };
-PNAME(hdmi_p)	= { "sclk_hdmiphy", "dout_hdmi_pixel" };
+PNAME(hdmi_p)	= { "dout_hdmi_pixel", "sclk_hdmiphy" };
 PNAME(maudio0_p)	= { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
 			  "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
 
-- 
1.7.10.4

[PATCH 4/5] clk/exynos5420: add hdmi mux to change parents in hdmi driver

[Rahul Sharma]

hdmi driver needs to change the parent of hdmi clock
to pixel clock or hdmiphy clock, based on the stability
of hdmiphy. This patch is exposing the mux for changing
the parent.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
 Documentation/devicetree/bindings/clock/exynos5420-clock.txt |    5 +++++
 drivers/clk/samsung/clk-exynos5420.c                         |    5 ++++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
index f0b1ce0..c7a319d 100644
--- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
+++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
@@ -182,6 +182,11 @@ clock which they consume.
   g3d			501
   smmu_tv		502
 
+  Mux			ID
+  ----------------------------
+
+  mout_hdmi		1024
+
 Example 1: An example of a clock controller node is listed below.
 
 	clock: clock-controller@0x10010000 {
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 193d25e..59cf177 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -111,6 +111,9 @@ enum exynos5420_clks {
 	aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
 	smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_tv,
 
+	/* mux clocks */
+	mout_hdmi = 1024,
+
 	nr_clks,
 };
 
@@ -371,7 +374,7 @@ struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
 	MUX(none, "mout_mipi1", group2_p, SRC_DISP10, 16, 3),
 	MUX(none, "mout_dp1", group2_p, SRC_DISP10, 20, 3),
 	MUX(none, "mout_pixel", group2_p, SRC_DISP10, 24, 3),
-	MUX(none, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
+	MUX(mout_hdmi, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
 
 	/* MAU Block */
 	MUX(none, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3),
-- 
1.7.10.4

[PATCH 5/5] clk/exynos5420: assign sclk_pixel id to pixel clock divider

[Rahul Sharma]

sclk_pixel is used to represent pixel clock divider on all exynos
SoCs not as a gate clock. It is queried in driver to pass as the
parent to hdmi clock while switching between parents. A new ID can
be asssigned Pixel gate clock which is currently not in use. Pixel
clock gate is default 'on'.

Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
---
 drivers/clk/samsung/clk-exynos5420.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 59cf177..edd0696 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -434,7 +434,7 @@ struct samsung_div_clock exynos5420_div_clks[] __initdata = {
 	DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
 	DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
 	DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
-	DIV(none, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
+	DIV(sclk_pixel, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
 
 	/* Audio Block */
 	DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
@@ -570,7 +570,7 @@ struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
 		GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
 	GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
 		GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0),
-	GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel",
+	GATE(none, "sclk_pixel", "dout_hdmi_pixel",
 		GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
 	GATE(sclk_dp1, "sclk_dp1", "dout_dp1",
 		GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
-- 
1.7.10.4

Re: [PATCH 0/5] clk/exynos5420: add clocks for hdmi subsystem

[Rahul Sharma]

+ mike

On Tue, Jun 18, 2013 at 8:03 PM, Rahul Sharma <rahul.sharma-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org> wrote:
> Add clock changes for hdmi subsystem for exynos5250 SoC. These
> include addition of new clocks like mout_hdmi and smmu_tv, associating
> ID to clk_hdmiphy and some essential corrections.
>
> This set is based on kukjin's for-next branch at
> http://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git.
>
> This set dependents on the following patches which add support for Exynos5420
> http://www.mail-archive.com/linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org/msg19264.html
>
> Rahul Sharma (5):
>   clk/exynos5420: add sclk_hdmiphy to the list of special clocks
>   clk/exynos5420: add gate clock for tv sysmmu
>   clk/exynos5420: fix the order of parents of hdmi mux
>   clk/exynos5420: add hdmi mux to change parents in hdmi driver
>   clk/exynos5420: assign sclk_pixel id to pixel clock divider
>
>  .../devicetree/bindings/clock/exynos5420-clock.txt   |    7 +++++++
>  drivers/clk/samsung/clk-exynos5420.c                 |   18 +++++++++++-------
>  2 files changed, 18 insertions(+), 7 deletions(-)
>
> --
> 1.7.10.4
>

Re: [PATCH 0/5] clk/exynos5420: add clocks for hdmi subsystem

[Kukjin Kim]

On 06/19/13 13:04, Rahul Sharma wrote:
> + mike
>
Mike, I'm waiting for your reply on this. If you're OK, let me take this 
series on top of exynos5420 stuff in samsung tree.

Of course, if any concerns, please let me know.

Thanks,
- Kukjin

> On Tue, Jun 18, 2013 at 8:03 PM, Rahul Sharma<rahul.sharma@samsung.com>  wrote:
>> Add clock changes for hdmi subsystem for exynos5250 SoC. These
>> include addition of new clocks like mout_hdmi and smmu_tv, associating
>> ID to clk_hdmiphy and some essential corrections.
>>
>> This set is based on kukjin's for-next branch at
>> http://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git.
>>
>> This set dependents on the following patches which add support for Exynos5420
>> http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg19264.html
>>
>> Rahul Sharma (5):
>>    clk/exynos5420: add sclk_hdmiphy to the list of special clocks
>>    clk/exynos5420: add gate clock for tv sysmmu
>>    clk/exynos5420: fix the order of parents of hdmi mux
>>    clk/exynos5420: add hdmi mux to change parents in hdmi driver
>>    clk/exynos5420: assign sclk_pixel id to pixel clock divider
>>
>>   .../devicetree/bindings/clock/exynos5420-clock.txt   |    7 +++++++
>>   drivers/clk/samsung/clk-exynos5420.c                 |   18 +++++++++++-------
>>   2 files changed, 18 insertions(+), 7 deletions(-)
>>
>> --
>> 1.7.10.4

Re: [PATCH 0/5] clk/exynos5420: add clocks for hdmi subsystem

[Mike Turquette]

Quoting Kukjin Kim (2013-06-19 07:01:17)
> On 06/19/13 13:04, Rahul Sharma wrote:
> > + mike
> >
> Mike, I'm waiting for your reply on this. If you're OK, let me take this 
> series on top of exynos5420 stuff in samsung tree.
> 
> Of course, if any concerns, please let me know.

I never got these patches.  I'm not subscribed to devicetree-devel or
linux-samsung so I only got two replies to patch #0, but none of the
code. Can you or Rajul resend?

Thanks,
Mike

> 
> Thanks,
> - Kukjin
> 
> > On Tue, Jun 18, 2013 at 8:03 PM, Rahul Sharma<rahul.sharma@samsung.com>  wrote:
> >> Add clock changes for hdmi subsystem for exynos5250 SoC. These
> >> include addition of new clocks like mout_hdmi and smmu_tv, associating
> >> ID to clk_hdmiphy and some essential corrections.
> >>
> >> This set is based on kukjin's for-next branch at
> >> http://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git.
> >>
> >> This set dependents on the following patches which add support for Exynos5420
> >> http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg19264.html
> >>
> >> Rahul Sharma (5):
> >>    clk/exynos5420: add sclk_hdmiphy to the list of special clocks
> >>    clk/exynos5420: add gate clock for tv sysmmu
> >>    clk/exynos5420: fix the order of parents of hdmi mux
> >>    clk/exynos5420: add hdmi mux to change parents in hdmi driver
> >>    clk/exynos5420: assign sclk_pixel id to pixel clock divider
> >>
> >>   .../devicetree/bindings/clock/exynos5420-clock.txt   |    7 +++++++
> >>   drivers/clk/samsung/clk-exynos5420.c                 |   18 +++++++++++-------
> >>   2 files changed, 18 insertions(+), 7 deletions(-)
> >>
> >> --
> >> 1.7.10.4

Re: [PATCH 0/5] clk/exynos5420: add clocks for hdmi subsystem

[Rahul Sharma]

On Fri, Jun 21, 2013 at 10:02 AM, Mike Turquette <mturquette@linaro.org> wrote:
> Quoting Kukjin Kim (2013-06-19 07:01:17)
>> On 06/19/13 13:04, Rahul Sharma wrote:
>> > + mike
>> >
>> Mike, I'm waiting for your reply on this. If you're OK, let me take this
>> series on top of exynos5420 stuff in samsung tree.
>>
>> Of course, if any concerns, please let me know.
>
> I never got these patches.  I'm not subscribed to devicetree-devel or
> linux-samsung so I only got two replies to patch #0, but none of the
> code. Can you or Rajul resend?
>

Sure mike.

> Thanks,
> Mike
>
>>
>> Thanks,
>> - Kukjin
>>
>> > On Tue, Jun 18, 2013 at 8:03 PM, Rahul Sharma<rahul.sharma@samsung.com>  wrote:
>> >> Add clock changes for hdmi subsystem for exynos5250 SoC. These
>> >> include addition of new clocks like mout_hdmi and smmu_tv, associating
>> >> ID to clk_hdmiphy and some essential corrections.
>> >>
>> >> This set is based on kukjin's for-next branch at
>> >> http://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git.
>> >>
>> >> This set dependents on the following patches which add support for Exynos5420
>> >> http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg19264.html
>> >>
>> >> Rahul Sharma (5):
>> >>    clk/exynos5420: add sclk_hdmiphy to the list of special clocks
>> >>    clk/exynos5420: add gate clock for tv sysmmu
>> >>    clk/exynos5420: fix the order of parents of hdmi mux
>> >>    clk/exynos5420: add hdmi mux to change parents in hdmi driver
>> >>    clk/exynos5420: assign sclk_pixel id to pixel clock divider
>> >>
>> >>   .../devicetree/bindings/clock/exynos5420-clock.txt   |    7 +++++++
>> >>   drivers/clk/samsung/clk-exynos5420.c                 |   18 +++++++++++-------
>> >>   2 files changed, 18 insertions(+), 7 deletions(-)
>> >>
>> >> --
>> >> 1.7.10.4

Re: [PATCH 1/5] clk/exynos5420: add sclk_hdmiphy to the list of special clocks

[Rahul Sharma]

+Mike

On Tue, Jun 18, 2013 at 8:03 PM, Rahul Sharma <rahul.sharma@samsung.com> wrote:
> Add sclk_hdmiphy to the list of exposed clocks. This is required
> by hdmi driver to change the parent of hdmi clock.
>
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> ---
>  Documentation/devicetree/bindings/clock/exynos5420-clock.txt |    1 +
>  drivers/clk/samsung/clk-exynos5420.c                         |    4 ++--
>  2 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
> index 9bcc4b1..596a368 100644
> --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
> @@ -59,6 +59,7 @@ clock which they consume.
>    sclk_pwm             155
>    sclk_gscl_wa         156
>    sclk_gscl_wb         157
> +  sclk_hdmiphy         158
>
>     [Peripheral Clock Gates]
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 68a96cb..0945435 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -91,7 +91,7 @@ enum exynos5420_clks {
>         sclk_i2s2, sclk_pcm1, sclk_pcm2, sclk_spdif, sclk_hdmi, sclk_pixel,
>         sclk_dp1, sclk_mipi1, sclk_fimd1, sclk_maudio0, sclk_maupcm0,
>         sclk_usbd300, sclk_usbd301, sclk_usbphy300, sclk_usbphy301, sclk_unipro,
> -       sclk_pwm, sclk_gscl_wa, sclk_gscl_wb,
> +       sclk_pwm, sclk_gscl_wa, sclk_gscl_wb, sclk_hdmiphy,
>
>         /* gate clocks */
>         aclk66_peric = 256, uart0, uart1, uart2, uart3, i2c0, i2c1, i2c2, i2c3,
> @@ -268,7 +268,7 @@ struct samsung_fixed_rate_clock exynos5420_fixed_rate_ext_clks[] __initdata = {
>
>  /* fixed rate clocks generated inside the soc */
>  struct samsung_fixed_rate_clock exynos5420_fixed_rate_clks[] __initdata = {
> -       FRATE(none, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
> +       FRATE(sclk_hdmiphy, "sclk_hdmiphy", NULL, CLK_IS_ROOT, 24000000),
>         FRATE(none, "sclk_pwi", NULL, CLK_IS_ROOT, 24000000),
>         FRATE(none, "sclk_usbh20", NULL, CLK_IS_ROOT, 48000000),
>         FRATE(none, "mphy_refclk_ixtal24", NULL, CLK_IS_ROOT, 48000000),
> --
> 1.7.10.4
>

Re: [PATCH 2/5] clk/exynos5420: add gate clock for tv sysmmu

[Rahul Sharma]

+Mike

On Tue, Jun 18, 2013 at 8:03 PM, Rahul Sharma <rahul.sharma@samsung.com> wrote:
> Adding sysmmu clock for tv for exynos5420.
>
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> ---
>  Documentation/devicetree/bindings/clock/exynos5420-clock.txt |    1 +
>  drivers/clk/samsung/clk-exynos5420.c                         |    3 ++-
>  2 files changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
> index 596a368..f0b1ce0 100644
> --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
> @@ -180,6 +180,7 @@ clock which they consume.
>    fimc_lite3           495
>    aclk_g3d             500
>    g3d                  501
> +  smmu_tv              502
>
>  Example 1: An example of a clock controller node is listed below.
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 0945435..e8be481 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -109,7 +109,7 @@ enum exynos5420_clks {
>         aclk300_gscl = 460, smmu_gscl0, smmu_gscl1, gscl_wa, gscl_wb, gscl0,
>         gscl1, clk_3aa, aclk266_g2d = 470, sss, slim_sss, mdma0,
>         aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
> -       smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d,
> +       smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_tv,
>
>         nr_clks,
>  };
> @@ -696,6 +696,7 @@ struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
>         GATE(smmu_mscl0, "smmu_mscl0", "aclk400_mscl", GATE_IP_MSCL, 8, 0, 0),
>         GATE(smmu_mscl1, "smmu_mscl1", "aclk400_mscl", GATE_IP_MSCL, 9, 0, 0),
>         GATE(smmu_mscl2, "smmu_mscl2", "aclk400_mscl", GATE_IP_MSCL, 10, 0, 0),
> +       GATE(smmu_tv, "smmu_tv", "aclk200_disp1", GATE_IP_DISP1, 9, 0, 0),
>  };
>
>  static __initdata struct of_device_id ext_clk_match[] = {
> --
> 1.7.10.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 3/5] clk/exynos5420: fix the order of parents of hdmi mux

[Rahul Sharma]

+Mike

On Tue, Jun 18, 2013 at 8:03 PM, Rahul Sharma <rahul.sharma@samsung.com> wrote:
> Listing sclk_hdmiphy at 0th position in the list of parents is
> causing wrong configuration in reg SRC_DISP10.
>
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5420.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index e8be481..193d25e 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -257,7 +257,7 @@ PNAME(audio2_p)     = { "fin_pll", "cdclk2", "sclk_dpll", "sclk_mpll",
>                   "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
>  PNAME(spdif_p) = { "fin_pll", "dout_audio0", "dout_audio1", "dout_audio2",
>                   "spdif_extclk", "sclk_ipll", "sclk_epll", "sclk_rpll" };
> -PNAME(hdmi_p)  = { "sclk_hdmiphy", "dout_hdmi_pixel" };
> +PNAME(hdmi_p)  = { "dout_hdmi_pixel", "sclk_hdmiphy" };
>  PNAME(maudio0_p)       = { "fin_pll", "maudio_clk", "sclk_dpll", "sclk_mpll",
>                           "sclk_spll", "sclk_ipll", "sclk_epll", "sclk_rpll" };
>
> --
> 1.7.10.4
>

Re: [PATCH 4/5] clk/exynos5420: add hdmi mux to change parents in hdmi driver

[Rahul Sharma]

+Mike

On Tue, Jun 18, 2013 at 8:03 PM, Rahul Sharma <rahul.sharma@samsung.com> wrote:
> hdmi driver needs to change the parent of hdmi clock
> to pixel clock or hdmiphy clock, based on the stability
> of hdmiphy. This patch is exposing the mux for changing
> the parent.
>
> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
> ---
>  Documentation/devicetree/bindings/clock/exynos5420-clock.txt |    5 +++++
>  drivers/clk/samsung/clk-exynos5420.c                         |    5 ++++-
>  2 files changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
> index f0b1ce0..c7a319d 100644
> --- a/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
> +++ b/Documentation/devicetree/bindings/clock/exynos5420-clock.txt
> @@ -182,6 +182,11 @@ clock which they consume.
>    g3d                  501
>    smmu_tv              502
>
> +  Mux                  ID
> +  ----------------------------
> +
> +  mout_hdmi            1024
> +
>  Example 1: An example of a clock controller node is listed below.
>
>         clock: clock-controller@0x10010000 {
> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
> index 193d25e..59cf177 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -111,6 +111,9 @@ enum exynos5420_clks {
>         aclk333_g2d = 480, g2d, aclk333_432_gscl = 490, smmu_3aa, smmu_fimcl0,
>         smmu_fimcl1, smmu_fimcl3, fimc_lite3, aclk_g3d = 500, g3d, smmu_tv,
>
> +       /* mux clocks */
> +       mout_hdmi = 1024,
> +
>         nr_clks,
>  };
>
> @@ -371,7 +374,7 @@ struct samsung_mux_clock exynos5420_mux_clks[] __initdata = {
>         MUX(none, "mout_mipi1", group2_p, SRC_DISP10, 16, 3),
>         MUX(none, "mout_dp1", group2_p, SRC_DISP10, 20, 3),
>         MUX(none, "mout_pixel", group2_p, SRC_DISP10, 24, 3),
> -       MUX(none, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
> +       MUX(mout_hdmi, "mout_hdmi", hdmi_p, SRC_DISP10, 28, 1),
>
>         /* MAU Block */
>         MUX(none, "mout_maudio0", maudio0_p, SRC_MAU, 28, 3),
> --
> 1.7.10.4
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 5/5] clk/exynos5420: assign sclk_pixel id to pixel clock divider

[Rahul Sharma]

+Mike

On Tue, Jun 18, 2013 at 7:54 PM, Rahul Sharma <r.sh.open@gmail.com> wrote:
> With this patch, it is at par with Exynos5250 and Exynos4 clocks
> where sclk_pixel ID is assigned to a divider clock but in real,
> sclk_pixel is listed under gate clocks (enum value).
>
> Alternate to this, I can allocate a new ID, div_pixel, listed under
> new category of Divider Clocks for Exyno4, 5250 and 5420.
> div_pixel ID can be assigned to pixel clock dividers for all 3 SoCs.
> This ID can be accessed by hdmi driver as usual. While sclk_pixel
> ID can be left unused for Exyno4, 5250 as there are no pixel clock
> gates. And, For 5420, sclk_pixel can optionally be used to
> enable/disable the pixel clock gate.
>
> Regards,
> Rahul Sharma.
>
> On Tue, Jun 18, 2013 at 8:03 PM, Rahul Sharma <rahul.sharma@samsung.com> wrote:
>> sclk_pixel is used to represent pixel clock divider on all exynos
>> SoCs not as a gate clock. It is queried in driver to pass as the
>> parent to hdmi clock while switching between parents. A new ID can
>> be asssigned Pixel gate clock which is currently not in use. Pixel
>> clock gate is default 'on'.
>>
>> Signed-off-by: Rahul Sharma <rahul.sharma@samsung.com>
>> ---
>>  drivers/clk/samsung/clk-exynos5420.c |    4 ++--
>>  1 file changed, 2 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
>> index 59cf177..edd0696 100644
>> --- a/drivers/clk/samsung/clk-exynos5420.c
>> +++ b/drivers/clk/samsung/clk-exynos5420.c
>> @@ -434,7 +434,7 @@ struct samsung_div_clock exynos5420_div_clks[] __initdata = {
>>         DIV(none, "dout_fimd1", "mout_fimd1", DIV_DISP10, 0, 4),
>>         DIV(none, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
>>         DIV(none, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
>> -       DIV(none, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
>> +       DIV(sclk_pixel, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
>>
>>         /* Audio Block */
>>         DIV(none, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
>> @@ -570,7 +570,7 @@ struct samsung_gate_clock exynos5420_gate_clks[] __initdata = {
>>                 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
>>         GATE(sclk_hdmi, "sclk_hdmi", "mout_hdmi",
>>                 GATE_TOP_SCLK_DISP1, 9, CLK_SET_RATE_PARENT, 0),
>> -       GATE(sclk_pixel, "sclk_pixel", "dout_hdmi_pixel",
>> +       GATE(none, "sclk_pixel", "dout_hdmi_pixel",
>>                 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
>>         GATE(sclk_dp1, "sclk_dp1", "dout_dp1",
>>                 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
>> --
>> 1.7.10.4
>>

Re: [PATCH 0/5] clk/exynos5420: add clocks for hdmi subsystem

[Mike Turquette]

Quoting Rahul Sharma (2013-06-20 21:47:35)
> On Fri, Jun 21, 2013 at 10:02 AM, Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> wrote:
> > Quoting Kukjin Kim (2013-06-19 07:01:17)
> >> On 06/19/13 13:04, Rahul Sharma wrote:
> >> > + mike
> >> >
> >> Mike, I'm waiting for your reply on this. If you're OK, let me take this
> >> series on top of exynos5420 stuff in samsung tree.
> >>
> >> Of course, if any concerns, please let me know.
> >
> > I never got these patches.  I'm not subscribed to devicetree-devel or
> > linux-samsung so I only got two replies to patch #0, but none of the
> > code. Can you or Rajul resend?
> >
> 
> Sure mike.

Acked-by: Mike Turquette <mturquette-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org>

Regards,
Mike

> 
> > Thanks,
> > Mike
> >
> >>
> >> Thanks,
> >> - Kukjin
> >>
> >> > On Tue, Jun 18, 2013 at 8:03 PM, Rahul Sharma<rahul.sharma-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>  wrote:
> >> >> Add clock changes for hdmi subsystem for exynos5250 SoC. These
> >> >> include addition of new clocks like mout_hdmi and smmu_tv, associating
> >> >> ID to clk_hdmiphy and some essential corrections.
> >> >>
> >> >> This set is based on kukjin's for-next branch at
> >> >> http://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git.
> >> >>
> >> >> This set dependents on the following patches which add support for Exynos5420
> >> >> http://www.mail-archive.com/linux-samsung-soc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org/msg19264.html
> >> >>
> >> >> Rahul Sharma (5):
> >> >>    clk/exynos5420: add sclk_hdmiphy to the list of special clocks
> >> >>    clk/exynos5420: add gate clock for tv sysmmu
> >> >>    clk/exynos5420: fix the order of parents of hdmi mux
> >> >>    clk/exynos5420: add hdmi mux to change parents in hdmi driver
> >> >>    clk/exynos5420: assign sclk_pixel id to pixel clock divider
> >> >>
> >> >>   .../devicetree/bindings/clock/exynos5420-clock.txt   |    7 +++++++
> >> >>   drivers/clk/samsung/clk-exynos5420.c                 |   18 +++++++++++-------
> >> >>   2 files changed, 18 insertions(+), 7 deletions(-)
> >> >>
> >> >> --
> >> >> 1.7.10.4

Re: [PATCH 0/5] clk/exynos5420: add clocks for hdmi subsystem

[Rahul Sharma]

Thanks Mike.

I will rebase these patches to v3.11-next/samsung-clk branch and post v2.

regards,
Rahul Sharma.

On Fri, Jun 21, 2013 at 10:13 PM, Mike Turquette <mturquette@linaro.org> wrote:
> Quoting Rahul Sharma (2013-06-20 21:47:35)
>> On Fri, Jun 21, 2013 at 10:02 AM, Mike Turquette <mturquette@linaro.org> wrote:
>> > Quoting Kukjin Kim (2013-06-19 07:01:17)
>> >> On 06/19/13 13:04, Rahul Sharma wrote:
>> >> > + mike
>> >> >
>> >> Mike, I'm waiting for your reply on this. If you're OK, let me take this
>> >> series on top of exynos5420 stuff in samsung tree.
>> >>
>> >> Of course, if any concerns, please let me know.
>> >
>> > I never got these patches.  I'm not subscribed to devicetree-devel or
>> > linux-samsung so I only got two replies to patch #0, but none of the
>> > code. Can you or Rajul resend?
>> >
>>
>> Sure mike.
>
> Acked-by: Mike Turquette <mturquette@linaro.org>
>
> Regards,
> Mike
>
>>
>> > Thanks,
>> > Mike
>> >
>> >>
>> >> Thanks,
>> >> - Kukjin
>> >>
>> >> > On Tue, Jun 18, 2013 at 8:03 PM, Rahul Sharma<rahul.sharma@samsung.com>  wrote:
>> >> >> Add clock changes for hdmi subsystem for exynos5250 SoC. These
>> >> >> include addition of new clocks like mout_hdmi and smmu_tv, associating
>> >> >> ID to clk_hdmiphy and some essential corrections.
>> >> >>
>> >> >> This set is based on kukjin's for-next branch at
>> >> >> http://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git.
>> >> >>
>> >> >> This set dependents on the following patches which add support for Exynos5420
>> >> >> http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg19264.html
>> >> >>
>> >> >> Rahul Sharma (5):
>> >> >>    clk/exynos5420: add sclk_hdmiphy to the list of special clocks
>> >> >>    clk/exynos5420: add gate clock for tv sysmmu
>> >> >>    clk/exynos5420: fix the order of parents of hdmi mux
>> >> >>    clk/exynos5420: add hdmi mux to change parents in hdmi driver
>> >> >>    clk/exynos5420: assign sclk_pixel id to pixel clock divider
>> >> >>
>> >> >>   .../devicetree/bindings/clock/exynos5420-clock.txt   |    7 +++++++
>> >> >>   drivers/clk/samsung/clk-exynos5420.c                 |   18 +++++++++++-------
>> >> >>   2 files changed, 18 insertions(+), 7 deletions(-)
>> >> >>
>> >> >> --
>> >> >> 1.7.10.4

Re: [PATCH 0/5] clk/exynos5420: add clocks for hdmi subsystem

[Rahul Sharma]

Hi Mr. Kim,

v3.11-next/soc-exynos5420 seems correct branch for it, not
v3.11-next/samsung-clk. In this
case rebasing is not required. It cleanly applies there.

regards,
Rahul Sharma.

On Mon, Jun 24, 2013 at 9:33 AM, Rahul Sharma <r.sh.open@gmail.com> wrote:
> Thanks Mike.
>
> I will rebase these patches to v3.11-next/samsung-clk branch and post v2.
>
> regards,
> Rahul Sharma.
>
> On Fri, Jun 21, 2013 at 10:13 PM, Mike Turquette <mturquette@linaro.org> wrote:
>> Quoting Rahul Sharma (2013-06-20 21:47:35)
>>> On Fri, Jun 21, 2013 at 10:02 AM, Mike Turquette <mturquette@linaro.org> wrote:
>>> > Quoting Kukjin Kim (2013-06-19 07:01:17)
>>> >> On 06/19/13 13:04, Rahul Sharma wrote:
>>> >> > + mike
>>> >> >
>>> >> Mike, I'm waiting for your reply on this. If you're OK, let me take this
>>> >> series on top of exynos5420 stuff in samsung tree.
>>> >>
>>> >> Of course, if any concerns, please let me know.
>>> >
>>> > I never got these patches.  I'm not subscribed to devicetree-devel or
>>> > linux-samsung so I only got two replies to patch #0, but none of the
>>> > code. Can you or Rajul resend?
>>> >
>>>
>>> Sure mike.
>>
>> Acked-by: Mike Turquette <mturquette@linaro.org>
>>
>> Regards,
>> Mike
>>
>>>
>>> > Thanks,
>>> > Mike
>>> >
>>> >>
>>> >> Thanks,
>>> >> - Kukjin
>>> >>
>>> >> > On Tue, Jun 18, 2013 at 8:03 PM, Rahul Sharma<rahul.sharma@samsung.com>  wrote:
>>> >> >> Add clock changes for hdmi subsystem for exynos5250 SoC. These
>>> >> >> include addition of new clocks like mout_hdmi and smmu_tv, associating
>>> >> >> ID to clk_hdmiphy and some essential corrections.
>>> >> >>
>>> >> >> This set is based on kukjin's for-next branch at
>>> >> >> http://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git.
>>> >> >>
>>> >> >> This set dependents on the following patches which add support for Exynos5420
>>> >> >> http://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg19264.html
>>> >> >>
>>> >> >> Rahul Sharma (5):
>>> >> >>    clk/exynos5420: add sclk_hdmiphy to the list of special clocks
>>> >> >>    clk/exynos5420: add gate clock for tv sysmmu
>>> >> >>    clk/exynos5420: fix the order of parents of hdmi mux
>>> >> >>    clk/exynos5420: add hdmi mux to change parents in hdmi driver
>>> >> >>    clk/exynos5420: assign sclk_pixel id to pixel clock divider
>>> >> >>
>>> >> >>   .../devicetree/bindings/clock/exynos5420-clock.txt   |    7 +++++++
>>> >> >>   drivers/clk/samsung/clk-exynos5420.c                 |   18 +++++++++++-------
>>> >> >>   2 files changed, 18 insertions(+), 7 deletions(-)
>>> >> >>
>>> >> >> --
>>> >> >> 1.7.10.4

Re: [PATCH 0/5] clk/exynos5420: add clocks for hdmi subsystem

[Kukjin Kim]

On 06/24/13 13:28, Rahul Sharma wrote:

[...]

>>>>> I never got these patches.  I'm not subscribed to devicetree-devel or
>>>>> linux-samsung so I only got two replies to patch #0, but none of the
>>>>> code. Can you or Rajul resend?
>>>>>
>>>>
>>>> Sure mike.
>>>
>>> Acked-by: Mike Turquette<mturquette@linaro.org>
>>>
Applied with Mike's ack.

Thanks,
- Kukjin