From: Eric Lin <eric.lin@sifive.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: conor@kernel.org, krzysztof.kozlowski+dt@linaro.org,
linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, dslin1010@gmail.com,
Zong Li <zong.li@sifive.com>,
vincent.chen@sifive.com, Greentime Hu <greentime.hu@sifive.com>
Subject: Re: [PATCH 3/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
Date: Thu, 20 Jul 2023 17:49:17 +0800 [thread overview]
Message-ID: <CAPqJEFp_YgsXOymQPH1Pr4cORtv=8oS0OWnACWqNe69ARMRwvA@mail.gmail.com> (raw)
In-Reply-To: <0865b422-d587-c1c7-9463-510832ddddf4@linaro.org>
Hi Krzysztof,
On Wed, Jul 12, 2023 at 8:30 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 12/07/2023 13:09, Eric Lin wrote:
> > On Sat, Jul 01, 2023 at 10:22:25AM +0200, Krzysztof Kozlowski wrote:
> >> On 28/06/2023 18:31, Eric Lin wrote:
> >>
> >>>>>>
> >>>>>>> + - enum:
> >>>>>>> + - sifive,pL2Cache0
> >>>>>>> + - sifive,pL2Cache1
> >>>>>>
> >>>>>> What is "0" and "1" here? What do these compatibles represent? Why they
> >>>>>> do not have any SoC related part?
> >>>>>
> >>>>> The pL2Cache1 has minor changes in hardware, but it can use the same
> >>>>> pl2 cache driver.
> >>>>
> >>>> Then why aren't they compatible?
> >>>>
> >>>
> >>> The pL2Cache1 has removed some unused bits in the register compared to
> >>> pl2Cache0.
> >>> From the hardware perspective, they are not compatible but they can
> >>> share the same pl2 cache driver in software.
> >>
> >> So they are compatible... If they were not compatible, you wouldn't be
> >> able to use the same match in the driver.
> >>
> >>> Thus, we would like to keep both. It would be great if you can provide
> >>> some suggestions. Thanks.
> >>
> >> I propose to make them compatible, like every other piece of SoC. I
> >> don't see any benefit of having them separate.
> >>
> >
> > Hi Krzysztof,
> >
> > Sorry for the late reply.
> > The pl2 cache is our internal platform IP and is not part of any SoC.
> >
> > The reason why this driver is compatible with the hardware "pl2cache0" and hardware "pl2cache1"
> > is that it doesn't program the different parts of the config register
> > However, our internal software (e.g., bare-metal software) will program these different parts,
> > so it needs to rely on the different compatible string to identify the hardware.
> >
> > Additionally, we would like the compatible strings to reflect which hardware is being used Thanks.
>
> I don't understand how does it contradicts anything I said. So you do
> agree with me? Or what?
>
Thanks for your suggestions. OK, I'll fix it in v2.
Best regards,
Eric Lin
> Best regards,
> Krzysztof
>
prev parent reply other threads:[~2023-07-20 9:51 UTC|newest]
Thread overview: 30+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-16 6:32 [PATCH 0/3] Add SiFive Private L2 cache and PMU driver Eric Lin
2023-06-16 6:32 ` [PATCH 1/3] soc: sifive: Add SiFive private L2 cache support Eric Lin
2023-06-16 8:30 ` Ben Dooks
2023-06-23 8:21 ` Eric Lin
2023-06-16 19:02 ` Christophe JAILLET
2023-06-23 8:28 ` Eric Lin
2023-06-16 21:05 ` Conor Dooley
2023-06-23 9:49 ` Eric Lin
2023-06-16 6:32 ` [PATCH 2/3] soc: sifive: Add SiFive private L2 cache PMU driver Eric Lin
2023-06-16 10:12 ` Conor Dooley
2023-06-20 3:14 ` Eric Lin
2023-06-21 15:17 ` Conor Dooley
2023-06-23 13:24 ` Will Deacon
2023-06-23 16:03 ` Eric Lin
2023-07-11 8:41 ` Ben Dooks
2023-06-16 19:05 ` Christophe JAILLET
2023-06-16 6:32 ` [PATCH 3/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller Eric Lin
2023-06-16 10:10 ` Conor Dooley
2023-06-16 10:37 ` Ben Dooks
2023-06-26 3:06 ` Eric Lin
2023-06-16 10:45 ` Krzysztof Kozlowski
2023-06-26 3:26 ` Eric Lin
2023-06-26 6:19 ` Krzysztof Kozlowski
2023-06-28 16:31 ` Eric Lin
2023-07-01 8:22 ` Krzysztof Kozlowski
2023-07-12 11:09 ` Eric Lin
2023-07-12 12:30 ` Krzysztof Kozlowski
2023-07-12 12:48 ` Conor Dooley
2023-07-20 10:16 ` Eric Lin
2023-07-20 9:49 ` Eric Lin [this message]
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