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[31.151.115.246]) by smtp.gmail.com with ESMTPSA id hw20-20020a170907a0d400b007aacfce2a91sm2713110ejc.27.2022.10.31.01.55.13 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 31 Oct 2022 01:55:14 -0700 (PDT) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 31 Oct 2022 09:55:13 +0100 Message-Id: Subject: Re: [PATCH 01/10] arm64: dts: qcom: sm6350: Add resets for SDHCI 1/2 From: "Luca Weiss" To: "Marijn Suijten" , Cc: <~postmarketos/upstreaming@lists.sr.ht>, "AngeloGioacchino Del Regno" , "Konrad Dybcio" , "Martin Botka" , "Jami Kettunen" , "Andy Gross" , "Bjorn Andersson" , "Rob Herring" , "Krzysztof Kozlowski" , "Luca Weiss" , , , X-Mailer: aerc 0.12.0 References: <20221030073232.22726-1-marijn.suijten@somainline.org> <20221030073232.22726-2-marijn.suijten@somainline.org> In-Reply-To: <20221030073232.22726-2-marijn.suijten@somainline.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Sun Oct 30, 2022 at 8:32 AM CET, Marijn Suijten wrote: > Make sure the SDHCI hardware is properly reset before interacting with > it, to protect against any possibly indeterminate state left by the > bootloader. > > Suggested-by: Konrad Dybcio > Signed-off-by: Marijn Suijten Reviewed-by: Luca Weiss Tested-by: Luca Weiss # sm7225-fairphone-fp4 Regards Luca > --- > arch/arm64/boot/dts/qcom/sm6350.dtsi | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/q= com/sm6350.dtsi > index c39de7d3ace0..a3ae765d9781 100644 > --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi > @@ -490,6 +490,7 @@ sdhc_1: mmc@7c4000 { > <&gcc GCC_SDCC1_APPS_CLK>, > <&rpmhcc RPMH_CXO_CLK>; > clock-names =3D "iface", "core", "xo"; > + resets =3D <&gcc GCC_SDCC1_BCR>; > qcom,dll-config =3D <0x000f642c>; > qcom,ddr-config =3D <0x80040868>; > power-domains =3D <&rpmhpd SM6350_CX>; > @@ -1068,6 +1069,7 @@ sdhc_2: mmc@8804000 { > <&gcc GCC_SDCC2_APPS_CLK>, > <&rpmhcc RPMH_CXO_CLK>; > clock-names =3D "iface", "core", "xo"; > + resets =3D <&gcc GCC_SDCC2_BCR>; > interconnects =3D <&aggre2_noc MASTER_SDCC_2 0 &clk_virt SLAVE_EBI_CH= 0 0>, > <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>; > interconnect-names =3D "sdhc-ddr", "cpu-sdhc"; > --=20 > 2.38.1