From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D2971C54EAA for ; Fri, 27 Jan 2023 12:45:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234313AbjA0MpH (ORCPT ); Fri, 27 Jan 2023 07:45:07 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234242AbjA0MpF (ORCPT ); Fri, 27 Jan 2023 07:45:05 -0500 Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 11826EB63 for ; Fri, 27 Jan 2023 04:45:03 -0800 (PST) Received: by mail-ej1-x62f.google.com with SMTP id gs13so2671173ejc.0 for ; Fri, 27 Jan 2023 04:45:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=fairphone.com; s=fair; h=in-reply-to:references:subject:cc:to:from:message-id:date :content-transfer-encoding:mime-version:from:to:cc:subject:date :message-id:reply-to; bh=MX9M/CiZsZu3eRTMUNRiNUGMe4+cADFwlytwC/x09Xc=; b=os9EfhoUhlN0cwLkhc4UfN/DkmnANUL3h3F2KvJkZi3Q+w+c4pMtoSOwGpEUJ/54j4 wNJB1EnnEa0YjAb0JxyfGLx6MpWhuNwUUAD1c56DamRDhTEFyJyp2Krk9fXNC/AeQlLx JCCoKFpHlvnoKyrbDY0NZbh7BN3g/fMLLdm0jx20utBEHhxMwxEgjCgVfgvDeanOwZYO gsNmpKoP4FmbPIPPvAH/h3yfglhCMNyBQlwCYOA0uObCNyw/lnEz7+tyYy3ejcTlb3nz FkNofJA3BqB+nYriT7fYRgV0Cm4VnOGnxiDB5IyqxX5PTPfOPh6xmYlnyJfLTFbquUhW v/Xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:references:subject:cc:to:from:message-id:date :content-transfer-encoding:mime-version:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=MX9M/CiZsZu3eRTMUNRiNUGMe4+cADFwlytwC/x09Xc=; b=J7ZlSWoBC0j3wkdTEYQe0q2RcVYC3eoDbYgfgBLuANYp4JfKSimNFFiQmDHgBcp+h4 xAVdQ1jsEoHEej2SjHq550O4DNYmC1HwbLvx82GSOXOv6odFCfWMZYVID3YHGKlUt1RY 7ConrL6SD8C1Fvq27YJl8HFRBDhZbqV+p1iy3UDnDipKgLnGThKU2QBj6FrFXxXs6D8v tSF1ugN2Od5sai4ySfcygQYbZpMgXdmAXj2e9H3KLufbJovunZn0fnAdbupNcjvX40Ka cmwb6TVoCbZtmtvKhe6/ga+zB+dfQwex8bKk+EeKaycA6rLOzjhIPFhicF4sdY5mC6H8 N6TQ== X-Gm-Message-State: AFqh2koKJr32PuvAj4p5yRiGU+VgefgkXKz9LFX6wvDs+22sdYhmu3Fd mpmbOOHVn6Jc9G4UCClCeW4Ieg== X-Google-Smtp-Source: AMrXdXvW7nFA3CS90qGLU3JsWJZakuYpNGeQO07VRLQjUODbUx6HmFg+u6V4G1MpvDApgx8+3FmrKA== X-Received: by 2002:a17:906:c02:b0:83f:cbc0:1b30 with SMTP id s2-20020a1709060c0200b0083fcbc01b30mr40931496ejf.10.1674823501603; Fri, 27 Jan 2023 04:45:01 -0800 (PST) Received: from localhost (144-178-202-138.static.ef-service.nl. [144.178.202.138]) by smtp.gmail.com with ESMTPSA id my20-20020a1709065a5400b00878465f059dsm2180031ejc.59.2023.01.27.04.45.00 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 27 Jan 2023 04:45:01 -0800 (PST) Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 27 Jan 2023 13:45:00 +0100 Message-Id: From: "Luca Weiss" To: "Bryan O'Donoghue" , "Andy Gross" , "Bjorn Andersson" , "Konrad Dybcio" , "Loic Poulain" , "Robert Foss" , "Rob Herring" , "Krzysztof Kozlowski" Cc: <~postmarketos/upstreaming@lists.sr.ht>, , , , , Subject: Re: [PATCH v2 2/4] arm64: dts: qcom: sm6350: Add camera clock controller X-Mailer: aerc 0.14.0 References: <20221213-sm6350-cci-v2-0-15c2c14c34bb@fairphone.com> <20221213-sm6350-cci-v2-2-15c2c14c34bb@fairphone.com> <3ae863df-3260-4863-d88f-da4d3f442174@linaro.org> In-Reply-To: <3ae863df-3260-4863-d88f-da4d3f442174@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue Jan 24, 2023 at 4:25 PM CET, Bryan O'Donoghue wrote: > On 24/01/2023 14:48, Luca Weiss wrote: > > On Fri Jan 20, 2023 at 5:49 PM CET, Bryan O'Donoghue wrote: > >> On 20/01/2023 13:13, Luca Weiss wrote: > >>> + camcc: clock-controller@ad00000 { > >>> + compatible =3D "qcom,sm6350-camcc"; > >>> + reg =3D <0 0x0ad00000 0 0x16000>; > >>> + clocks =3D <&rpmhcc RPMH_CXO_CLK>; > >>> + #clock-cells =3D <1>; > >>> + #reset-cells =3D <1>; > >>> + #power-domain-cells =3D <1>; > >>> + }; > >> > >> Should you include > >> > >> required-opps =3D <&rpmhpd_opp_low_svs>; > >> > >> ? > >=20 > > I don't know, it works without. But doesn't this property not just > > affect power-domains? I haven't passed any here. > >=20 > > Should you have a TITAN_TOP pd though ? Can I reference <&camcc TITAN_TOP_GDSC> from itself? I know that having it on is required to turn on at least some clocks (maybe all clocks). But from what I understand how power domains are normally handled, the driver core enables them before the driver is probed, so self referencing wouldn't work. And at least no other SoC upstream references TITAN_TOP_GDSC in camcc. Regards Luca > > --- > bod