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Wed, 17 Jul 2024 02:05:10 -0700 (PDT) Received: from localhost ([2a0a:ef40:ee7:2401:197d:e048:a80f:bc44]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3680db048a8sm11095848f8f.111.2024.07.17.02.05.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 17 Jul 2024 02:05:09 -0700 (PDT) Content-Type: text/plain; charset=UTF-8 Date: Wed, 17 Jul 2024 10:05:09 +0100 Message-Id: Cc: , , "Bjorn Andersson" , "Conor Dooley" , "Damien Le Moal" , "de Goede" , "Jens Axboe" , "Konrad Dybcio" , "Krzysztof Kozlowski" , , , "Rob Herring" Subject: Re: [PATCH 1/3] ARM: dts: qcom: {a,i}pq8064: correct clock-names in sata node From: "Rayyan Ansari" To: "Niklas Cassel" Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailer: aerc 0.17.0-0-g6ea74eb30457 References: <20240716105245.49549-1-rayyan.ansari@linaro.org> <20240716105245.49549-2-rayyan.ansari@linaro.org> In-Reply-To: On Wed Jul 17, 2024 at 9:45 AM BST, Niklas Cassel wrote: > On Tue, Jul 16, 2024 at 11:45:59AM +0100, Rayyan Ansari wrote: > > Correct the clock-names in the AHCI SATA controller node to adhere to > > the bindings. > >=20 > > Signed-off-by: Rayyan Ansari > > Hello Rayyan, > > This patch is 1/3, so first in the series. > A patch that is first in the series usually has no other dependencies. > (Unless referencing another series in the cover-letter.) > > So is this a fix that can be sent out separately and picked up the > QCOM maintainers / ARM DT maintainers directly, or does this patch > actually depend on patches 2-3 ? Hi Niklas, Yes, this patch does not depend on the following two patches, I just thought that sending this as a series would make sense given that patches 2-3 would surface this error (as we can run dtbs_check against yaml bindings but not text bindings). > If the former, I suggest that you send out patch 1/3 as a standalone > fix, since it does not need to be blocked by unrelated DT binding > conversion. Ah okay - for v2 I'll send patch 1 on its own, and then patch 2 & 3 as a series. > If the latter, perhaps reorder the patches and improve the commit log > for this patch. > > > Kind regards, > Niklas Thanks, Rayyan > > --- > > arch/arm/boot/dts/qcom/qcom-apq8064.dtsi | 4 ++-- > > arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi | 2 +- > > 2 files changed, 3 insertions(+), 3 deletions(-) > >=20 > > diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/d= ts/qcom/qcom-apq8064.dtsi > > index 81cf387e1817..277bde958d0e 100644 > > --- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > > +++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi > > @@ -889,9 +889,9 @@ sata0: sata@29000000 { > > <&gcc SATA_PMALIVE_CLK>; > > clock-names =3D "slave_iface", > > "iface", > > - "bus", > > + "core", > > "rxoob", > > - "core_pmalive"; > > + "pmalive"; > > =20 > > assigned-clocks =3D <&gcc SATA_RXOOB_CLK>, > > <&gcc SATA_PMALIVE_CLK>; > > diff --git a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi b/arch/arm/boot/d= ts/qcom/qcom-ipq8064.dtsi > > index da0fd75f4711..dd974eb4065f 100644 > > --- a/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi > > +++ b/arch/arm/boot/dts/qcom/qcom-ipq8064.dtsi > > @@ -1292,7 +1292,7 @@ sata: sata@29000000 { > > <&gcc SATA_A_CLK>, > > <&gcc SATA_RXOOB_CLK>, > > <&gcc SATA_PMALIVE_CLK>; > > - clock-names =3D "slave_face", "iface", "core", > > + clock-names =3D "slave_iface", "iface", "core", > > "rxoob", "pmalive"; > > =20 > > assigned-clocks =3D <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>; > > --=20 > > 2.45.2 > >=20