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[89.23.255.189]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-a9ee0e2f3cdsm418712966b.185.2024.11.09.15.31.48 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sat, 09 Nov 2024 15:31:49 -0800 (PST) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Sun, 10 Nov 2024 00:31:48 +0100 Message-Id: Cc: "Bjorn Andersson" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Marijn Suijten" , , , , "Abel Vesa" , "Johan Hovold" To: "Marcus Glocker" , "Konrad Dybcio" From: "Daniel Gomez" Subject: Re: [PATCH v5 4/6] arm64: dts: qcom: Add UFS node X-Mailer: aerc HEAD-434ca29 References: In-Reply-To: On Fri Aug 30, 2024 at 7:25 PM CEST, Marcus Glocker wrote: > On Fri, Aug 30, 2024 at 02:05:48AM +0200, Konrad Dybcio wrote: > >> On 17.08.2024 10:38 PM, Marcus Glocker wrote: >> > Add the UFS Host Controller node. This was basically copied from the >> > arch/arm64/boot/dts/qcom/sc7180.dtsi file. >> > >> > Signed-off-by: Marcus Glocker >> > Acked-by: Krzysztof Kozlowski >> > --- >> > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 72 +++++++++++++++++++++++++= + >> > 1 file changed, 72 insertions(+) >> > >> > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi=20 >> > b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> > index 7bca5fcd7d52..9f01b3ff3737 100644 >> > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi >> > @@ -2878,6 +2878,78 @@ mmss_noc: interconnect@1780000 { >> > #interconnect-cells =3D <2>; >> > }; >> > >> > + ufs_mem_hc: ufs@1d84000 { >> > + compatible =3D "qcom,x1e80100-ufshc", "qcom,ufshc", >> > + "jedec,ufs-2.0"; >> > + reg =3D <0 0x01d84000 0 0x3000>; >> > + interrupts =3D ; >> > + phys =3D <&ufs_mem_phy>; >> > + phy-names =3D "ufsphy"; >> > + lanes-per-direction =3D <1>; >> > + #reset-cells =3D <1>; >> > + resets =3D <&gcc GCC_UFS_PHY_BCR>; >> > + reset-names =3D "rst"; >> > + >> > + power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; >> > + >> > + iommus =3D <&apps_smmu 0xa0 0x0>; >>=20 >> Looks like this should be 0x1a0 maybe >> > + >> > + clock-names =3D "core_clk", >> > + "bus_aggr_clk", >> > + "iface_clk", >> > + "core_clk_unipro", >> > + "ref_clk", >> > + "tx_lane0_sync_clk", >> > + "rx_lane0_sync_clk"; >> > + clocks =3D <&gcc GCC_UFS_PHY_AXI_CLK>, >> > + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, >> > + <&gcc GCC_UFS_PHY_AHB_CLK>, >> > + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, >> > + <&rpmhcc RPMH_CXO_CLK>, >> > + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, >> > + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>; >>=20 >> You also want >>=20 >> <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK> >>=20 >> > + freq-table-hz =3D <50000000 200000000>, >> 25000000 300000000 >>=20 >> > + <0 0>, >> > + <0 0>, >> > + <37500000 150000000>, >> 75000000 300000000 >>=20 >> > + <0 0>, >> > + <0 0>, >> > + <0 0>; >> > + >> > + interconnects =3D <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS >> > + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, >> > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> > + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; >> > + interconnect-names =3D "ufs-ddr", "cpu-ufs"; >> > + >> > + qcom,ice =3D <&ice>; >> > + >> > + status =3D "disabled"; >> > + }; >> > + >> > + ufs_mem_phy: phy@1d87000 { >> > + compatible =3D "qcom,x1e80100-qmp-ufs-phy"; >> > + reg =3D <0 0x01d87000 0 0x1000>; >>=20 >> most definitely should be 0x01d80000 with a size of 0x2000 >>=20 >> > + clocks =3D <&rpmhcc RPMH_CXO_CLK>, >> > + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, >> > + <&tcsr TCSR_UFS_PHY_CLKREF_EN>; >> > + clock-names =3D "ref", >> > + "ref_aux", >> > + "qref"; >> > + power-domains =3D <&gcc GCC_UFS_PHY_GDSC>; >> > + resets =3D <&ufs_mem_hc 0>; >> > + reset-names =3D "ufsphy"; >> > + #phy-cells =3D <0>; >> > + status =3D "disabled"; >> > + }; >> > + >> > + ice: crypto@1d90000 { >> > + compatible =3D "qcom,x1e80100-inline-crypto-engine", >> > + "qcom,inline-crypto-engine"; >> > + reg =3D <0 0x01d90000 0 0x8000>; >>=20 >> 0x1d88000 >>=20 >>=20 >> All this combined means you probably wrote your init sequence into some >> free(?) register space and the one left over from the bootloader was >> good enough :P >>=20 >> Konrad > > I have not done anything special in our sub-system to boot this DTB. > Changing the values as suggested by you also doesn't make any difference > to me. > > Anyway, I think I'll give up at this point, since this process is > getting too time consuming for me. We'll go ahead with out downstream > patches, which works for us so far. Hi Marcus, I came across this and I'd be interested in picking up the patches for test= ing. Is there any guide or documentation available that I could follow to boot L= inux on this machine using this patchset? Also, could you share where I might be= able to find those downstream patches? Thanks, Daniel > > Cheers, > Marcus