From mboxrd@z Thu Jan 1 00:00:00 1970 From: Jingoo Han Subject: Re: [PATCH v6] PCI: Store PCIe bus address in struct of_pci_range Date: Mon, 3 Aug 2015 23:41:20 +0900 Message-ID: References: <1438010223-124422-1-git-send-email-gabriele.paoloni@huawei.com> <20150729172053.GE31170@google.com> <20150730161447.GG9640@google.com> <20150730171445.GI9640@google.com> <55BB8CC6.1080203@ti.com> Mime-Version: 1.0 (1.0) Content-Type: text/plain; charset=euc-kr Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: Sender: linux-pci-owner@vger.kernel.org To: Gabriele Paoloni Cc: Kishon Vijay Abraham I , Rob Herring , Bjorn Helgaas , "arnd@arndb.de" , "lorenzo.pieralisi@arm.com" , "Wangzhou (B)" , "robh+dt@kernel.org" , "james.morse@arm.com" , "Liviu.Dudau@arm.com" , "linux-pci@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , Yuanzhichang , Zhudacai , zhangjukuo , qiuzhenfa , "Liguozhu (Kenneth)" , Pratyush Anand , Arnd Bergmann , "jingoohan1@gmail.com" List-Id: devicetree@vger.kernel.org On 2015. 8. 1., at AM 12:09, Gabriele Paoloni wrote: >=20 >> -----Original Message----- >> From: Kishon Vijay Abraham I [mailto:kishon@ti.com] >> Sent: Friday, July 31, 2015 3:57 PM >> To: Gabriele Paoloni; Rob Herring >> Cc: Bjorn Helgaas; arnd@arndb.de; lorenzo.pieralisi@arm.com; Wangzho= u >> (B); robh+dt@kernel.org; james.morse@arm.com; Liviu.Dudau@arm.com; >> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; >> devicetree@vger.kernel.org; Yuanzhichang; Zhudacai; zhangjukuo; >> qiuzhenfa; Liguozhu (Kenneth); Jingoo Han; Pratyush Anand; Arnd >> Bergmann; Arnd Bergmann >> Subject: Re: [PATCH v6] PCI: Store PCIe bus address in struct >> of_pci_range >>=20 >> +Arnd >>=20 >> Hi, >>=20 >>> On Friday 31 July 2015 07:55 PM, Gabriele Paoloni wrote: >>> [+cc Kishon] >>>=20 >>>> -----Original Message----- >>>> From: linux-pci-owner@vger.kernel.org [mailto:linux-pci- >>>> owner@vger.kernel.org] On Behalf Of Rob Herring >>>> Sent: Thursday, July 30, 2015 9:42 PM >>>> To: Gabriele Paoloni >>>> Cc: Bjorn Helgaas; arnd@arndb.de; lorenzo.pieralisi@arm.com; >> Wangzhou >>>> (B); robh+dt@kernel.org; james.morse@arm.com; Liviu.Dudau@arm.com; >>>> linux-pci@vger.kernel.org; linux-arm-kernel@lists.infradead.org; >>>> devicetree@vger.kernel.org; Yuanzhichang; Zhudacai; zhangjukuo; >>>> qiuzhenfa; Liguozhu (Kenneth); Jingoo Han; Pratyush Anand >>>> Subject: Re: [PATCH v6] PCI: Store PCIe bus address in struct >>>> of_pci_range >>>>=20 >>>> On Thu, Jul 30, 2015 at 12:34 PM, Gabriele Paoloni >>>> wrote: >>>>>> -----Original Message----- >>>>>> From: Bjorn Helgaas [mailto:bhelgaas@google.com] >>>>>> Sent: 30 July 2015 18:15 >>>>>> On Thu, Jul 30, 2015 at 04:50:55PM +0000, Gabriele Paoloni wrote= : >>>>>>>> -----Original Message----- >>>>>>>> From: linux-pci-owner@vger.kernel.org [mailto:linux-pci- >>>>>>>> owner@vger.kernel.org] On Behalf Of Bjorn Helgaas >>>>>>>> Sent: Thursday, July 30, 2015 5:15 PM >>>>>>>> On Thu, Jul 30, 2015 at 01:52:13PM +0000, Gabriele Paoloni wro= te: >>>>=20 >>>> [...] >>>>=20 >>>>>>>>> I don=A1=AFt think we should rely on [CPU] addresses...what i= f the >>>>>>>> intermediate >>>>>>>>> translation layer changes the lower significant bits of the >>>> "bus >>>>>>>> address" >>>>>>>>> to translate into a cpu address? >>>>>>>>=20 >>>>>>>> Is it really a possiblity that the lower bits could be changed= ? >>>>>>>=20 >>>>>>> I've checked all the current deignware users DTs except "pci- >>>>>> layerscape" >>>>>>> that I could not find: >>>>>>> spear1310.dtsi >>>>>>> spear1340.dtsi >>>>>>> dra7.dtsi >>>>>>> imx6qdl.dtsi >>>>>>> imx6sx.dtsi >>>>>>> keystone.dtsi >>>>>>> exynos5440.dtsi >>>>>>>=20 >>>>>>> None of them modifies the lower bits. To be more precise the on= ly >>>> guy >>>>>>> that provides another translation layer is "dra7.dtsi": >>>>>>> axi0 >>>>>>> http://lxr.free- >>>> electrons.com/source/arch/arm/boot/dts/dra7.dtsi#L207 >>>>>>>=20 >>>>>>> axi1 >>>>>>> http://lxr.free- >>>> electrons.com/source/arch/arm/boot/dts/dra7.dtsi#L241 >>>>>>>=20 >>>>>>> For this case masking the top 4bits (bits28 to 31) should make >> the >>>> job. >>>>=20 >>>> IMO, we should just fix this case. After further study, I don't >> think >>>> this is a DW issue, but rather an SOC integration issue. >>>>=20 >>>> I believe you can just fixup the address in the pp->ops->host_init >> hook. Yep, it is SOC specific code for dra7. This is NOT a DW issue. >>>=20 >>> Yes I guess that I could just assign pp->(*)_mod_base to the CPU >> address >>> in DW and mask it out in dra7xx_pcie_host_init()... >>>=20 >>> Kishon, would you be ok with that? >>=20 >> Initially I was using *base-mask* property from dt. Me and Arnd (cc'= ed) >> had >> this discussion [1] before we decided the current approach. It'll be >> good to >> check with Arnd too. >>=20 >> [1] -> http://lists.infradead.org/pipermail/linux-arm-kernel/2014- >> May/253528.html >=20 >=20 > In this patch you use the mask into designware....instead the approac= h=20 > proposed by Rob means to have the mask declared in the dra7 driver an= d > you modified the pp members in dra7xx_pcie_host_init by masking them.= =2E. I want to move that code to dra7 driver, because that code is dra7-specific. Best regards, Jingoo Han > BTW good to have Arnd opinion too.. >>=20 >> Thanks >> Kishon