[PATCH v2 1/4] dt-bindings: clock: fsl-sai: Document i.MX8M support

[PATCH v2 1/4] dt-bindings: clock: fsl-sai: Document i.MX8M support

[Marek Vasut]

The i.MX8M/Mini/Nano/Plus variant of the SAI IP has control registers
shifted by +8 bytes and requires additional bus clock. Document support
for the i.MX8M variant of the IP with this register shift and additional
clock. Update the description slightly.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Nicolin Chen <nicoleotsuka@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Shengjiu Wang <shengjiu.wang@gmail.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Takashi Iwai <tiwai@suse.com>
Cc: Xiubo Li <Xiubo.Lee@gmail.com>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-sound@vger.kernel.org
---
V2: No change
---
 .../bindings/clock/fsl,sai-clock.yaml         | 32 ++++++++++++++++---
 1 file changed, 27 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
index 3bca9d11c148f..e62543deeb7da 100644
--- a/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
@@ -10,10 +10,10 @@ maintainers:
   - Michael Walle <michael@walle.cc>
 
 description: |
-  It is possible to use the BCLK pin of a SAI module as a generic clock
-  output. Some SoC are very constrained in their pin multiplexer
-  configuration. Eg. pins can only be changed groups. For example, on the
-  LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
+  It is possible to use the BCLK pin of a SAI module as a generic
+  clock output. Some SoC are very constrained in their pin multiplexer
+  configuration. E.g. pins can only be changed in groups. For example, on
+  the LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
   the second pins are wasted. Using this binding it is possible to use the
   clock of the second SAI as a MCLK clock for an audio codec, for example.
 
@@ -21,7 +21,17 @@ description: |
 
 properties:
   compatible:
-    const: fsl,vf610-sai-clock
+    oneOf:
+      - items:
+          - enum:
+              - fsl,imx8mm-sai-clock
+              - fsl,imx8mn-sai-clock
+              - fsl,imx8mp-sai-clock
+          - const: fsl,imx8mq-sai-clock
+      - items:
+          - enum:
+              - fsl,imx8mq-sai-clock
+              - fsl,vf610-sai-clock
 
   reg:
     maxItems: 1
@@ -32,6 +42,18 @@ properties:
   '#clock-cells':
     const: 0
 
+allOf:
+  - if:
+      not:
+        properties:
+          compatible:
+            contains:
+              const: fsl,imx8mq-sai-clock
+    then:
+      properties:
+        clocks:
+          maxItems: 2
+
 required:
   - compatible
   - reg
-- 
2.45.2

[PATCH v2 2/4] clk: fsl-sai: Add i.MX8M support with 8 byte register offset

[Marek Vasut]

The i.MX8M/Mini/Nano/Plus variant of the SAI IP has control registers
shifted by +8 bytes and requires additional bus clock. Add support for
the i.MX8M variant of the IP with this register shift and additional
clock.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Nicolin Chen <nicoleotsuka@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Shengjiu Wang <shengjiu.wang@gmail.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Takashi Iwai <tiwai@suse.com>
Cc: Xiubo Li <Xiubo.Lee@gmail.com>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-sound@vger.kernel.org
---
V2: Update commit message, align it with the bindings one
---
 drivers/clk/Kconfig       |  2 +-
 drivers/clk/clk-fsl-sai.c | 22 ++++++++++++++++++----
 2 files changed, 19 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 713573b6c86c7..575743d7e2c71 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -247,7 +247,7 @@ config COMMON_CLK_FSL_FLEXSPI
 
 config COMMON_CLK_FSL_SAI
 	bool "Clock driver for BCLK of Freescale SAI cores"
-	depends on ARCH_LAYERSCAPE || COMPILE_TEST
+	depends on ARCH_LAYERSCAPE || ARCH_MXC || COMPILE_TEST
 	help
 	  This driver supports the Freescale SAI (Synchronous Audio Interface)
 	  to be used as a generic clock output. Some SoCs have restrictions
diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c
index cba45e07562da..628e53a3a26fa 100644
--- a/drivers/clk/clk-fsl-sai.c
+++ b/drivers/clk/clk-fsl-sai.c
@@ -26,9 +26,14 @@ struct fsl_sai_clk {
 	spinlock_t lock;
 };
 
+struct fsl_sai_data {
+	unsigned int	offset;	/* Register offset */
+};
+
 static int fsl_sai_clk_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
+	const struct fsl_sai_data *data = device_get_match_data(dev);
 	struct fsl_sai_clk *sai_clk;
 	struct clk_parent_data pdata = { .index = 0 };
 	void __iomem *base;
@@ -44,17 +49,17 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
 
 	spin_lock_init(&sai_clk->lock);
 
-	sai_clk->gate.reg = base + I2S_CSR;
+	sai_clk->gate.reg = base + data->offset + I2S_CSR;
 	sai_clk->gate.bit_idx = CSR_BCE_BIT;
 	sai_clk->gate.lock = &sai_clk->lock;
 
-	sai_clk->div.reg = base + I2S_CR2;
+	sai_clk->div.reg = base + data->offset + I2S_CR2;
 	sai_clk->div.shift = CR2_DIV_SHIFT;
 	sai_clk->div.width = CR2_DIV_WIDTH;
 	sai_clk->div.lock = &sai_clk->lock;
 
 	/* set clock direction, we are the BCLK master */
-	writel(CR2_BCD, base + I2S_CR2);
+	writel(CR2_BCD, base + data->offset + I2S_CR2);
 
 	hw = devm_clk_hw_register_composite_pdata(dev, dev->of_node->name,
 						  &pdata, 1, NULL, NULL,
@@ -69,8 +74,17 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
 	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
 }
 
+static const struct fsl_sai_data fsl_sai_vf610_data = {
+	.offset	= 0,
+};
+
+static const struct fsl_sai_data fsl_sai_imx8mq_data = {
+	.offset	= 8,
+};
+
 static const struct of_device_id of_fsl_sai_clk_ids[] = {
-	{ .compatible = "fsl,vf610-sai-clock" },
+	{ .compatible = "fsl,vf610-sai-clock", .data = &fsl_sai_vf610_data },
+	{ .compatible = "fsl,imx8mq-sai-clock", .data = &fsl_sai_imx8mq_data },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, of_fsl_sai_clk_ids);
-- 
2.45.2

[PATCH v2 3/4] dt-bindings: clock: fsl-sai: Document clock-cells = <1> support

[Marek Vasut]

The driver now supports generation of both BCLK and MCLK, document
support for #clock-cells = <0> for legacy case and #clock-cells = <1>
for the new case which can differentiate between BCLK and MCLK.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Nicolin Chen <nicoleotsuka@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Shengjiu Wang <shengjiu.wang@gmail.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Takashi Iwai <tiwai@suse.com>
Cc: Xiubo Li <Xiubo.Lee@gmail.com>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-sound@vger.kernel.org
---
V2: No change
---
 Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
index e62543deeb7da..250d7ec729c6e 100644
--- a/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/fsl,sai-clock.yaml
@@ -10,7 +10,7 @@ maintainers:
   - Michael Walle <michael@walle.cc>
 
 description: |
-  It is possible to use the BCLK pin of a SAI module as a generic
+  It is possible to use the BCLK or MCLK pin of a SAI module as a generic
   clock output. Some SoC are very constrained in their pin multiplexer
   configuration. E.g. pins can only be changed in groups. For example, on
   the LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
@@ -40,7 +40,7 @@ properties:
     maxItems: 1
 
   '#clock-cells':
-    const: 0
+    maximum: 1
 
 allOf:
   - if:
-- 
2.45.2

[PATCH v2 4/4] clk: fsl-sai: Add MCLK generation support

[Marek Vasut]

The driver currently supports generating BCLK. There are systems which
require generation of MCLK instead. Register new MCLK clock and handle
clock-cells = <1> to differentiate between BCLK and MCLK. In case of a
legacy system with clock-cells = <0>, the driver behaves as before, i.e.
always returns BCLK.

Signed-off-by: Marek Vasut <marex@denx.de>
---
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Jaroslav Kysela <perex@perex.cz>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Liam Girdwood <lgirdwood@gmail.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Michael Walle <michael@walle.cc>
Cc: Nicolin Chen <nicoleotsuka@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Shengjiu Wang <shengjiu.wang@gmail.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Takashi Iwai <tiwai@suse.com>
Cc: Xiubo Li <Xiubo.Lee@gmail.com>
Cc: devicetree@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: linux-sound@vger.kernel.org
---
V2: No change
---
 drivers/clk/clk-fsl-sai.c | 81 ++++++++++++++++++++++++++++++++-------
 1 file changed, 67 insertions(+), 14 deletions(-)

diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c
index 628e53a3a26fa..0f8e2f2662d87 100644
--- a/drivers/clk/clk-fsl-sai.c
+++ b/drivers/clk/clk-fsl-sai.c
@@ -7,6 +7,7 @@
 
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/clk.h>
 #include <linux/clk-provider.h>
 #include <linux/err.h>
 #include <linux/of.h>
@@ -15,27 +16,44 @@
 
 #define I2S_CSR		0x00
 #define I2S_CR2		0x08
+#define I2S_MCR		0x100
 #define CSR_BCE_BIT	28
+#define CSR_TE_BIT	31
 #define CR2_BCD		BIT(24)
 #define CR2_DIV_SHIFT	0
 #define CR2_DIV_WIDTH	8
+#define MCR_MOE		BIT(30)
 
 struct fsl_sai_clk {
-	struct clk_divider div;
-	struct clk_gate gate;
+	struct clk_divider bclk_div;
+	struct clk_divider mclk_div;
+	struct clk_gate bclk_gate;
+	struct clk_gate mclk_gate;
+	struct clk_hw *bclk_hw;
+	struct clk_hw *mclk_hw;
 	spinlock_t lock;
 };
 
 struct fsl_sai_data {
 	unsigned int	offset;	/* Register offset */
+	bool		have_mclk; /* Have MCLK control */
 };
 
+static struct clk_hw *
+fsl_sai_of_clk_get(struct of_phandle_args *clkspec, void *data)
+{
+	struct fsl_sai_clk *sai_clk = data;
+
+	return clkspec->args[0] ? sai_clk->mclk_hw : sai_clk->bclk_hw;
+}
+
 static int fsl_sai_clk_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	const struct fsl_sai_data *data = device_get_match_data(dev);
-	struct fsl_sai_clk *sai_clk;
 	struct clk_parent_data pdata = { .index = 0 };
+	struct fsl_sai_clk *sai_clk;
+	struct clk *clk_bus;
 	void __iomem *base;
 	struct clk_hw *hw;
 
@@ -47,39 +65,74 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
 	if (IS_ERR(base))
 		return PTR_ERR(base);
 
+	clk_bus = devm_clk_get_enabled(dev, "bus");
+	if (IS_ERR(clk_bus))
+		return PTR_ERR(clk_bus);
+
 	spin_lock_init(&sai_clk->lock);
 
-	sai_clk->gate.reg = base + data->offset + I2S_CSR;
-	sai_clk->gate.bit_idx = CSR_BCE_BIT;
-	sai_clk->gate.lock = &sai_clk->lock;
+	sai_clk->bclk_gate.reg = base + data->offset + I2S_CSR;
+	sai_clk->bclk_gate.bit_idx = CSR_BCE_BIT;
+	sai_clk->bclk_gate.lock = &sai_clk->lock;
 
-	sai_clk->div.reg = base + data->offset + I2S_CR2;
-	sai_clk->div.shift = CR2_DIV_SHIFT;
-	sai_clk->div.width = CR2_DIV_WIDTH;
-	sai_clk->div.lock = &sai_clk->lock;
+	sai_clk->bclk_div.reg = base + data->offset + I2S_CR2;
+	sai_clk->bclk_div.shift = CR2_DIV_SHIFT;
+	sai_clk->bclk_div.width = CR2_DIV_WIDTH;
+	sai_clk->bclk_div.lock = &sai_clk->lock;
 
 	/* set clock direction, we are the BCLK master */
 	writel(CR2_BCD, base + data->offset + I2S_CR2);
 
-	hw = devm_clk_hw_register_composite_pdata(dev, dev->of_node->name,
+	hw = devm_clk_hw_register_composite_pdata(dev, "BCLK",
 						  &pdata, 1, NULL, NULL,
-						  &sai_clk->div.hw,
+						  &sai_clk->bclk_div.hw,
 						  &clk_divider_ops,
-						  &sai_clk->gate.hw,
+						  &sai_clk->bclk_gate.hw,
 						  &clk_gate_ops,
 						  CLK_SET_RATE_GATE);
 	if (IS_ERR(hw))
 		return PTR_ERR(hw);
 
-	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, hw);
+	sai_clk->bclk_hw = hw;
+
+	if (data->have_mclk) {
+		sai_clk->mclk_gate.reg = base + data->offset + I2S_CSR;
+		sai_clk->mclk_gate.bit_idx = CSR_TE_BIT;
+		sai_clk->mclk_gate.lock = &sai_clk->lock;
+
+		sai_clk->mclk_div.reg = base + I2S_MCR;
+		sai_clk->mclk_div.shift = CR2_DIV_SHIFT;
+		sai_clk->mclk_div.width = CR2_DIV_WIDTH;
+		sai_clk->mclk_div.lock = &sai_clk->lock;
+
+		pdata.index = 1; /* MCLK1 */
+		hw = devm_clk_hw_register_composite_pdata(dev, "MCLK",
+							  &pdata, 1, NULL, NULL,
+							  &sai_clk->mclk_div.hw,
+							  &clk_divider_ops,
+							  &sai_clk->mclk_gate.hw,
+							  &clk_gate_ops,
+							  CLK_SET_RATE_GATE);
+		if (IS_ERR(hw))
+			return PTR_ERR(hw);
+
+		sai_clk->mclk_hw = hw;
+
+		/* set clock direction, we are the MCLK output */
+		writel(MCR_MOE, base + I2S_MCR);
+	}
+
+	return devm_of_clk_add_hw_provider(dev, fsl_sai_of_clk_get, sai_clk);
 }
 
 static const struct fsl_sai_data fsl_sai_vf610_data = {
 	.offset	= 0,
+	.have_mclk = false,
 };
 
 static const struct fsl_sai_data fsl_sai_imx8mq_data = {
 	.offset	= 8,
+	.have_mclk = true,
 };
 
 static const struct of_device_id of_fsl_sai_clk_ids[] = {
-- 
2.45.2

Re: [PATCH v2 3/4] dt-bindings: clock: fsl-sai: Document clock-cells = <1> support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 377 bytes --]

On Thu, Dec 26, 2024 at 05:22:23PM +0100, Marek Vasut wrote:
> The driver now supports generation of both BCLK and MCLK, document
> support for #clock-cells = <0> for legacy case and #clock-cells = <1>
> for the new case which can differentiate between BCLK and MCLK.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v2 1/4] dt-bindings: clock: fsl-sai: Document i.MX8M support

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 434 bytes --]

On Thu, Dec 26, 2024 at 05:22:21PM +0100, Marek Vasut wrote:
> The i.MX8M/Mini/Nano/Plus variant of the SAI IP has control registers
> shifted by +8 bytes and requires additional bus clock. Document support
> for the i.MX8M variant of the IP with this register shift and additional
> clock. Update the description slightly.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v2 4/4] clk: fsl-sai: Add MCLK generation support

[Marek Vasut]

On 12/30/24 2:28 AM, Peng Fan wrote:

[...]

>> static int fsl_sai_clk_probe(struct platform_device *pdev)
>> {
>> 	struct device *dev = &pdev->dev;
>> 	const struct fsl_sai_data *data = device_get_match_data(dev);
>> -	struct fsl_sai_clk *sai_clk;
>> 	struct clk_parent_data pdata = { .index = 0 };
>> +	struct fsl_sai_clk *sai_clk;
>> +	struct clk *clk_bus;
>> 	void __iomem *base;
>> 	struct clk_hw *hw;
>>
>> @@ -47,39 +65,74 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
>> 	if (IS_ERR(base))
>> 		return PTR_ERR(base);
>>
>> +	clk_bus = devm_clk_get_enabled(dev, "bus");
>> +	if (IS_ERR(clk_bus))
>> +		return PTR_ERR(clk_bus);
>> +
> 
> This only applies to i.MX?
I think so ... what am I missing , some Vybrid / Layerscape detail ?

Re: [PATCH v2 2/4] clk: fsl-sai: Add i.MX8M support with 8 byte register offset

[Peng Fan]

On Thu, Dec 26, 2024 at 05:22:22PM +0100, Marek Vasut wrote:
>The i.MX8M/Mini/Nano/Plus variant of the SAI IP has control registers
>shifted by +8 bytes and requires additional bus clock. Add support for
>the i.MX8M variant of the IP with this register shift and additional
>clock.
>
>Signed-off-by: Marek Vasut <marex@denx.de>

Reviewed-by: Peng Fan <peng.fan@nxp.com>

Re: [PATCH v2 4/4] clk: fsl-sai: Add MCLK generation support

[Peng Fan]

On Thu, Dec 26, 2024 at 05:22:24PM +0100, Marek Vasut wrote:
>The driver currently supports generating BCLK. There are systems which
>require generation of MCLK instead. Register new MCLK clock and handle
>clock-cells = <1> to differentiate between BCLK and MCLK. In case of a
>legacy system with clock-cells = <0>, the driver behaves as before, i.e.
>always returns BCLK.
>
>Signed-off-by: Marek Vasut <marex@denx.de>
>---
>Cc: Conor Dooley <conor+dt@kernel.org>
>Cc: Fabio Estevam <festevam@gmail.com>
>Cc: Jaroslav Kysela <perex@perex.cz>
>Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
>Cc: Liam Girdwood <lgirdwood@gmail.com>
>Cc: Mark Brown <broonie@kernel.org>
>Cc: Michael Turquette <mturquette@baylibre.com>
>Cc: Michael Walle <michael@walle.cc>
>Cc: Nicolin Chen <nicoleotsuka@gmail.com>
>Cc: Rob Herring <robh@kernel.org>
>Cc: Shengjiu Wang <shengjiu.wang@gmail.com>
>Cc: Stephen Boyd <sboyd@kernel.org>
>Cc: Takashi Iwai <tiwai@suse.com>
>Cc: Xiubo Li <Xiubo.Lee@gmail.com>
>Cc: devicetree@vger.kernel.org
>Cc: linux-clk@vger.kernel.org
>Cc: linux-sound@vger.kernel.org
>---
>V2: No change
>---
> drivers/clk/clk-fsl-sai.c | 81 ++++++++++++++++++++++++++++++++-------
> 1 file changed, 67 insertions(+), 14 deletions(-)
>
>diff --git a/drivers/clk/clk-fsl-sai.c b/drivers/clk/clk-fsl-sai.c
>index 628e53a3a26fa..0f8e2f2662d87 100644
>--- a/drivers/clk/clk-fsl-sai.c
>+++ b/drivers/clk/clk-fsl-sai.c
>@@ -7,6 +7,7 @@
> 
> #include <linux/module.h>
> #include <linux/platform_device.h>
>+#include <linux/clk.h>
> #include <linux/clk-provider.h>
> #include <linux/err.h>
> #include <linux/of.h>
>@@ -15,27 +16,44 @@
> 
> #define I2S_CSR		0x00
> #define I2S_CR2		0x08
>+#define I2S_MCR		0x100
> #define CSR_BCE_BIT	28
>+#define CSR_TE_BIT	31
> #define CR2_BCD		BIT(24)
> #define CR2_DIV_SHIFT	0
> #define CR2_DIV_WIDTH	8
>+#define MCR_MOE		BIT(30)
> 
> struct fsl_sai_clk {
>-	struct clk_divider div;
>-	struct clk_gate gate;
>+	struct clk_divider bclk_div;
>+	struct clk_divider mclk_div;
>+	struct clk_gate bclk_gate;
>+	struct clk_gate mclk_gate;
>+	struct clk_hw *bclk_hw;
>+	struct clk_hw *mclk_hw;
> 	spinlock_t lock;
> };
> 
> struct fsl_sai_data {
> 	unsigned int	offset;	/* Register offset */
>+	bool		have_mclk; /* Have MCLK control */
> };
> 
>+static struct clk_hw *
>+fsl_sai_of_clk_get(struct of_phandle_args *clkspec, void *data)
>+{
>+	struct fsl_sai_clk *sai_clk = data;
>+
>+	return clkspec->args[0] ? sai_clk->mclk_hw : sai_clk->bclk_hw;
>+}
>+
> static int fsl_sai_clk_probe(struct platform_device *pdev)
> {
> 	struct device *dev = &pdev->dev;
> 	const struct fsl_sai_data *data = device_get_match_data(dev);
>-	struct fsl_sai_clk *sai_clk;
> 	struct clk_parent_data pdata = { .index = 0 };
>+	struct fsl_sai_clk *sai_clk;
>+	struct clk *clk_bus;
> 	void __iomem *base;
> 	struct clk_hw *hw;
> 
>@@ -47,39 +65,74 @@ static int fsl_sai_clk_probe(struct platform_device *pdev)
> 	if (IS_ERR(base))
> 		return PTR_ERR(base);
> 
>+	clk_bus = devm_clk_get_enabled(dev, "bus");
>+	if (IS_ERR(clk_bus))
>+		return PTR_ERR(clk_bus);
>+

This only applies to i.MX? 

> 	spin_lock_init(&sai_clk->lock);
> 

Regards,
Peng

Re: [PATCH v2 4/4] clk: fsl-sai: Add MCLK generation support

[Michael Walle]

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Hi Marek,

On Thu Dec 26, 2024 at 5:22 PM CET, Marek Vasut wrote:
> The driver currently supports generating BCLK.

I'd say the driver supports generating *any* clock on the BCLK pin.
It's not necessarily the BCLK clock. I.e. on the board where this is
used, this is the clock with a given frequency sourcing the PLL in
the audio codec.

> There are systems which require generation of MCLK instead.

You mean systems that use the MCLK pin instead? ..Which is the
normal use case for this pin. This driver was created because the
LS1028A doesn't have a MCLK pin, so we've "misused" the BCLK pin,
with the restriction that only integer dividers are possible. I
haven't looked at the datasheet, but doesn't the MCLK has a PLL
which could generate any frequency? Also I'd expect that the imx
SoCs already supports the MCLK for audio applications. Isn't that
the case?

> Register new MCLK clock and handle
> clock-cells = <1> to differentiate between BCLK and MCLK. In case of a
> legacy system with clock-cells = <0>, the driver behaves as before, i.e.
> always returns BCLK.

-michael

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Re: [PATCH v2 4/4] clk: fsl-sai: Add MCLK generation support

[Marek Vasut]

On 12/30/24 8:51 AM, Michael Walle wrote:
> Hi Marek,

Hi,

> On Thu Dec 26, 2024 at 5:22 PM CET, Marek Vasut wrote:
>> The driver currently supports generating BCLK.
> 
> I'd say the driver supports generating *any* clock on the BCLK pin.

The clock are coming out of the SAI 'BCLK' output and are controlled by 
the SAI BCLK control bits. Of course, it is possible to feed arbitrary 
upstream clock into the SAI and have those exposed on the BCLK pin. I'll 
try to reword the commit message to make that clearer.

> It's not necessarily the BCLK clock. I.e. on the board where this is
> used, this is the clock with a given frequency sourcing the PLL in
> the audio codec.

Right

>> There are systems which require generation of MCLK instead.
> 
> You mean systems that use the MCLK pin instead?

Yes

> ..Which is the
> normal use case for this pin. This driver was created because the
> LS1028A doesn't have a MCLK pin, so we've "misused" the BCLK pin,
> with the restriction that only integer dividers are possible.

I have a system that is wired a bit unfortunately, I need to source 
codec clock, where the codec is the clock consumer and needs to be able 
to control the clock (SGTL5000). SAI MCLK is the only way I can get them 
out of the pin I need, hence this patch.

> I
> haven't looked at the datasheet, but doesn't the MCLK has a PLL
> which could generate any frequency?

Audio PLL , sure.

> Also I'd expect that the imx
> SoCs already supports the MCLK for audio applications. Isn't that
> the case?

That does not work if the MCLK has to be enabled/disabled by the MCLK 
clock consumer .

[...]

Re: [PATCH v2 4/4] clk: fsl-sai: Add MCLK generation support

[Michael Walle]

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Hi,

> > ..Which is the
> > normal use case for this pin. This driver was created because the
> > LS1028A doesn't have a MCLK pin, so we've "misused" the BCLK pin,
> > with the restriction that only integer dividers are possible.
>
> I have a system that is wired a bit unfortunately, I need to source 
> codec clock, where the codec is the clock consumer and needs to be able 
> to control the clock (SGTL5000). SAI MCLK is the only way I can get them 
> out of the pin I need, hence this patch.

Which is also the default case, no?

> > Also I'd expect that the imx
> > SoCs already supports the MCLK for audio applications. Isn't that
> > the case?
>
> That does not work if the MCLK has to be enabled/disabled by the MCLK 
> clock consumer .

Why's that?

Don't get me wrong. I don't have anything against this patch, I'm
just confused, why that isn't already working with the current MCLK
driver as this seems to be the usual requirements.

-michael

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Re: [PATCH v2 4/4] clk: fsl-sai: Add MCLK generation support

[Marek Vasut]

On 1/2/25 10:58 AM, Michael Walle wrote:
> Hi,

Hi,

>>> ..Which is the
>>> normal use case for this pin. This driver was created because the
>>> LS1028A doesn't have a MCLK pin, so we've "misused" the BCLK pin,
>>> with the restriction that only integer dividers are possible.
>>
>> I have a system that is wired a bit unfortunately, I need to source
>> codec clock, where the codec is the clock consumer and needs to be able
>> to control the clock (SGTL5000). SAI MCLK is the only way I can get them
>> out of the pin I need, hence this patch.
> 
> Which is also the default case, no?

Not quite, there is a difference.

If SAI (audio driver) is used to control the MCLK enablement, then MCLK 
clock is not always enabled, and it is not necessarily enabled when the 
codec may need the clock to be enabled. There is also no way for the 
codec node to specify phandle to clock provider in DT, because the SAI 
(audio driver) is not clock provider.

If SAI (clock driver) is used to control the MCLK enablement, then MCLK 
clock is enabled when the codec needs the clock enabled, because the 
codec is the clock consumer and the SAI (clock driver) is the clock 
provider, and the codec driver can request the clock to be enabled when 
needed. There is also the usual phandle to clock provider in DT, because 
the SAI (clock driver) is clock provider.

>>> Also I'd expect that the imx
>>> SoCs already supports the MCLK for audio applications. Isn't that
>>> the case?
>>
>> That does not work if the MCLK has to be enabled/disabled by the MCLK
>> clock consumer .
> 
> Why's that?
> 
> Don't get me wrong. I don't have anything against this patch, I'm
> just confused, why that isn't already working with the current MCLK
> driver as this seems to be the usual requirements.
Which current MCLK driver, the SAI in audio driver role ?

Does the paragraph in the middle of this email possibly answer this 
question ?

Re: [PATCH v2 4/4] clk: fsl-sai: Add MCLK generation support

[Michael Walle]

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On Thu Jan 2, 2025 at 2:34 PM CET, Marek Vasut wrote:
> On 1/2/25 10:58 AM, Michael Walle wrote:
> > Hi,
>
> Hi,
>
> >>> ..Which is the
> >>> normal use case for this pin. This driver was created because the
> >>> LS1028A doesn't have a MCLK pin, so we've "misused" the BCLK pin,
> >>> with the restriction that only integer dividers are possible.
> >>
> >> I have a system that is wired a bit unfortunately, I need to source
> >> codec clock, where the codec is the clock consumer and needs to be able
> >> to control the clock (SGTL5000). SAI MCLK is the only way I can get them
> >> out of the pin I need, hence this patch.
> > 
> > Which is also the default case, no?
>
> Not quite, there is a difference.
>
> If SAI (audio driver) is used to control the MCLK enablement, then MCLK 
> clock is not always enabled, and it is not necessarily enabled when the 
> codec may need the clock to be enabled. There is also no way for the 
> codec node to specify phandle to clock provider in DT, because the SAI 
> (audio driver) is not clock provider.
>
> If SAI (clock driver) is used to control the MCLK enablement, then MCLK 
> clock is enabled when the codec needs the clock enabled, because the 
> codec is the clock consumer and the SAI (clock driver) is the clock 
> provider, and the codec driver can request the clock to be enabled when 
> needed. There is also the usual phandle to clock provider in DT, because 
> the SAI (clock driver) is clock provider.
>
> >>> Also I'd expect that the imx
> >>> SoCs already supports the MCLK for audio applications. Isn't that
> >>> the case?
> >>
> >> That does not work if the MCLK has to be enabled/disabled by the MCLK
> >> clock consumer .
> > 
> > Why's that?
> > 
> > Don't get me wrong. I don't have anything against this patch, I'm
> > just confused, why that isn't already working with the current MCLK
> > driver as this seems to be the usual requirements.
> Which current MCLK driver, the SAI in audio driver role ?

Yes.

> Does the paragraph in the middle of this email possibly answer this 
> question ?

Yes thanks!

For reference, IMHO the correct way to do it would be to add clock
provider support to the original SAI, esp. because both drivers are
mutually exclusive. But I'm fine to add MCLK support for this driver
for hardware which has a spare SAI and to just use that as a MCLK
source.

Acked-by: Michael Walle <mwalle@kernel.org>

-michael

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