[PATCH 0/4] media: i2c: Add driver for Sony IMX728

[PATCH 0/4] media: i2c: Add driver for Sony IMX728

[Sebastian LaVine]

This series adds a V4L2 sensor driver for the Sony IMX728, and related
devicetree overlays.

v4l2-compliance 1.26.1-5142, 64 bits, 64-bit time_t
v4l2-compliance SHA: 4aee01a02792 2023-12-12 21:40:38

Compliance test for device /dev/v4l-subdev4:

Driver Info:
        Driver version   : 6.12.9
        Capabilities     : 0x00000000

Required ioctls:
        test VIDIOC_SUDBEV_QUERYCAP: OK
        test invalid ioctls: OK

Allow for multiple opens:
        test second /dev/v4l-subdev4 open: OK
        test VIDIOC_SUBDEV_QUERYCAP: OK
        test for unlimited opens: OK

Debug ioctls:
        test VIDIOC_LOG_STATUS: OK (Not Supported)

Input ioctls:
        test VIDIOC_G/S_TUNER/ENUM_FREQ_BANDS: OK (Not Supported)
        test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
        test VIDIOC_S_HW_FREQ_SEEK: OK (Not Supported)
        test VIDIOC_ENUMAUDIO: OK (Not Supported)
        test VIDIOC_G/S/ENUMINPUT: OK (Not Supported)
        test VIDIOC_G/S_AUDIO: OK (Not Supported)
        Inputs: 0 Audio Inputs: 0 Tuners: 0

Output ioctls:
        test VIDIOC_G/S_MODULATOR: OK (Not Supported)
        test VIDIOC_G/S_FREQUENCY: OK (Not Supported)
        test VIDIOC_ENUMAUDOUT: OK (Not Supported)
        test VIDIOC_G/S/ENUMOUTPUT: OK (Not Supported)
        test VIDIOC_G/S_AUDOUT: OK (Not Supported)
        Outputs: 0 Audio Outputs: 0 Modulators: 0

Input/Output configuration ioctls:
        test VIDIOC_ENUM/G/S/QUERY_STD: OK (Not Supported)
        test VIDIOC_ENUM/G/S/QUERY_DV_TIMINGS: OK (Not Supported)
        test VIDIOC_DV_TIMINGS_CAP: OK (Not Supported)
        test VIDIOC_G/S_EDID: OK (Not Supported)

Control ioctls:
        test VIDIOC_QUERY_EXT_CTRL/QUERYMENU: OK
        test VIDIOC_QUERYCTRL: OK
        test VIDIOC_G/S_CTRL: OK
        test VIDIOC_G/S/TRY_EXT_CTRLS: OK
        test VIDIOC_(UN)SUBSCRIBE_EVENT/DQEVENT: OK
        test VIDIOC_G/S_JPEGCOMP: OK (Not Supported)
        Standard Controls: 9 Private Controls: 0

Format ioctls:
        test VIDIOC_ENUM_FMT/FRAMESIZES/FRAMEINTERVALS: OK (Not Supported)
        test VIDIOC_G/S_PARM: OK (Not Supported)
        test VIDIOC_G_FBUF: OK (Not Supported)
        test VIDIOC_G_FMT: OK (Not Supported)
        test VIDIOC_TRY_FMT: OK (Not Supported)
        test VIDIOC_S_FMT: OK (Not Supported)
        test VIDIOC_G_SLICED_VBI_CAP: OK (Not Supported)
        test Cropping: OK (Not Supported)
        test Composing: OK (Not Supported)
        test Scaling: OK (Not Supported)

Codec ioctls:
        test VIDIOC_(TRY_)ENCODER_CMD: OK (Not Supported)
        test VIDIOC_G_ENC_INDEX: OK (Not Supported)
        test VIDIOC_(TRY_)DECODER_CMD: OK (Not Supported)

Buffer ioctls:
        test VIDIOC_REQBUFS/CREATE_BUFS/QUERYBUF: OK (Not Supported)
        test CREATE_BUFS maximum buffers: OK
        test VIDIOC_EXPBUF: OK (Not Supported)
        test Requests: OK (Not Supported)

Total for device /dev/v4l-subdev4: 44, Succeeded: 44, Failed: 0, Warnings: 0


This is a v3 of a series that was originally sent last summer[0].

[0]: https://lore.kernel.org/r/linux-media/20240628-imx728-driver-v2-0-80efa6774286@d3engineering.com/

v2 -> v3:
- Update maintainer
- Update bindings example
- Add devicetree overlays
- The driver now supports SRGGB12_1X12, not SRGGB10_1X10
- The driver now outputs at 3856x2176, not 2840x2160
- Fixed exposure, again controls
- Removed duplicate register writes (removed repeat HDR writes, etc)
- Fixed imx728_wait_for_state use of the cci_* API
- Re-added _imx728_set_routing (necessary for imx728_init_state)

Sebastian LaVine (4):
  media: dt-bindings: Add Sony IMX728
  media: i2c: Add driver for Sony IMX728
  arm64: dts: ti: k3-am62a7-sk: Add overlay for fusion 2 board
  arm64: dts: ti: Add overlays for IMX728 RCM

 .../bindings/media/i2c/sony,imx728.yaml       |   96 +
 MAINTAINERS                                   |    9 +
 arch/arm64/boot/dts/ti/Makefile               |    4 +
 .../boot/dts/ti/k3-am62a7-sk-fusion-2.dtso    |  115 +
 .../dts/ti/k3-fpdlink-imx728-rcm-0-0.dtso     |  108 +
 arch/arm64/configs/defconfig                  |    1 +
 drivers/media/i2c/Kconfig                     |   12 +
 drivers/media/i2c/Makefile                    |    1 +
 drivers/media/i2c/imx728.c                    | 9655 +++++++++++++++++
 9 files changed, 10001 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
 create mode 100644 arch/arm64/boot/dts/ti/k3-fpdlink-imx728-rcm-0-0.dtso
 create mode 100644 drivers/media/i2c/imx728.c

--
2.34.1
Please be aware that this email includes email addresses outside of the organization.

[PATCH 1/4] media: dt-bindings: Add Sony IMX728

[Sebastian LaVine]

Adds bindings for the Sony IMX728.

Signed-off-by: Sebastian LaVine <slavine@d3embedded.com>
Mentored-by: Stuart Burtner <sburtner@d3embedded.com>
---
 .../bindings/media/i2c/sony,imx728.yaml       | 96 +++++++++++++++++++
 MAINTAINERS                                   |  6 ++
 2 files changed, 102 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml

diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml
new file mode 100644
index 000000000000..f76000ed7bff
--- /dev/null
+++ b/Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/sony,imx728.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sony IMX728 Camera Sensor
+
+maintainers:
+  - Stuart Burtner <sburtner@d3embedded.com>
+
+description:
+  The Sony IMX728 is a 1/1.72-Inch CMOS Solid-state image sensor with a
+  color square pixel array and 8.39M active pixels. It is programmed
+  through an I2C interface.
+
+  The sensor can output up to 3840x2160 at a maximum of 45 frames/s over
+  a CSI-2 serial interface. It supports RAW24/20/16/12 and 10.
+
+properties:
+  compatible:
+    enum:
+      - sony,imx728
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    description: Clock frequency from 18 to 30MHz
+    maxItems: 1
+
+  clock-names:
+    const: inck
+
+  reset-gpios:
+    maxItems: 1
+    description:
+      Specifier for the GPIO connected to the XCLR (System Reset) pin.
+
+  error0-gpios:
+    maxItems: 1
+    description:
+      Specifier for the GPIO connected to the XWRN pin.
+
+  error1-gpios:
+    maxItems: 1
+    description:
+      Specifier for the GPIO connected to the XERR pin.
+
+  port:
+    $ref: /schemas/graph.yaml#/properties/port
+    additionalProperties: false
+
+    properties:
+      endpoint:
+        $ref: ../video-interfaces.yaml#
+        unevaluatedProperties: false
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - port
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/gpio/gpio.h>
+
+    i2c {
+        clock-frequency = <400000>;
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        camera@1a {
+            compatible = "sony,imx728";
+            reg = <0x1a>;
+
+            clocks = <&fixed_clock>;
+            clock-names = "inck";
+
+            reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
+            error0-gpios = <&sens_exp 1 GPIO_ACTIVE_HIGH>;
+            error1-gpios = <&sens_exp 2 GPIO_ACTIVE_HIGH>;
+
+            port {
+                camera1: endpoint {
+                    remote-endpoint = <&vin1a_ep>;
+                };
+            };
+        };
+    };
+
+...
diff --git a/MAINTAINERS b/MAINTAINERS
index 575f0e6f0532..50bff3558d7d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21885,6 +21885,12 @@ T:     git git://linuxtv.org/media.git
 F:     Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml
 F:     drivers/media/i2c/imx415.c

+SONY IMX728 SENSOR DRIVER
+M:     Stuart Burtner <sburtner@d3embedded.com>
+L:     linux-media@vger.kernel.org
+S:     Odd Fixes
+F:     Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml
+
 SONY MEMORYSTICK SUBSYSTEM
 M:     Maxim Levitsky <maximlevitsky@gmail.com>
 M:     Alex Dubov <oakad@yahoo.com>
--
2.34.1

Please be aware that this email includes email addresses outside of the organization.

Re: [PATCH 1/4] media: dt-bindings: Add Sony IMX728

[Krzysztof Kozlowski]

On 12/02/2025 20:56, Sebastian LaVine wrote:
> +
> +  reset-gpios:
> +    maxItems: 1
> +    description:
> +      Specifier for the GPIO connected to the XCLR (System Reset) pin.

s/Specifier for the GPIO connected to the//
But you could say that it is active low, for example.

> +
> +  error0-gpios:
> +    maxItems: 1
> +    description:
> +      Specifier for the GPIO connected to the XWRN pin.

The same.

> +
> +  error1-gpios:
> +    maxItems: 1
> +    description:
> +      Specifier for the GPIO connected to the XERR pin.
> +
> +  port:
> +    $ref: /schemas/graph.yaml#/properties/port
> +    additionalProperties: false
> +
> +    properties:
> +      endpoint:
> +        $ref: ../video-interfaces.yaml#
> +        unevaluatedProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - clock-names
> +  - port
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/gpio/gpio.h>
> +
> +    i2c {
> +        clock-frequency = <400000>;

Drop, not really relevant.

> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +
> +        camera@1a {
> +            compatible = "sony,imx728";
> +            reg = <0x1a>;
> +
> +            clocks = <&fixed_clock>;
> +            clock-names = "inck";
> +
> +            reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>;
> +            error0-gpios = <&sens_exp 1 GPIO_ACTIVE_HIGH>;
> +            error1-gpios = <&sens_exp 2 GPIO_ACTIVE_HIGH>;
> +
> +            port {
> +                camera1: endpoint {
> +                    remote-endpoint = <&vin1a_ep>;
> +                };
> +            };
> +        };
> +    };
> +
> +...
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 575f0e6f0532..50bff3558d7d 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -21885,6 +21885,12 @@ T:     git git://linuxtv.org/media.git
>  F:     Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml
>  F:     drivers/media/i2c/imx415.c
> 
> +SONY IMX728 SENSOR DRIVER
> +M:     Stuart Burtner <sburtner@d3embedded.com>
> +L:     linux-media@vger.kernel.org
> +S:     Odd Fixes


Hm, why only odd fixes? If you don't care about driver, we also kind of
might not care and remove it soon.


> +F:     Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml
> +
>  SONY MEMORYSTICK SUBSYSTEM
>  M:     Maxim Levitsky <maximlevitsky@gmail.com>
>  M:     Alex Dubov <oakad@yahoo.com>
> --
> 2.34.1
> 
> Please be aware that this email includes email addresses outside of the organization.


Obviously. Please drop it. You can use b4 relay if you need to escape
corporate junk.

Best regards,
Krzysztof

Re: [PATCH 1/4] media: dt-bindings: Add Sony IMX728

[Sebastian LaVine]

On Wed Feb 12, 2025 at 3:07 PM EST, Krzysztof Kozlowski wrote:
> On 12/02/2025 20:56, Sebastian LaVine wrote:
>> +
>> +  reset-gpios:
>> +    maxItems: 1
>> +    description:
>> +      Specifier for the GPIO connected to the XCLR (System Reset) pin.
>
> s/Specifier for the GPIO connected to the//
> But you could say that it is active low, for example.
>
>> +
>> +  error0-gpios:
>> +    maxItems: 1
>> +    description:
>> +      Specifier for the GPIO connected to the XWRN pin.
>
> The same.
>

Thanks, I'll make this change in v4.

>>
>> ...
>>
>> +
>> +examples:
>> +  - |
>> +    #include <dt-bindings/gpio/gpio.h>
>> +
>> +    i2c {
>> +        clock-frequency = <400000>;
>
> Drop, not really relevant.

Ack, I'll remove in v4.

>>
>> ...
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 575f0e6f0532..50bff3558d7d 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -21885,6 +21885,12 @@ T:     git git://linuxtv.org/media.git
>>  F:     Documentation/devicetree/bindings/media/i2c/sony,imx415.yaml
>>  F:     drivers/media/i2c/imx415.c
>>
>> +SONY IMX728 SENSOR DRIVER
>> +M:     Stuart Burtner <sburtner@d3embedded.com>
>> +L:     linux-media@vger.kernel.org
>> +S:     Odd Fixes
>
>
> Hm, why only odd fixes? If you don't care about driver, we also kind of
> might not care and remove it soon.
>

Understood -- we've discussed this and Stuart will be able to commit to
"Maintained" status going forward. I'll update this for v4.

>
> ...
>
> Obviously. Please drop it. You can use b4 relay if you need to escape
> corporate junk.
>

Sorry about that. I can look into using `b4 relay` going forward to
prevent that message from being added to patches. Unfortunately I'm not
sure of a way to remove it from my normal mail (like this message).

Thanks,

--
Sebastian

Please be aware that this email includes email addresses outside of the organization.

Re: [PATCH 1/4] media: dt-bindings: Add Sony IMX728

[Krzysztof Kozlowski]

On Wed, Feb 12, 2025 at 02:56:53PM -0500, Sebastian LaVine wrote:
> Adds bindings for the Sony IMX728.
> 
> Signed-off-by: Sebastian LaVine <slavine@d3embedded.com>
> Mentored-by: Stuart Burtner <sburtner@d3embedded.com>
> ---

Please run scripts/checkpatch.pl and fix reported warnings. After that,
run also 'scripts/checkpatch.pl --strict' and (probably) fix more
warnings. Some warnings can be ignored, especially from --strict run,
but the code here looks like it needs a fix. Feel free to get in touch
if the warning is not clear.

Best regards,
Krzysztof

Re: [PATCH 1/4] media: dt-bindings: Add Sony IMX728

[Sebastian LaVine]

Hello Krzysztof,

On Thu Feb 13, 2025 at 4:26 AM EST, Krzysztof Kozlowski wrote:
> On Wed, Feb 12, 2025 at 02:56:53PM -0500, Sebastian LaVine wrote:
>> Adds bindings for the Sony IMX728.
>>
>> Signed-off-by: Sebastian LaVine <slavine@d3embedded.com>
>> Mentored-by: Stuart Burtner <sburtner@d3embedded.com>
>> ---
>
> Please run scripts/checkpatch.pl and fix reported warnings. After that,
> run also 'scripts/checkpatch.pl --strict' and (probably) fix more
> warnings. Some warnings can be ignored, especially from --strict run,
> but the code here looks like it needs a fix. Feel free to get in touch
> if the warning is not clear.

The only output I get from scripts/checkpatch.pl for this patch is the
following:

> next$ scripts/checkpatch.pl --strict  patches/outgoing/0001-media-dt-bindings-Add-Sony-IMX728.patch
> WARNING: Non-standard signature: Mentored-by:
> #9:
> Mentored-by: Stuart Burtner <sburtner@d3embedded.com>
>
> total: 0 errors, 1 warnings, 0 checks, 108 lines checked
>
> ...

I can change this to a Signed-off-by from Stuart if you would like,
though I feel that Mentored-by is applicable to this case.

Thanks,

--
Sebastian

Please be aware that this email includes email addresses outside of the organization.

Re: [PATCH 1/4] media: dt-bindings: Add Sony IMX728

[Sebastian LaVine]

I'll put Stuart as Acked-By in future patches.

Thanks,

--
Sebastian
Please be aware that this email includes email addresses outside of the organization.

Re: [PATCH 1/4] media: dt-bindings: Add Sony IMX728

[Krzysztof Kozlowski]

On 26/02/2025 18:50, Sebastian LaVine wrote:
> Hello Krzysztof,
> 
> On Thu Feb 13, 2025 at 4:26 AM EST, Krzysztof Kozlowski wrote:
>> On Wed, Feb 12, 2025 at 02:56:53PM -0500, Sebastian LaVine wrote:
>>> Adds bindings for the Sony IMX728.
>>>
>>> Signed-off-by: Sebastian LaVine <slavine@d3embedded.com>
>>> Mentored-by: Stuart Burtner <sburtner@d3embedded.com>
>>> ---
>>
>> Please run scripts/checkpatch.pl and fix reported warnings. After that,
>> run also 'scripts/checkpatch.pl --strict' and (probably) fix more
>> warnings. Some warnings can be ignored, especially from --strict run,
>> but the code here looks like it needs a fix. Feel free to get in touch
>> if the warning is not clear.
> 
> The only output I get from scripts/checkpatch.pl for this patch is the
> following:
> 
>> next$ scripts/checkpatch.pl --strict  patches/outgoing/0001-media-dt-bindings-Add-Sony-IMX728.patch
>> WARNING: Non-standard signature: Mentored-by:
>> #9:
>> Mentored-by: Stuart Burtner <sburtner@d3embedded.com>
>>
>> total: 0 errors, 1 warnings, 0 checks, 108 lines checked
>>
>> ...
> 
> I can change this to a Signed-off-by from Stuart if you would like,
> though I feel that Mentored-by is applicable to this case.

It has been two weeks, so I don't remember what warning I saw (countless
of patches in between). It's possible I had in mind the "mentored-by",
because it's nowhere explained in Linux. Does it mean part of DCO chain?
Does it mean reviews or suggestions? This should be one of standard
tags, IMO, with all its effects (because tags have meaning, e.g. DCO or
reviewer's statement of oversight).


Best regards,
Krzysztof

[PATCH 2/4] media: i2c: Add driver for Sony IMX728

[Sebastian LaVine]

Adds a driver for the Sony IMX728 image sensor.

Signed-off-by: Sebastian LaVine <slavine@d3embedded.com>
Mentored-by: Stuart Burtner <sburtner@d3embedded.com>
---
 MAINTAINERS                  |    1 +
 arch/arm64/configs/defconfig |    1 +
 drivers/media/i2c/Kconfig    |   12 +
 drivers/media/i2c/Makefile   |    1 +
 drivers/media/i2c/imx728.c   | 9655 ++++++++++++++++++++++++++++++++++
 5 files changed, 9670 insertions(+)
 create mode 100644 drivers/media/i2c/imx728.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 50bff3558d7d..27fb3c1be732 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21890,6 +21890,7 @@ M:      Stuart Burtner <sburtner@d3embedded.com>
 L:     linux-media@vger.kernel.org
 S:     Odd Fixes
 F:     Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml
+F:     drivers/media/i2c/imx728.c

 SONY MEMORYSTICK SUBSYSTEM
 M:     Maxim Levitsky <maximlevitsky@gmail.com>
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c62831e61586..0ff578bb4645 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -852,6 +852,7 @@ CONFIG_VIDEO_TI_J721E_CSI2RX=m
 CONFIG_VIDEO_HANTRO=m
 CONFIG_VIDEO_IMX219=m
 CONFIG_VIDEO_IMX412=m
+CONFIG_VIDEO_IMX728=m
 CONFIG_VIDEO_OV5640=m
 CONFIG_VIDEO_OV5645=m
 CONFIG_DRM=m
diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig
index 8ba096b8ebca..79129f533eaa 100644
--- a/drivers/media/i2c/Kconfig
+++ b/drivers/media/i2c/Kconfig
@@ -264,6 +264,18 @@ config VIDEO_IMX415
          To compile this driver as a module, choose M here: the
          module will be called imx415.

+config VIDEO_IMX728
+       tristate "Sony IMX728 sensor support"
+       depends on I2C && VIDEO_DEV
+       select MEDIA_CONTROLLER
+       select VIDEO_V4L2_SUBDEV_API
+       help
+         This is a Video4Linux2 sensor driver for the Sony
+         IMX728 camera.
+
+         To compile this driver as a module, choose M here: the
+         module will be called imx728.
+
 config VIDEO_MAX9271_LIB
        tristate

diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile
index fbb988bd067a..d22df59f460d 100644
--- a/drivers/media/i2c/Makefile
+++ b/drivers/media/i2c/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_VIDEO_IMX335) += imx335.o
 obj-$(CONFIG_VIDEO_IMX355) += imx355.o
 obj-$(CONFIG_VIDEO_IMX412) += imx412.o
 obj-$(CONFIG_VIDEO_IMX415) += imx415.o
+obj-$(CONFIG_VIDEO_IMX728) += imx728.o
 obj-$(CONFIG_VIDEO_IR_I2C) += ir-kbd-i2c.o
 obj-$(CONFIG_VIDEO_ISL7998X) += isl7998x.o
 obj-$(CONFIG_VIDEO_KS0127) += ks0127.o
diff --git a/drivers/media/i2c/imx728.c b/drivers/media/i2c/imx728.c
new file mode 100644
index 000000000000..75120ca01ce6
--- /dev/null
+++ b/drivers/media/i2c/imx728.c
@@ -0,0 +1,9655 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Sony IMX728 CMOS Image Sensor Driver
+ *
+ * Copyright (c) 2024-2025 Define Design Deploy Corp
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/gpio/consumer.h>
+#include <linux/i2c.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pm_runtime.h>
+#include <linux/types.h>
+#include <linux/v4l2-mediabus.h>
+#include <linux/videodev2.h>
+#include <media/v4l2-cci.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-subdev.h>
+
+#define IMX728_FRAMERATE_MAX           30
+#define IMX728_FRAMERATE_DEFAULT       30
+#define IMX728_FRAMERATE_MIN           10
+
+#define IMX728_PIXEL_ARRAY_WIDTH       3857
+#define IMX728_PIXEL_ARRAY_HEIGHT      2177
+#define IMX728_PIXEL_ARRAY_MARGIN_TOP  1
+#define IMX728_PIXEL_ARRAY_MARGIN_LEFT 1
+#define IMX728_PIXEL_ARRAY_RECORDING_WIDTH     3856
+#define IMX728_PIXEL_ARRAY_RECORDING_HEIGHT    2176
+
+#define IMX728_PIXEL_RATE              248832000
+#define IMX728_LINK_FREQ               800000000
+
+#define IMX728_EXPOSURE_DEFAULT        1440
+#define IMX728_AGAIN_DEFAULT           240
+
+#define IMX728_PM_IDLE_TIMEOUT         1000
+
+#define IMX728_REG_STATE              CCI_REG8(0x2cac)
+#define IMX728_REG_EXPOSURE_SP1       CCI_REG32_LE(0x98dc)
+#define IMX728_REG_EXPOSURE_SP2       CCI_REG32_LE(0x98e4)
+#define IMX728_REG_EXPOSURE_SP1VS     CCI_REG32_LE(0x98ec)
+#define IMX728_REG_FME_ISP_GAIN_FID0  CCI_REG16_LE(0x9918)
+#define IMX728_REG_FLIP               CCI_REG8(0x9651)
+#define IMX728_REG_HFLIP              CCI_REG8(0xb67c)
+#define IMX728_REG_VFLIP              CCI_REG8(0xb67d)
+#define IMX728_REG_VMINOR             CCI_REG8(0x6000)
+#define IMX728_REG_VMAJOR             CCI_REG8(0x6002)
+#define IMX728_REG_RESET_0            CCI_REG8(0xb661)
+#define IMX728_REG_RESET_1            CCI_REG8(0x95c5)
+#define IMX728_REG_INCK_0             CCI_REG8(0x1b20)
+#define IMX728_REG_INCK_1             CCI_REG8(0x1b1c)
+#define IMX728_REG_SLEEP              CCI_REG8(0x1b05)
+#define IMX728_REG_REGMAP             CCI_REG8(0xffff)
+#define IMX728_REG_UNIT_00            CCI_REG8(0x98e0)
+#define IMX728_REG_UNIT_01            CCI_REG8(0x98e8)
+#define IMX728_REG_UNIT_02            CCI_REG8(0x98f0)
+#define IMX728_REG_OB_0               CCI_REG16_LE(0xec12)
+#define IMX728_REG_OB_1               CCI_REG8(0xec14)
+#define IMX728_REG_SKEW               CCI_REG8(0x1761)
+#define IMX728_REG_SUBP_0             CCI_REG8(0x9714)
+#define IMX728_REG_SUBP_1             CCI_REG8(0xb684)
+#define IMX728_REG_STREAM_02          CCI_REG8(0x1b04)
+
+enum imx728_sensor_state {
+       IMX728_SENSOR_STATE_SLEEP      = 0x02,
+       IMX728_SENSOR_STATE_STANDBY    = 0x04,
+       IMX728_SENSOR_STATE_STREAMING  = 0x10,
+       IMX728_SENSOR_STATE_SAFE       = 0x20,
+};
+
+enum imx728_remap_mode_id {
+       IMX728_REMAP_MODE_STANDBY                              = 0x00,
+       IMX728_REMAP_MODE_STANDBY_PIXEL_SHADING_COMPENSATION   = 0x01,
+       IMX728_REMAP_MODE_STANDBY_SPOT_PIXEL_COMPENSATION      = 0x02,
+       IMX728_REMAP_MODE_STREAMING                            = 0x04,
+       IMX728_REMAP_MODE_STREAMING_PIXEL_SHADING_COMPENSATION = 0x05,
+       IMX728_REMAP_MODE_STREAMING_SPOT_PIXEL_COMPENSATION    = 0x06,
+       IMX728_REMAP_MODE_SLEEP                                = 0x20,
+};
+
+enum imx728_drive_mode {
+       IMX728_MODE_3856x2176_45_4LANE_RAW10 = 0x01,
+       IMX728_MODE_3856x2176_45_4LANE_RAW12 = 0x02,
+       IMX728_MODE_3856x2176_45_4LANE_RAW16 = 0x03,
+       IMX728_MODE_3856x2176_45_4LANE_RAW20 = 0x04,
+       IMX728_MODE_3856x2176_45_4LANE_RAW12_HDR = 0x05,
+       IMX728_MODE_3856x2176_40_4LANE_RAW10 = 0x11,
+       IMX728_MODE_3856x2176_40_4LANE_RAW12 = 0x12,
+       IMX728_MODE_3856x2176_40_4LANE_RAW16 = 0x13,
+       IMX728_MODE_3856x2176_40_4LANE_RAW20 = 0x14,
+       IMX728_MODE_3856x2176_40_4LANE_RAW12_HDR = 0x16,
+};
+
+enum imx728_awbmode {
+       IMX728_AWBMODE_ATW = 0,
+       IMX728_AWBMODE_ALL_PULL_IN = 1,
+       IMX728_AWBMODE_USER_PRESET = 2,
+       IMX728_AWBMODE_FULL_MWB = 3,
+       IMX728_AWBMODE_HOLD = 4,
+};
+
+enum imx728_img_raw_mode {
+       IMX728_IMG_MODE_LINEAR = 0x0,
+       IMX728_IMG_MODE_LI = 0x1,
+       IMX728_IMG_MODE_HDR = 0x2,
+       IMX728_IMG_MODE_LI_HDR = 0x3,
+};
+
+enum imx728_aemode {
+       IMX728_AEMODE_AE_AUTO  = 0,
+       IMX728_AEMODE_AE_HOLD  = 1,
+       IMX728_AEMODE_SCALE_ME = 2,
+       IMX728_AEMODE_FULL_ME  = 3,
+};
+
+enum imx728_fme_shtval_unit {
+       IMX728_FME_SHTVAL_UNIT_LINES        = 1,
+       IMX728_FME_SHTVAL_UNIT_MICROSECONDS = 3,
+       IMX728_FME_SHTVAL_UNIT_FRAMES       = 4,
+};
+
+enum imx728_linear_raw_sel {
+       IMX728_RAW_SEL_SP1H = 0x0,
+       IMX728_RAW_SEL_SP1L = 0x1,
+       IMX728_RAW_SEL_SP1EC = 0x2,
+       IMX728_RAW_SEL_SP2 = 0x3,
+       IMX728_RAW_SEL_SP1VS = 0x4
+};
+
+struct imx728_ctrl {
+       struct v4l2_ctrl_handler handler;
+       struct v4l2_ctrl *exposure;
+       struct v4l2_ctrl *again;
+       struct v4l2_ctrl *h_flip;
+       struct v4l2_ctrl *v_flip;
+       struct v4l2_ctrl *pixel_rate;
+       struct v4l2_ctrl *link_freq;
+};
+
+/*
+ * struct imx728 - imx728 device structure
+ * @dev: Device handle
+ * @clk: Pointer to imx728 clock
+ * @client: Pointer to I2C client
+ * @regmap: Pointer to regmap structure
+ * @reset_gpio: Pointer to XCLR gpio
+ * @subdev: V4L2 subdevice structure
+ * @format: V4L2 media bus frame format structure
+ *              (width and height are in sync with the compose rect)
+ * @pad: Media pad structure
+ * @ctrl: imx728 control structure
+ * @clk_rate: Frequency of imx728 clock
+ * @fps: Current frame rate of the sensor.
+ * @lock: Mutex structure for V4L2 ctrl handler
+ * @streaming: Flag to store streaming on/off status
+ */
+struct imx728 {
+       struct device *dev;
+
+       struct clk *clk;
+       struct i2c_client *client;
+       struct regmap *regmap;
+       struct gpio_desc *reset_gpio;
+
+       struct v4l2_subdev subdev;
+       struct v4l2_mbus_framefmt format;
+       struct media_pad pad;
+
+       struct imx728_ctrl ctrl;
+
+       unsigned long clk_rate;
+       u32 fps;
+
+       struct mutex lock;
+       bool streaming;
+};
+
+static const struct v4l2_area imx728_framesizes[] = {
+       {
+               .width = 3856,
+               .height = 2176,
+       },
+};
+
+static const u32 imx728_mbus_formats[] = {
+       MEDIA_BUS_FMT_SRGGB12_1X12,
+};
+
+static const s64 imx728_link_freq_menu[] = {
+       IMX728_LINK_FREQ,
+};
+
+static const struct cci_reg_sequence imx728_wdr_12bit_3856x2176[] = {
+       {CCI_REG8(0xffff), 0x00},
+       {CCI_REG8(0x1749), 0x01},
+       {CCI_REG8(0x174b), 0x01},
+       {CCI_REG8(0x2dcc), 0x69},
+       {CCI_REG8(0x2dcd), 0x04},
+       {CCI_REG8(0x2dce), 0x68},
+       {CCI_REG8(0x2dcf), 0x04},
+       {CCI_REG8(0x2dd4), 0x00},
+       {CCI_REG8(0x2dd5), 0x00},
+       {CCI_REG8(0x2dd6), 0x00},
+       {CCI_REG8(0x2dd7), 0x00},
+       {CCI_REG8(0x2dd8), 0x00},
+       {CCI_REG8(0x2dd9), 0x00},
+       {CCI_REG8(0x2ddc), 0x00},
+       {CCI_REG8(0x2ddd), 0x00},
+       {CCI_REG8(0x2dde), 0x63},
+       {CCI_REG8(0x2ddf), 0x04},
+       {CCI_REG8(0x2de0), 0x62},
+       {CCI_REG8(0x2de1), 0x04},
+       {CCI_REG8(0x2de6), 0x00},
+       {CCI_REG8(0x2de7), 0x00},
+       {CCI_REG8(0x2de8), 0x00},
+       {CCI_REG8(0x2de9), 0x00},
+       {CCI_REG8(0x2dea), 0x00},
+       {CCI_REG8(0x2deb), 0x00},
+       {CCI_REG8(0x2dee), 0x00},
+       {CCI_REG8(0x2def), 0x00},
+       {CCI_REG8(0x2df8), 0x00},
+       {CCI_REG8(0x2df9), 0x00},
+       {CCI_REG8(0x2dfa), 0x00},
+       {CCI_REG8(0x2dfb), 0x00},
+       {CCI_REG8(0x2dfc), 0x00},
+       {CCI_REG8(0x2dfd), 0x00},
+       {CCI_REG8(0x2e00), 0x00},
+       {CCI_REG8(0x2e01), 0x00},
+       {CCI_REG8(0x2e02), 0x68},
+       {CCI_REG8(0x2e03), 0x04},
+       {CCI_REG8(0x2e04), 0x69},
+       {CCI_REG8(0x2e05), 0x04},
+       {CCI_REG8(0x2e06), 0x62},
+       {CCI_REG8(0x2e07), 0x04},
+       {CCI_REG8(0x2e08), 0x63},
+       {CCI_REG8(0x2e09), 0x04},
+       {CCI_REG8(0x2e0e), 0x6c},
+       {CCI_REG8(0x2e0f), 0x04},
+       {CCI_REG8(0x2e10), 0x66},
+       {CCI_REG8(0x2e11), 0x04},
+       {CCI_REG8(0x2e12), 0x67},
+       {CCI_REG8(0x2e13), 0x04},
+       {CCI_REG8(0x2e28), 0x78},
+       {CCI_REG8(0x2e29), 0x05},
+       {CCI_REG8(0x2e2a), 0x00},
+       {CCI_REG8(0x2e2c), 0x78},
+       {CCI_REG8(0x2e2d), 0x05},
+       {CCI_REG8(0x2e2e), 0x00},
+       {CCI_REG8(0x2e3a), 0x05},
+       {CCI_REG8(0x2e3b), 0x00},
+       {CCI_REG8(0x2e40), 0x5a},
+       {CCI_REG8(0x2e60), 0x7f},
+       {CCI_REG8(0x2e61), 0x00},
+       {CCI_REG8(0x2e64), 0x37},
+       {CCI_REG8(0x2e65), 0x00},
+       {CCI_REG8(0x2e66), 0x37},
+       {CCI_REG8(0x2e67), 0x00},
+       {CCI_REG8(0x2e68), 0xf7},
+       {CCI_REG8(0x2e69), 0x00},
+       {CCI_REG8(0x2e6a), 0x5f},
+       {CCI_REG8(0x2e6b), 0x00},
+       {CCI_REG8(0x2e6c), 0x3f},
+       {CCI_REG8(0x2e6d), 0x00},
+       {CCI_REG8(0x2e6e), 0x6f},
+       {CCI_REG8(0x2e6f), 0x00},
+       {CCI_REG8(0x2e70), 0x3f},
+       {CCI_REG8(0x2e71), 0x00},
+       {CCI_REG8(0x2e72), 0x2f},
+       {CCI_REG8(0x2e73), 0x00},
+       {CCI_REG8(0x2ea0), 0x64},
+       {CCI_REG8(0x2ea1), 0xca},
+       {CCI_REG8(0x2ea2), 0x19},
+       {CCI_REG8(0x2ea3), 0x2d},
+       {CCI_REG8(0x2edd), 0x01},
+       {CCI_REG8(0x2f26), 0x0b},
+       {CCI_REG8(0x2f27), 0x00},
+       {CCI_REG8(0x2f4a), 0x20},
+       {CCI_REG8(0x2f4b), 0x00},
+       {CCI_REG8(0x2f56), 0x00},
+       {CCI_REG8(0x2f57), 0x00},
+       {CCI_REG8(0x2f68), 0x78},
+       {CCI_REG8(0x2f69), 0x00},
+       {CCI_REG8(0x2f6a), 0x04},
+       {CCI_REG8(0x2f6b), 0x00},
+       {CCI_REG8(0x2f76), 0x16},
+       {CCI_REG8(0x2f77), 0x00},
+       {CCI_REG8(0x2f98), 0x8d},
+       {CCI_REG8(0x2f99), 0x00},
+       {CCI_REG8(0x2f9a), 0x0a},
+       {CCI_REG8(0x2f9b), 0x00},
+       {CCI_REG8(0x2fa6), 0x10},
+       {CCI_REG8(0x2fa7), 0x00},
+       {CCI_REG8(0x2fc2), 0x0b},
+       {CCI_REG8(0x2fc3), 0x00},
+       {CCI_REG8(0x2fe2), 0x0b},
+       {CCI_REG8(0x2fe3), 0x00},
+       {CCI_REG8(0x300c), 0x78},
+       {CCI_REG8(0x300d), 0x00},
+       {CCI_REG8(0x300e), 0x05},
+       {CCI_REG8(0x300f), 0x00},
+       {CCI_REG8(0x3018), 0x8d},
+       {CCI_REG8(0x3019), 0x00},
+       {CCI_REG8(0x301a), 0x0a},
+       {CCI_REG8(0x301b), 0x00},
+       {CCI_REG8(0x301c), 0x7d},
+       {CCI_REG8(0x301d), 0x00},
+       {CCI_REG8(0x301e), 0x04},
+       {CCI_REG8(0x301f), 0x00},
+       {CCI_REG8(0x306a), 0x00},
+       {CCI_REG8(0x306b), 0x00},
+       {CCI_REG8(0x306c), 0x00},
+       {CCI_REG8(0x306d), 0x00},
+       {CCI_REG8(0x306e), 0x01},
+       {CCI_REG8(0x306f), 0x00},
+       {CCI_REG8(0x3070), 0x06},
+       {CCI_REG8(0x3071), 0x00},
+       {CCI_REG8(0x3072), 0x07},
+       {CCI_REG8(0x3073), 0x00},
+       {CCI_REG8(0x3074), 0xc9},
+       {CCI_REG8(0x3075), 0x08},
+       {CCI_REG8(0x3082), 0xcc},
+       {CCI_REG8(0x3083), 0x08},
+       {CCI_REG8(0x3084), 0xcd},
+       {CCI_REG8(0x3085), 0x08},
+       {CCI_REG8(0x30ed), 0x11},
+       {CCI_REG8(0x30ee), 0x1f},
+       {CCI_REG8(0x30ef), 0x11},
+       {CCI_REG8(0x30f0), 0x0d},
+       {CCI_REG8(0x30f1), 0x1f},
+       {CCI_REG8(0x30f2), 0x1f},
+       {CCI_REG8(0x3142), 0x00},
+       {CCI_REG8(0x315e), 0xd4},
+       {CCI_REG8(0x315f), 0x01},
+       {CCI_REG8(0x3162), 0x47},
+       {CCI_REG8(0x3163), 0x02},
+       {CCI_REG8(0x3176), 0xe0},
+       {CCI_REG8(0x3177), 0x01},
+       {CCI_REG8(0x317a), 0x41},
+       {CCI_REG8(0x317b), 0x02},
+       {CCI_REG8(0x31c2), 0x88},
+       {CCI_REG8(0x31c3), 0x01},
+       {CCI_REG8(0x31d4), 0xd5},
+       {CCI_REG8(0x31d5), 0x01},
+       {CCI_REG8(0x31d8), 0x48},
+       {CCI_REG8(0x31d9), 0x02},
+       {CCI_REG8(0x31ec), 0xe1},
+       {CCI_REG8(0x31ed), 0x01},
+       {CCI_REG8(0x31f0), 0x42},
+       {CCI_REG8(0x31f1), 0x02},
+       {CCI_REG8(0x3238), 0x89},
+       {CCI_REG8(0x3239), 0x01},
+       {CCI_REG8(0x3256), 0xff},
+       {CCI_REG8(0x3257), 0x07},
+       {CCI_REG8(0x326e), 0x05},
+       {CCI_REG8(0x326f), 0x03},
+       {CCI_REG8(0x32ba), 0xff},
+       {CCI_REG8(0x32bb), 0x07},
+       {CCI_REG8(0x32d0), 0xff},
+       {CCI_REG8(0x32d1), 0x07},
+       {CCI_REG8(0x32d2), 0xff},
+       {CCI_REG8(0x32d3), 0x07},
+       {CCI_REG8(0x32e8), 0xff},
+       {CCI_REG8(0x32e9), 0x07},
+       {CCI_REG8(0x32ea), 0xff},
+       {CCI_REG8(0x32eb), 0x07},
+       {CCI_REG8(0x3334), 0xff},
+       {CCI_REG8(0x3335), 0x07},
+       {CCI_REG8(0x3336), 0xff},
+       {CCI_REG8(0x3337), 0x07},
+       {CCI_REG8(0x334c), 0xff},
+       {CCI_REG8(0x334d), 0x07},
+       {CCI_REG8(0x33b0), 0xff},
+       {CCI_REG8(0x33b1), 0x07},
+       {CCI_REG8(0x33c6), 0xff},
+       {CCI_REG8(0x33c7), 0x07},
+       {CCI_REG8(0x33d2), 0x00},
+       {CCI_REG8(0x33d3), 0x03},
+       {CCI_REG8(0x3412), 0xff},
+       {CCI_REG8(0x3413), 0x07},
+       {CCI_REG8(0x3420), 0xff},
+       {CCI_REG8(0x3421), 0x07},
+       {CCI_REG8(0x3422), 0xff},
+       {CCI_REG8(0x3423), 0x07},
+       {CCI_REG8(0x346c), 0x28},
+       {CCI_REG8(0x346d), 0x01},
+       {CCI_REG8(0x3470), 0xff},
+       {CCI_REG8(0x3471), 0x07},
+       {CCI_REG8(0x347c), 0x01},
+       {CCI_REG8(0x347d), 0x03},
+       {CCI_REG8(0x34bc), 0xff},
+       {CCI_REG8(0x34bd), 0x07},
+       {CCI_REG8(0x3556), 0x03},
+       {CCI_REG8(0x3557), 0x03},
+       {CCI_REG8(0x3562), 0xfb},
+       {CCI_REG8(0x3563), 0x02},
+       {CCI_REG8(0x3586), 0x44},
+       {CCI_REG8(0x3587), 0x02},
+       {CCI_REG8(0x35b8), 0x04},
+       {CCI_REG8(0x35b9), 0x03},
+       {CCI_REG8(0x35c4), 0xfc},
+       {CCI_REG8(0x35c5), 0x02},
+       {CCI_REG8(0x35e8), 0x45},
+       {CCI_REG8(0x35e9), 0x02},
+       {CCI_REG8(0x35f4), 0xd6},
+       {CCI_REG8(0x35f5), 0x01},
+       {CCI_REG8(0x3636), 0xd5},
+       {CCI_REG8(0x3637), 0x01},
+       {CCI_REG8(0x3750), 0xc1},
+       {CCI_REG8(0x3751), 0x00},
+       {CCI_REG8(0x3752), 0xff},
+       {CCI_REG8(0x3753), 0x07},
+       {CCI_REG8(0x3754), 0xff},
+       {CCI_REG8(0x3755), 0x07},
+       {CCI_REG8(0x3760), 0xff},
+       {CCI_REG8(0x3761), 0x07},
+       {CCI_REG8(0x37b0), 0xc1},
+       {CCI_REG8(0x37b1), 0x00},
+       {CCI_REG8(0x37b2), 0xdc},
+       {CCI_REG8(0x37b3), 0x01},
+       {CCI_REG8(0x37b4), 0x03},
+       {CCI_REG8(0x37b5), 0x02},
+       {CCI_REG8(0x37b6), 0x33},
+       {CCI_REG8(0x37b7), 0x02},
+       {CCI_REG8(0x37f0), 0xff},
+       {CCI_REG8(0x37f1), 0x07},
+       {CCI_REG8(0x37f2), 0xc0},
+       {CCI_REG8(0x37f3), 0x00},
+       {CCI_REG8(0x37f6), 0xff},
+       {CCI_REG8(0x37f7), 0x07},
+       {CCI_REG8(0x3800), 0xdd},
+       {CCI_REG8(0x3801), 0x01},
+       {CCI_REG8(0x3802), 0xc0},
+       {CCI_REG8(0x3803), 0x00},
+       {CCI_REG8(0x3804), 0x34},
+       {CCI_REG8(0x3805), 0x02},
+       {CCI_REG8(0x3806), 0x02},
+       {CCI_REG8(0x3807), 0x02},
+       {CCI_REG8(0x3b10), 0xff},
+       {CCI_REG8(0x3b11), 0x07},
+       {CCI_REG8(0x3b12), 0x00},
+       {CCI_REG8(0x3b13), 0x00},
+       {CCI_REG8(0x3b18), 0xff},
+       {CCI_REG8(0x3b19), 0x07},
+       {CCI_REG8(0x3b1a), 0x00},
+       {CCI_REG8(0x3b1b), 0x00},
+       {CCI_REG8(0x3b20), 0xff},
+       {CCI_REG8(0x3b21), 0x07},
+       {CCI_REG8(0x3b22), 0x00},
+       {CCI_REG8(0x3b23), 0x00},
+       {CCI_REG8(0x3b40), 0x00},
+       {CCI_REG8(0x3b41), 0x00},
+       {CCI_REG8(0x3b42), 0xff},
+       {CCI_REG8(0x3b43), 0x07},
+       {CCI_REG8(0x3b48), 0x00},
+       {CCI_REG8(0x3b49), 0x00},
+       {CCI_REG8(0x3b4a), 0xff},
+       {CCI_REG8(0x3b4b), 0x07},
+       {CCI_REG8(0x3b50), 0x00},
+       {CCI_REG8(0x3b51), 0x00},
+       {CCI_REG8(0x3b52), 0xff},
+       {CCI_REG8(0x3b53), 0x07},
+       {CCI_REG8(0x3b66), 0xd4},
+       {CCI_REG8(0x3b67), 0x01},
+       {CCI_REG8(0x3bf4), 0xd5},
+       {CCI_REG8(0x3bf5), 0x01},
+       {CCI_REG8(0x3d7c), 0xce},
+       {CCI_REG8(0x3d7d), 0x01},
+       {CCI_REG8(0x3dfc), 0x2c},
+       {CCI_REG8(0x3dfd), 0x01},
+       {CCI_REG8(0x3eba), 0xd7},
+       {CCI_REG8(0x3ebb), 0x00},
+       {CCI_REG8(0x3ebe), 0xff},
+       {CCI_REG8(0x3ebf), 0x07},
+       {CCI_REG8(0x3ec2), 0xff},
+       {CCI_REG8(0x3ec3), 0x07},
+       {CCI_REG8(0x3efa), 0xd7},
+       {CCI_REG8(0x3efb), 0x00},
+       {CCI_REG8(0x3efe), 0xff},
+       {CCI_REG8(0x3eff), 0x07},
+       {CCI_REG8(0x3f02), 0xff},
+       {CCI_REG8(0x3f03), 0x07},
+       {CCI_REG8(0x3f08), 0xd8},
+       {CCI_REG8(0x3f09), 0x00},
+       {CCI_REG8(0x3f0a), 0xdc},
+       {CCI_REG8(0x3f0b), 0x00},
+       {CCI_REG8(0x3f0c), 0xff},
+       {CCI_REG8(0x3f0d), 0x07},
+       {CCI_REG8(0x3f0e), 0xff},
+       {CCI_REG8(0x3f0f), 0x07},
+       {CCI_REG8(0x3f10), 0xff},
+       {CCI_REG8(0x3f11), 0x07},
+       {CCI_REG8(0x3f12), 0xff},
+       {CCI_REG8(0x3f13), 0x07},
+       {CCI_REG8(0x3f48), 0xd8},
+       {CCI_REG8(0x3f49), 0x00},
+       {CCI_REG8(0x3f4a), 0xdc},
+       {CCI_REG8(0x3f4b), 0x00},
+       {CCI_REG8(0x3f4c), 0xff},
+       {CCI_REG8(0x3f4d), 0x07},
+       {CCI_REG8(0x3f4e), 0xff},
+       {CCI_REG8(0x3f4f), 0x07},
+       {CCI_REG8(0x3f50), 0xff},
+       {CCI_REG8(0x3f51), 0x07},
+       {CCI_REG8(0x3f52), 0xff},
+       {CCI_REG8(0x3f53), 0x07},
+       {CCI_REG8(0x3f58), 0xdd},
+       {CCI_REG8(0x3f59), 0x00},
+       {CCI_REG8(0x3f5c), 0xff},
+       {CCI_REG8(0x3f5d), 0x07},
+       {CCI_REG8(0x3f60), 0xff},
+       {CCI_REG8(0x3f61), 0x07},
+       {CCI_REG8(0x3f98), 0xdd},
+       {CCI_REG8(0x3f99), 0x00},
+       {CCI_REG8(0x3f9c), 0xff},
+       {CCI_REG8(0x3f9d), 0x07},
+       {CCI_REG8(0x3fa0), 0xff},
+       {CCI_REG8(0x3fa1), 0x07},
+       {CCI_REG8(0x3faa), 0xc7},
+       {CCI_REG8(0x3fab), 0x00},
+       {CCI_REG8(0x3fac), 0xe0},
+       {CCI_REG8(0x3fad), 0x00},
+       {CCI_REG8(0x3fea), 0xc7},
+       {CCI_REG8(0x3feb), 0x00},
+       {CCI_REG8(0x3fec), 0xe0},
+       {CCI_REG8(0x3fed), 0x00},
+       {CCI_REG8(0x3ff8), 0xc8},
+       {CCI_REG8(0x3ff9), 0x00},
+       {CCI_REG8(0x3ffa), 0xcc},
+       {CCI_REG8(0x3ffb), 0x00},
+       {CCI_REG8(0x4038), 0xc8},
+       {CCI_REG8(0x4039), 0x00},
+       {CCI_REG8(0x403a), 0xcc},
+       {CCI_REG8(0x403b), 0x00},
+       {CCI_REG8(0x4048), 0xcd},
+       {CCI_REG8(0x4049), 0x00},
+       {CCI_REG8(0x404e), 0xdf},
+       {CCI_REG8(0x404f), 0x00},
+       {CCI_REG8(0x4088), 0xcd},
+       {CCI_REG8(0x4089), 0x00},
+       {CCI_REG8(0x408e), 0xdf},
+       {CCI_REG8(0x408f), 0x00},
+       {CCI_REG8(0x420c), 0xff},
+       {CCI_REG8(0x420d), 0x07},
+       {CCI_REG8(0x4210), 0xff},
+       {CCI_REG8(0x4211), 0x07},
+       {CCI_REG8(0x4286), 0xff},
+       {CCI_REG8(0x4287), 0x07},
+       {CCI_REG8(0x428a), 0xff},
+       {CCI_REG8(0x428b), 0x07},
+       {CCI_REG8(0x4408), 0xff},
+       {CCI_REG8(0x4409), 0x07},
+       {CCI_REG8(0x4410), 0xff},
+       {CCI_REG8(0x4411), 0x07},
+       {CCI_REG8(0x4418), 0xff},
+       {CCI_REG8(0x4419), 0x07},
+       {CCI_REG8(0x4420), 0xff},
+       {CCI_REG8(0x4421), 0x07},
+       {CCI_REG8(0x4428), 0xff},
+       {CCI_REG8(0x4429), 0x07},
+       {CCI_REG8(0x4430), 0xff},
+       {CCI_REG8(0x4431), 0x07},
+       {CCI_REG8(0x4436), 0xff},
+       {CCI_REG8(0x4437), 0x07},
+       {CCI_REG8(0x443c), 0xff},
+       {CCI_REG8(0x443d), 0x07},
+       {CCI_REG8(0x4444), 0xff},
+       {CCI_REG8(0x4445), 0x07},
+       {CCI_REG8(0x4464), 0xff},
+       {CCI_REG8(0x4465), 0x07},
+       {CCI_REG8(0x446c), 0xff},
+       {CCI_REG8(0x446d), 0x07},
+       {CCI_REG8(0x4474), 0xff},
+       {CCI_REG8(0x4475), 0x07},
+       {CCI_REG8(0x4485), 0x28},
+       {CCI_REG8(0x44a7), 0x2e},
+       {CCI_REG8(0x44a8), 0x2c},
+       {CCI_REG8(0x4594), 0x1b},
+       {CCI_REG8(0x4596), 0x1f},
+       {CCI_REG8(0x459b), 0x1b},
+       {CCI_REG8(0x459d), 0x1f},
+       {CCI_REG8(0x45a1), 0x14},
+       {CCI_REG8(0x45a4), 0x16},
+       {CCI_REG8(0x45a6), 0x14},
+       {CCI_REG8(0x45ab), 0x16},
+       {CCI_REG8(0x45ac), 0x11},
+       {CCI_REG8(0x45ad), 0x11},
+       {CCI_REG8(0x45ae), 0x0b},
+       {CCI_REG8(0x45af), 0x0b},
+       {CCI_REG8(0x45b0), 0x0b},
+       {CCI_REG8(0x45b1), 0x0b},
+       {CCI_REG8(0x45b2), 0x1f},
+       {CCI_REG8(0x45b3), 0x0b},
+       {CCI_REG8(0x45b4), 0x0b},
+       {CCI_REG8(0x45b5), 0x1f},
+       {CCI_REG8(0x45b6), 0x1f},
+       {CCI_REG8(0x45b7), 0x1f},
+       {CCI_REG8(0x45b8), 0x1f},
+       {CCI_REG8(0x45b9), 0x1f},
+       {CCI_REG8(0x45ba), 0x1f},
+       {CCI_REG8(0x45bb), 0x1f},
+       {CCI_REG8(0x45bc), 0x1f},
+       {CCI_REG8(0x45bd), 0x1f},
+       {CCI_REG8(0x45be), 0x0d},
+       {CCI_REG8(0x45bf), 0x0d},
+       {CCI_REG8(0x45c0), 0x0b},
+       {CCI_REG8(0x45c1), 0x0b},
+       {CCI_REG8(0x45c2), 0x0b},
+       {CCI_REG8(0x45c3), 0x0b},
+       {CCI_REG8(0x45c4), 0x1f},
+       {CCI_REG8(0x45c5), 0x0b},
+       {CCI_REG8(0x45c6), 0x0b},
+       {CCI_REG8(0x460b), 0x01},
+       {CCI_REG8(0x462e), 0x1c},
+       {CCI_REG8(0x4631), 0x01},
+       {CCI_REG8(0x465a), 0x08},
+       {CCI_REG8(0x465b), 0x00},
+       {CCI_REG8(0x465c), 0x00},
+       {CCI_REG8(0x465d), 0x00},
+       {CCI_REG8(0x465e), 0x06},
+       {CCI_REG8(0x4660), 0x00},
+       {CCI_REG8(0x4661), 0x00},
+       {CCI_REG8(0x4662), 0x00},
+       {CCI_REG8(0x4663), 0x00},
+       {CCI_REG8(0x4664), 0x00},
+       {CCI_REG8(0x4665), 0x00},
+       {CCI_REG8(0x4666), 0x00},
+       {CCI_REG8(0x4667), 0x00},
+       {CCI_REG8(0x4668), 0x00},
+       {CCI_REG8(0x4669), 0x00},
+       {CCI_REG8(0x466a), 0x04},
+       {CCI_REG8(0x466c), 0x00},
+       {CCI_REG8(0x466d), 0x00},
+       {CCI_REG8(0x466e), 0x06},
+       {CCI_REG8(0x4670), 0x00},
+       {CCI_REG8(0x4671), 0x00},
+       {CCI_REG8(0x4672), 0x00},
+       {CCI_REG8(0x4673), 0x00},
+       {CCI_REG8(0x4674), 0x00},
+       {CCI_REG8(0x4675), 0x00},
+       {CCI_REG8(0x4676), 0x00},
+       {CCI_REG8(0x4677), 0x00},
+       {CCI_REG8(0x4678), 0x00},
+       {CCI_REG8(0x4679), 0x00},
+       {CCI_REG8(0x46ae), 0xca},
+       {CCI_REG8(0x46af), 0x00},
+       {CCI_REG8(0x46b0), 0xb8},
+       {CCI_REG8(0x46b1), 0x01},
+       {CCI_REG8(0x46b6), 0x34},
+       {CCI_REG8(0x46b7), 0x02},
+       {CCI_REG8(0x46b8), 0x87},
+       {CCI_REG8(0x46b9), 0x02},
+       {CCI_REG8(0x46ba), 0x94},
+       {CCI_REG8(0x46bb), 0x06},
+       {CCI_REG8(0x46d2), 0xa0},
+       {CCI_REG8(0x46d3), 0x04},
+       {CCI_REG8(0x4778), 0x02},
+       {CCI_REG8(0x4779), 0x02},
+       {CCI_REG8(0x477a), 0x02},
+       {CCI_REG8(0x477b), 0x02},
+       {CCI_REG8(0x477c), 0x02},
+       {CCI_REG8(0x477d), 0x02},
+       {CCI_REG8(0x477e), 0x02},
+       {CCI_REG8(0x477f), 0x02},
+       {CCI_REG8(0x4782), 0x03},
+       {CCI_REG8(0x4786), 0x03},
+       {CCI_REG8(0x4788), 0x03},
+       {CCI_REG8(0x4789), 0x03},
+       {CCI_REG8(0x478a), 0x03},
+       {CCI_REG8(0x478c), 0x03},
+       {CCI_REG8(0x478d), 0x03},
+       {CCI_REG8(0x478e), 0x03},
+       {CCI_REG8(0x4792), 0x03},
+       {CCI_REG8(0x4796), 0x03},
+       {CCI_REG8(0x4798), 0x01},
+       {CCI_REG8(0x4799), 0x02},
+       {CCI_REG8(0x479a), 0x03},
+       {CCI_REG8(0x479c), 0x03},
+       {CCI_REG8(0x479d), 0x03},
+       {CCI_REG8(0x479e), 0x03},
+       {CCI_REG8(0x47a3), 0x01},
+       {CCI_REG8(0x47ab), 0x00},
+       {CCI_REG8(0x47ad), 0x00},
+       {CCI_REG8(0x47b0), 0x03},
+       {CCI_REG8(0x47b1), 0x03},
+       {CCI_REG8(0x47b2), 0x03},
+       {CCI_REG8(0x47b3), 0x03},
+       {CCI_REG8(0x47b4), 0x03},
+       {CCI_REG8(0x47b5), 0x03},
+       {CCI_REG8(0x47b6), 0x03},
+       {CCI_REG8(0x47b7), 0x03},
+       {CCI_REG8(0x47f4), 0x12},
+       {CCI_REG8(0x47f6), 0x0c},
+       {CCI_REG8(0x47fa), 0x09},
+       {CCI_REG8(0x47fb), 0x0b},
+       {CCI_REG8(0x47fc), 0x0a},
+       {CCI_REG8(0x4801), 0x05},
+       {CCI_REG8(0x4802), 0x04},
+       {CCI_REG8(0x4803), 0x06},
+       {CCI_REG8(0x4804), 0x05},
+       {CCI_REG8(0x4805), 0x04},
+       {CCI_REG8(0x480a), 0x0d},
+       {CCI_REG8(0x480b), 0x14},
+       {CCI_REG8(0x480c), 0x10},
+       {CCI_REG8(0x480d), 0x12},
+       {CCI_REG8(0x480e), 0x16},
+       {CCI_REG8(0x4815), 0x09},
+       {CCI_REG8(0x4816), 0x05},
+       {CCI_REG8(0x4817), 0x08},
+       {CCI_REG8(0x481e), 0x09},
+       {CCI_REG8(0x481f), 0x09},
+       {CCI_REG8(0x4820), 0x0d},
+       {CCI_REG8(0x4827), 0x09},
+       {CCI_REG8(0x4828), 0x07},
+       {CCI_REG8(0x4829), 0x0b},
+       {CCI_REG8(0x482e), 0x0f},
+       {CCI_REG8(0x482f), 0x0f},
+       {CCI_REG8(0x4830), 0x0a},
+       {CCI_REG8(0x4831), 0x0a},
+       {CCI_REG8(0x48f2), 0x04},
+       {CCI_REG8(0x48f6), 0xe2},
+       {CCI_REG8(0x48f7), 0x00},
+       {CCI_REG8(0x48f8), 0x84},
+       {CCI_REG8(0x48f9), 0x00},
+       {CCI_REG8(0x48fa), 0x80},
+       {CCI_REG8(0x48fb), 0x00},
+       {CCI_REG8(0x48fc), 0x45},
+       {CCI_REG8(0x48fd), 0x00},
+       {CCI_REG8(0x48fe), 0x70},
+       {CCI_REG8(0x48ff), 0x00},
+       {CCI_REG8(0x48f6), 0xe2},
+       {CCI_REG8(0x48f7), 0x00},
+       {CCI_REG8(0x48f8), 0x84},
+       {CCI_REG8(0x48f9), 0x00},
+       {CCI_REG8(0x48fa), 0x80},
+       {CCI_REG8(0x48fb), 0x00},
+       {CCI_REG8(0x48fc), 0x45},
+       {CCI_REG8(0x48fd), 0x00},
+       {CCI_REG8(0x48fe), 0x70},
+       {CCI_REG8(0x48ff), 0x00},
+       {CCI_REG8(0x4902), 0xb9},
+       {CCI_REG8(0x4903), 0x00},
+       {CCI_REG8(0x4904), 0x45},
+       {CCI_REG8(0x4905), 0x00},
+       {CCI_REG8(0x4906), 0x1f},
+       {CCI_REG8(0x4907), 0x1f},
+       {CCI_REG8(0x4908), 0x18},
+       {CCI_REG8(0x4909), 0x1f},
+       {CCI_REG8(0x490a), 0x1e},
+       {CCI_REG8(0x490c), 0x0a},
+       {CCI_REG8(0x490d), 0x1f},
+       {CCI_REG8(0x490e), 0x00},
+       {CCI_REG8(0x490f), 0x00},
+       {CCI_REG8(0x4910), 0x06},
+       {CCI_REG8(0x4911), 0x00},
+       {CCI_REG8(0x4912), 0x00},
+       {CCI_REG8(0x4915), 0x00},
+       {CCI_REG8(0x491c), 0x78},
+       {CCI_REG8(0x491d), 0x78},
+       {CCI_REG8(0x491e), 0x78},
+       {CCI_REG8(0x491f), 0x78},
+       {CCI_REG8(0x4924), 0x61},
+       {CCI_REG8(0x4925), 0x61},
+       {CCI_REG8(0x4926), 0x61},
+       {CCI_REG8(0x4927), 0x61},
+       {CCI_REG8(0x4928), 0x5f},
+       {CCI_REG8(0x4929), 0x5f},
+       {CCI_REG8(0x492a), 0x5f},
+       {CCI_REG8(0x492b), 0x5f},
+       {CCI_REG8(0x492c), 0x78},
+       {CCI_REG8(0x492d), 0x78},
+       {CCI_REG8(0x492e), 0x78},
+       {CCI_REG8(0x492f), 0x78},
+       {CCI_REG8(0x4930), 0x78},
+       {CCI_REG8(0x4931), 0x78},
+       {CCI_REG8(0x4932), 0x78},
+       {CCI_REG8(0x4933), 0x78},
+       {CCI_REG8(0x4934), 0x78},
+       {CCI_REG8(0x4935), 0x78},
+       {CCI_REG8(0x4936), 0x78},
+       {CCI_REG8(0x4937), 0x78},
+       {CCI_REG8(0x4938), 0x5f},
+       {CCI_REG8(0x4939), 0x5f},
+       {CCI_REG8(0x493a), 0x5f},
+       {CCI_REG8(0x493b), 0x5f},
+       {CCI_REG8(0x4942), 0x0a},
+       {CCI_REG8(0x4943), 0x0a},
+       {CCI_REG8(0x4944), 0x0a},
+       {CCI_REG8(0x4945), 0x0a},
+       {CCI_REG8(0x4947), 0x1f},
+       {CCI_REG8(0x4948), 0x1f},
+       {CCI_REG8(0x4949), 0x1f},
+       {CCI_REG8(0x494a), 0x0c},
+       {CCI_REG8(0x494b), 0x0c},
+       {CCI_REG8(0x494c), 0x0c},
+       {CCI_REG8(0x494d), 0x0c},
+       {CCI_REG8(0x494e), 0x0e},
+       {CCI_REG8(0x494f), 0x0e},
+       {CCI_REG8(0x4950), 0x0e},
+       {CCI_REG8(0x4951), 0x0e},
+       {CCI_REG8(0x4952), 0x11},
+       {CCI_REG8(0x4953), 0x11},
+       {CCI_REG8(0x4954), 0x11},
+       {CCI_REG8(0x4955), 0x11},
+       {CCI_REG8(0x4956), 0x0e},
+       {CCI_REG8(0x4957), 0x0e},
+       {CCI_REG8(0x4958), 0x0e},
+       {CCI_REG8(0x4959), 0x0e},
+       {CCI_REG8(0x495a), 0x10},
+       {CCI_REG8(0x495b), 0x10},
+       {CCI_REG8(0x495c), 0x10},
+       {CCI_REG8(0x495d), 0x10},
+       {CCI_REG8(0x495e), 0x0e},
+       {CCI_REG8(0x495f), 0x0e},
+       {CCI_REG8(0x4960), 0x0e},
+       {CCI_REG8(0x4961), 0x0e},
+       {CCI_REG8(0x4970), 0x00},
+       {CCI_REG8(0x4971), 0x00},
+       {CCI_REG8(0x4972), 0x00},
+       {CCI_REG8(0x4973), 0x00},
+       {CCI_REG8(0x4974), 0x00},
+       {CCI_REG8(0x4975), 0x00},
+       {CCI_REG8(0x4976), 0x00},
+       {CCI_REG8(0x4977), 0x00},
+       {CCI_REG8(0x4978), 0x04},
+       {CCI_REG8(0x4979), 0x04},
+       {CCI_REG8(0x497a), 0x04},
+       {CCI_REG8(0x497b), 0x04},
+       {CCI_REG8(0x497c), 0x03},
+       {CCI_REG8(0x497d), 0x03},
+       {CCI_REG8(0x497e), 0x03},
+       {CCI_REG8(0x497f), 0x03},
+       {CCI_REG8(0x4980), 0x05},
+       {CCI_REG8(0x4981), 0x05},
+       {CCI_REG8(0x4982), 0x05},
+       {CCI_REG8(0x4983), 0x05},
+       {CCI_REG8(0x4984), 0x00},
+       {CCI_REG8(0x4985), 0x00},
+       {CCI_REG8(0x4986), 0x00},
+       {CCI_REG8(0x4987), 0x00},
+       {CCI_REG8(0x49e0), 0xc3},
+       {CCI_REG8(0x49e1), 0x00},
+       {CCI_REG8(0x49e2), 0xea},
+       {CCI_REG8(0x49e3), 0x01},
+       {CCI_REG8(0x49e4), 0xd7},
+       {CCI_REG8(0x49e5), 0x02},
+       {CCI_REG8(0x49e8), 0xc3},
+       {CCI_REG8(0x49e9), 0x00},
+       {CCI_REG8(0x49ea), 0xd6},
+       {CCI_REG8(0x49eb), 0x01},
+       {CCI_REG8(0x4a68), 0x72},
+       {CCI_REG8(0x4a69), 0x00},
+       {CCI_REG8(0x4a6a), 0x6e},
+       {CCI_REG8(0x4a6b), 0x00},
+       {CCI_REG8(0x4a9c), 0x6e},
+       {CCI_REG8(0x4a9d), 0x00},
+       {CCI_REG8(0x4bb8), 0x00},
+       {CCI_REG8(0x4bb9), 0x00},
+       {CCI_REG8(0x4bba), 0xff},
+       {CCI_REG8(0x4bbb), 0x03},
+       {CCI_REG8(0x4bc0), 0x00},
+       {CCI_REG8(0x4bc1), 0x00},
+       {CCI_REG8(0x4bc2), 0xff},
+       {CCI_REG8(0x4bc3), 0x03},
+       {CCI_REG8(0x4c46), 0x6e},
+       {CCI_REG8(0x4c47), 0x00},
+       {CCI_REG8(0x4cda), 0x28},
+       {CCI_REG8(0x4cdb), 0x00},
+       {CCI_REG8(0x4cde), 0x7b},
+       {CCI_REG8(0x4cdf), 0x00},
+       {CCI_REG8(0x4ce2), 0x28},
+       {CCI_REG8(0x4ce3), 0x00},
+       {CCI_REG8(0x4eea), 0x70},
+       {CCI_REG8(0x4eeb), 0x00},
+       {CCI_REG8(0x4f00), 0x6c},
+       {CCI_REG8(0x4f01), 0x00},
+       {CCI_REG8(0x5072), 0x6c},
+       {CCI_REG8(0x5073), 0x00},
+       {CCI_REG8(0x5086), 0x6c},
+       {CCI_REG8(0x5087), 0x00},
+       {CCI_REG8(0x55a0), 0x3a},
+       {CCI_REG8(0x55a1), 0x00},
+       {CCI_REG8(0x55a6), 0x7a},
+       {CCI_REG8(0x55a7), 0x01},
+       {CCI_REG8(0x55a8), 0x3a},
+       {CCI_REG8(0x55a9), 0x00},
+       {CCI_REG8(0x55ae), 0xbb},
+       {CCI_REG8(0x55af), 0x00},
+       {CCI_REG8(0x55b2), 0x60},
+       {CCI_REG8(0x55b3), 0x00},
+       {CCI_REG8(0x55b4), 0x86},
+       {CCI_REG8(0x55b5), 0x00},
+       {CCI_REG8(0x55b6), 0xb7},
+       {CCI_REG8(0x55b7), 0x00},
+       {CCI_REG8(0x55b8), 0x17},
+       {CCI_REG8(0x55b9), 0x00},
+       {CCI_REG8(0x55ba), 0x5f},
+       {CCI_REG8(0x55bb), 0x00},
+       {CCI_REG8(0x55bc), 0x8d},
+       {CCI_REG8(0x55bd), 0x00},
+       {CCI_REG8(0x55be), 0xbb},
+       {CCI_REG8(0x55bf), 0x00},
+       {CCI_REG8(0x594c), 0xff},
+       {CCI_REG8(0x594d), 0x03},
+       {CCI_REG8(0x594e), 0xff},
+       {CCI_REG8(0x594f), 0x03},
+       {CCI_REG8(0x5950), 0xff},
+       {CCI_REG8(0x5951), 0x03},
+       {CCI_REG8(0x5952), 0xff},
+       {CCI_REG8(0x5953), 0x03},
+       {CCI_REG8(0x5b24), 0x20},
+       {CCI_REG8(0x5b25), 0x0d},
+       {CCI_REG8(0x5b28), 0x88},
+       {CCI_REG8(0x5b29), 0x04},
+       {CCI_REG8(0x961c), 0x00},
+       {CCI_REG8(0x961d), 0x03},
+       {CCI_REG8(0x9722), 0x09},
+       {CCI_REG8(0x9788), 0x01},
+       {CCI_REG8(0x9796), 0xd0},
+       {CCI_REG8(0x9797), 0x0a},
+       {CCI_REG8(0x9798), 0xf0},
+       {CCI_REG8(0x9799), 0x00},
+       {CCI_REG8(0x979c), 0xd0},
+       {CCI_REG8(0x979d), 0x0a},
+       {CCI_REG8(0x979e), 0xf0},
+       {CCI_REG8(0x979f), 0x00},
+       {CCI_REG8(0x97a0), 0xc0},
+       {CCI_REG8(0x97a1), 0xdf},
+       {CCI_REG8(0x97a4), 0x80},
+       {CCI_REG8(0x97a5), 0x7a},
+       {CCI_REG8(0x97a8), 0x00},
+       {CCI_REG8(0x97a9), 0x50},
+       {CCI_REG8(0x97aa), 0xc0},
+       {CCI_REG8(0x97ab), 0x35},
+       {CCI_REG8(0x97c4), 0xc5},
+       {CCI_REG8(0x97c5), 0x02},
+       {CCI_REG8(0xb51d), 0x01},
+       {CCI_REG8(0xb526), 0x00},
+       {CCI_REG8(0xcf61), 0x00},
+       {CCI_REG8(0xcfaf), 0x00},
+       {CCI_REG8(0xcffd), 0x00},
+       {CCI_REG8(0xd04b), 0x00},
+       {CCI_REG8(0xd099), 0x00},
+       {CCI_REG8(0xd0e7), 0x00},
+       {CCI_REG8(0xb527), 0x05},
+       {CCI_REG8(0xcf62), 0x05},
+       {CCI_REG8(0xcfb0), 0x05},
+       {CCI_REG8(0xcffe), 0x05},
+       {CCI_REG8(0xd04c), 0x05},
+       {CCI_REG8(0xd09a), 0x05},
+       {CCI_REG8(0xd0e8), 0x05},
+       {CCI_REG8(0xb52a), 0xc0},
+       {CCI_REG8(0xcf65), 0xc0},
+       {CCI_REG8(0xcfb3), 0xc0},
+       {CCI_REG8(0xd001), 0xc0},
+       {CCI_REG8(0xd04f), 0xc0},
+       {CCI_REG8(0xd09d), 0xc0},
+       {CCI_REG8(0xd0eb), 0xc0},
+       {CCI_REG8(0xb52b), 0x03},
+       {CCI_REG8(0xcf66), 0x03},
+       {CCI_REG8(0xcfb4), 0x03},
+       {CCI_REG8(0xd002), 0x03},
+       {CCI_REG8(0xd050), 0x03},
+       {CCI_REG8(0xd09e), 0x03},
+       {CCI_REG8(0xd0ec), 0x03},
+       {CCI_REG8(0xb530), 0x00},
+       {CCI_REG8(0xcf6a), 0x00},
+       {CCI_REG8(0xcfb8), 0x00},
+       {CCI_REG8(0xd006), 0x00},
+       {CCI_REG8(0xd054), 0x00},
+       {CCI_REG8(0xd0a2), 0x00},
+       {CCI_REG8(0xd0f0), 0x00},
+       {CCI_REG8(0xb531), 0x05},
+       {CCI_REG8(0xcf6b), 0x05},
+       {CCI_REG8(0xcfb9), 0x05},
+       {CCI_REG8(0xd007), 0x05},
+       {CCI_REG8(0xd055), 0x05},
+       {CCI_REG8(0xd0a3), 0x05},
+       {CCI_REG8(0xd0f1), 0x05},
+       {CCI_REG8(0xb534), 0xc0},
+       {CCI_REG8(0xcf6e), 0xc0},
+       {CCI_REG8(0xcfbc), 0xc0},
+       {CCI_REG8(0xd00a), 0xc0},
+       {CCI_REG8(0xd058), 0xc0},
+       {CCI_REG8(0xd0a6), 0xc0},
+       {CCI_REG8(0xd0f4), 0xc0},
+       {CCI_REG8(0xb535), 0x03},
+       {CCI_REG8(0xcf6f), 0x03},
+       {CCI_REG8(0xcfbd), 0x03},
+       {CCI_REG8(0xd00b), 0x03},
+       {CCI_REG8(0xd059), 0x03},
+       {CCI_REG8(0xd0a7), 0x03},
+       {CCI_REG8(0xd0f5), 0x03},
+       {CCI_REG8(0xb644), 0x70},
+       {CCI_REG8(0xb645), 0x03},
+       {CCI_REG8(0xb646), 0x00},
+       {CCI_REG8(0xb647), 0x00},
+       {CCI_REG8(0xb68a), 0x00},
+       {CCI_REG8(0xb68b), 0x03},
+       {CCI_REG8(0xb6bc), 0x00},
+       {CCI_REG8(0xcf84), 0x00},
+       {CCI_REG8(0xcfd2), 0x00},
+       {CCI_REG8(0xd020), 0x00},
+       {CCI_REG8(0xd06e), 0x00},
+       {CCI_REG8(0xd0bc), 0x00},
+       {CCI_REG8(0xd10a), 0x00},
+       {CCI_REG8(0xb6bd), 0x05},
+       {CCI_REG8(0xcf85), 0x05},
+       {CCI_REG8(0xcfd3), 0x05},
+       {CCI_REG8(0xd021), 0x05},
+       {CCI_REG8(0xd06f), 0x05},
+       {CCI_REG8(0xd0bd), 0x05},
+       {CCI_REG8(0xd10b), 0x05},
+       {CCI_REG8(0xb6c0), 0xc0},
+       {CCI_REG8(0xcf88), 0xc0},
+       {CCI_REG8(0xcfd6), 0xc0},
+       {CCI_REG8(0xd024), 0xc0},
+       {CCI_REG8(0xd072), 0xc0},
+       {CCI_REG8(0xd0c0), 0xc0},
+       {CCI_REG8(0xd10e), 0xc0},
+       {CCI_REG8(0xb6c1), 0x03},
+       {CCI_REG8(0xcf89), 0x03},
+       {CCI_REG8(0xcfd7), 0x03},
+       {CCI_REG8(0xd025), 0x03},
+       {CCI_REG8(0xd073), 0x03},
+       {CCI_REG8(0xd0c1), 0x03},
+       {CCI_REG8(0xd10f), 0x03},
+       {CCI_REG8(0xb6cc), 0x00},
+       {CCI_REG8(0xcf8d), 0x00},
+       {CCI_REG8(0xcfdb), 0x00},
+       {CCI_REG8(0xd029), 0x00},
+       {CCI_REG8(0xd077), 0x00},
+       {CCI_REG8(0xd0c5), 0x00},
+       {CCI_REG8(0xd113), 0x00},
+       {CCI_REG8(0xb6cd), 0x05},
+       {CCI_REG8(0xcf8e), 0x05},
+       {CCI_REG8(0xcfdc), 0x05},
+       {CCI_REG8(0xd02a), 0x05},
+       {CCI_REG8(0xd078), 0x05},
+       {CCI_REG8(0xd0c6), 0x05},
+       {CCI_REG8(0xd114), 0x05},
+       {CCI_REG8(0xb6d0), 0xc0},
+       {CCI_REG8(0xcf91), 0xc0},
+       {CCI_REG8(0xcfdf), 0xc0},
+       {CCI_REG8(0xd02d), 0xc0},
+       {CCI_REG8(0xd07b), 0xc0},
+       {CCI_REG8(0xd0c9), 0xc0},
+       {CCI_REG8(0xd117), 0xc0},
+       {CCI_REG8(0xb6d1), 0x03},
+       {CCI_REG8(0xcf92), 0x03},
+       {CCI_REG8(0xcfe0), 0x03},
+       {CCI_REG8(0xd02e), 0x03},
+       {CCI_REG8(0xd07c), 0x03},
+       {CCI_REG8(0xd0ca), 0x03},
+       {CCI_REG8(0xd118), 0x03},
+       {CCI_REG8(0xb6e8), 0x51},
+       {CCI_REG8(0xb6e9), 0x05},
+       {CCI_REG8(0xb6ea), 0x55},
+       {CCI_REG8(0xb6ec), 0x40},
+       {CCI_REG8(0xb6ed), 0x05},
+       {CCI_REG8(0xb6ee), 0x55},
+       {CCI_REG8(0xb6ef), 0x55},
+       {CCI_REG8(0xb6f0), 0x55},
+       {CCI_REG8(0xb6f1), 0x55},
+       {CCI_REG8(0xb6f2), 0x55},
+       {CCI_REG8(0xb6f3), 0x01},
+       {CCI_REG8(0xec40), 0x70},
+       {CCI_REG8(0xec41), 0x03},
+       {CCI_REG8(0xec42), 0x00},
+       {CCI_REG8(0xec43), 0x00},
+       {CCI_REG8(0xec68), 0x88},
+       {CCI_REG8(0xec69), 0x07},
+       {CCI_REG8(0xec6a), 0x40},
+       {CCI_REG8(0xec6b), 0x04},
+       {CCI_REG8(0xec81), 0x01},
+       {CCI_REG8(0xec9e), 0x2c},
+       {CCI_REG8(0xec9f), 0x01},
+       {CCI_REG8(0xec80), 0x01},
+       {CCI_REG8(0x2dc0), 0xbb},
+       {CCI_REG8(0x2dc1), 0x08},
+       {CCI_REG8(0xb7dc), 0x01},
+       {CCI_REG8(0xb7dd), 0x01},
+       {CCI_REG8(0xb7de), 0x01},
+       {CCI_REG8(0x97a2), 0x80},
+       {CCI_REG8(0x97a3), 0xac},
+       {CCI_REG8(0x97a6), 0x00},
+       {CCI_REG8(0x97a7), 0x4b},
+       {CCI_REG8(0x97ae), 0x20},
+       {CCI_REG8(0x97af), 0x35},
+       {CCI_REG8(0x95c1), 0x01},
+       {CCI_REG8(0xfff0), 0x01},
+       {CCI_REG8(0x98ac), 0x03},
+       {CCI_REG8(0xa248), 0x03},
+       {CCI_REG8(0xffff), 0x00},
+       {CCI_REG8(0x9782), 0x00},
+       {CCI_REG8(0xb708), 0x00},
+       {CCI_REG8(0x9783), 0x00},
+       {CCI_REG8(0xffff), 0x00},
+       {CCI_REG8(0x1981), 0x01},
+       {CCI_REG8(0x1982), 0x01},
+       {CCI_REG8(0x1983), 0x01},
+       {CCI_REG8(0x1984), 0x01},
+       {CCI_REG8(0x1985), 0x01},
+       {CCI_REG8(0x56a5), 0x01},
+       {CCI_REG8(0x571c), 0x01},
+       {CCI_REG8(0x571d), 0x00},
+       {CCI_REG8(0x9782), 0x98},
+       {CCI_REG8(0xb708), 0x98},
+       {CCI_REG8(0x9783), 0x09},
+       {CCI_REG8(0x1708), 0x00},
+       {CCI_REG8(0x1709), 0x00},
+       {CCI_REG8(0x170a), 0x00},
+       {CCI_REG8(0x1b40), 0x00},
+       {CCI_REG8(0x1808), 0x01},
+       {CCI_REG8(0xffff), 0x00},
+       {CCI_REG8(0x98b5), 0x00},
+       {CCI_REG8(0x98b6), 0xd8},
+       {CCI_REG8(0x98b7), 0xd8},
+       {CCI_REG8(0x98b8), 0xec},
+       {CCI_REG8(0x98ca), 0x0f},
+       {CCI_REG8(0x98cb), 0x55},
+       {CCI_REG8(0x98cc), 0x0b},
+       {CCI_REG8(0x98d2), 0xa0},
+       {CCI_REG8(0x98d3), 0x28},
+       {CCI_REG8(0x98ec), 0x38},
+       {CCI_REG8(0xc1a8), 0x38},
+       {CCI_REG8(0xc2bc), 0x38},
+       {CCI_REG8(0xc3d0), 0x38},
+       {CCI_REG8(0xc4e4), 0x38},
+       {CCI_REG8(0xc5f8), 0x38},
+       {CCI_REG8(0xc70c), 0x38},
+       {CCI_REG8(0x98ed), 0x00},
+       {CCI_REG8(0xc1a9), 0x00},
+       {CCI_REG8(0xc2bd), 0x00},
+       {CCI_REG8(0xc3d1), 0x00},
+       {CCI_REG8(0xc4e5), 0x00},
+       {CCI_REG8(0xc5f9), 0x00},
+       {CCI_REG8(0xc70d), 0x00},
+       {CCI_REG8(0x98ee), 0x00},
+       {CCI_REG8(0xc1aa), 0x00},
+       {CCI_REG8(0xc2be), 0x00},
+       {CCI_REG8(0xc3d2), 0x00},
+       {CCI_REG8(0xc4e6), 0x00},
+       {CCI_REG8(0xc5fa), 0x00},
+       {CCI_REG8(0xc70e), 0x00},
+       {CCI_REG8(0x98ef), 0x00},
+       {CCI_REG8(0xc1ab), 0x00},
+       {CCI_REG8(0xc2bf), 0x00},
+       {CCI_REG8(0xc3d3), 0x00},
+       {CCI_REG8(0xc4e7), 0x00},
+       {CCI_REG8(0xc5fb), 0x00},
+       {CCI_REG8(0xc70f), 0x00},
+       {CCI_REG8(0x98f0), 0x03},
+       {CCI_REG8(0xc1ac), 0x03},
+       {CCI_REG8(0xc2c0), 0x03},
+       {CCI_REG8(0xc3d4), 0x03},
+       {CCI_REG8(0xc4e8), 0x03},
+       {CCI_REG8(0xc5fc), 0x03},
+       {CCI_REG8(0xc710), 0x03},
+       {CCI_REG8(0x98fc), 0x4b},
+       {CCI_REG8(0xc1b8), 0x4b},
+       {CCI_REG8(0xc2cc), 0x4b},
+       {CCI_REG8(0xc3e0), 0x4b},
+       {CCI_REG8(0xc4f4), 0x4b},
+       {CCI_REG8(0xc608), 0x4b},
+       {CCI_REG8(0xc71c), 0x4b},
+       {CCI_REG8(0x98fd), 0x00},
+       {CCI_REG8(0xc1b9), 0x00},
+       {CCI_REG8(0xc2cd), 0x00},
+       {CCI_REG8(0xc3e1), 0x00},
+       {CCI_REG8(0xc4f5), 0x00},
+       {CCI_REG8(0xc609), 0x00},
+       {CCI_REG8(0xc71d), 0x00},
+       {CCI_REG8(0x98fe), 0x00},
+       {CCI_REG8(0xc1ba), 0x00},
+       {CCI_REG8(0xc2ce), 0x00},
+       {CCI_REG8(0xc3e2), 0x00},
+       {CCI_REG8(0xc4f6), 0x00},
+       {CCI_REG8(0xc60a), 0x00},
+       {CCI_REG8(0xc71e), 0x00},
+       {CCI_REG8(0x9900), 0x15},
+       {CCI_REG8(0xc1bc), 0x15},
+       {CCI_REG8(0xc2d0), 0x15},
+       {CCI_REG8(0xc3e4), 0x15},
+       {CCI_REG8(0xc4f8), 0x15},
+       {CCI_REG8(0xc60c), 0x15},
+       {CCI_REG8(0xc720), 0x15},
+       {CCI_REG8(0x9901), 0x00},
+       {CCI_REG8(0xc1bd), 0x00},
+       {CCI_REG8(0xc2d1), 0x00},
+       {CCI_REG8(0xc3e5), 0x00},
+       {CCI_REG8(0xc4f9), 0x00},
+       {CCI_REG8(0xc60d), 0x00},
+       {CCI_REG8(0xc721), 0x00},
+       {CCI_REG8(0x9902), 0x00},
+       {CCI_REG8(0xc1be), 0x00},
+       {CCI_REG8(0xc2d2), 0x00},
+       {CCI_REG8(0xc3e6), 0x00},
+       {CCI_REG8(0xc4fa), 0x00},
+       {CCI_REG8(0xc60e), 0x00},
+       {CCI_REG8(0xc722), 0x00},
+       {CCI_REG8(0x9904), 0x21},
+       {CCI_REG8(0xc1c0), 0x21},
+       {CCI_REG8(0xc2d4), 0x21},
+       {CCI_REG8(0xc3e8), 0x21},
+       {CCI_REG8(0xc4fc), 0x21},
+       {CCI_REG8(0xc610), 0x21},
+       {CCI_REG8(0xc724), 0x21},
+       {CCI_REG8(0x9905), 0x00},
+       {CCI_REG8(0xc1c1), 0x00},
+       {CCI_REG8(0xc2d5), 0x00},
+       {CCI_REG8(0xc3e9), 0x00},
+       {CCI_REG8(0xc4fd), 0x00},
+       {CCI_REG8(0xc611), 0x00},
+       {CCI_REG8(0xc725), 0x00},
+       {CCI_REG8(0x9906), 0x00},
+       {CCI_REG8(0xc1c2), 0x00},
+       {CCI_REG8(0xc2d6), 0x00},
+       {CCI_REG8(0xc3ea), 0x00},
+       {CCI_REG8(0xc4fe), 0x00},
+       {CCI_REG8(0xc612), 0x00},
+       {CCI_REG8(0xc726), 0x00},
+       {CCI_REG8(0x9908), 0x54},
+       {CCI_REG8(0xc1c4), 0x54},
+       {CCI_REG8(0xc2d8), 0x54},
+       {CCI_REG8(0xc3ec), 0x54},
+       {CCI_REG8(0xc500), 0x54},
+       {CCI_REG8(0xc614), 0x54},
+       {CCI_REG8(0xc728), 0x54},
+       {CCI_REG8(0x9909), 0x00},
+       {CCI_REG8(0xc1c5), 0x00},
+       {CCI_REG8(0xc2d9), 0x00},
+       {CCI_REG8(0xc3ed), 0x00},
+       {CCI_REG8(0xc501), 0x00},
+       {CCI_REG8(0xc615), 0x00},
+       {CCI_REG8(0xc729), 0x00},
+       {CCI_REG8(0x990a), 0x00},
+       {CCI_REG8(0xc1c6), 0x00},
+       {CCI_REG8(0xc2da), 0x00},
+       {CCI_REG8(0xc3ee), 0x00},
+       {CCI_REG8(0xc502), 0x00},
+       {CCI_REG8(0xc616), 0x00},
+       {CCI_REG8(0xc72a), 0x00},
+       {CCI_REG8(0x9921), 0x04},
+       {CCI_REG8(0x9923), 0x02},
+       {CCI_REG8(0x9925), 0x28},
+       {CCI_REG8(0x9926), 0x14},
+       {CCI_REG8(0x9938), 0x4b},
+       {CCI_REG8(0x993e), 0x15},
+       {CCI_REG8(0x9960), 0x01},
+       {CCI_REG8(0x9961), 0x03},
+       {CCI_REG8(0x9963), 0x02},
+       {CCI_REG8(0x9968), 0xb6},
+       {CCI_REG8(0x9969), 0x26},
+       {CCI_REG8(0x996a), 0x00},
+       {CCI_REG8(0x996b), 0x00},
+       {CCI_REG8(0x996c), 0xf8},
+       {CCI_REG8(0x996d), 0x2a},
+       {CCI_REG8(0x996e), 0x00},
+       {CCI_REG8(0x996f), 0x00},
+       {CCI_REG8(0x9970), 0x01},
+       {CCI_REG8(0x9971), 0x00},
+       {CCI_REG8(0x9972), 0x00},
+       {CCI_REG8(0x9973), 0x00},
+       {CCI_REG8(0x9975), 0x03},
+       {CCI_REG8(0x9976), 0x04},
+       {CCI_REG8(0x9982), 0xb4},
+       {CCI_REG8(0x9983), 0x00},
+       {CCI_REG8(0x99c8), 0xb0},
+       {CCI_REG8(0x99c9), 0x04},
+       {CCI_REG8(0x99ca), 0xb0},
+       {CCI_REG8(0x99cb), 0x04},
+       {CCI_REG8(0x99de), 0x64},
+       {CCI_REG8(0x99df), 0x64},
+       {CCI_REG8(0x99e0), 0x64},
+       {CCI_REG8(0x99e1), 0x64},
+       {CCI_REG8(0x99e2), 0x64},
+       {CCI_REG8(0x99e3), 0x64},
+       {CCI_REG8(0x99e4), 0x64},
+       {CCI_REG8(0x99e5), 0x64},
+       {CCI_REG8(0x99e6), 0x64},
+       {CCI_REG8(0x99e7), 0x64},
+       {CCI_REG8(0x99e8), 0x64},
+       {CCI_REG8(0x99e9), 0x64},
+       {CCI_REG8(0x99ea), 0x64},
+       {CCI_REG8(0x99eb), 0x64},
+       {CCI_REG8(0x99ec), 0x64},
+       {CCI_REG8(0x99ed), 0x64},
+       {CCI_REG8(0x99ee), 0x64},
+       {CCI_REG8(0x99ef), 0x64},
+       {CCI_REG8(0x99f0), 0x64},
+       {CCI_REG8(0x99f1), 0x64},
+       {CCI_REG8(0x99f2), 0x64},
+       {CCI_REG8(0x99f3), 0x64},
+       {CCI_REG8(0x99f4), 0x64},
+       {CCI_REG8(0x99f5), 0x64},
+       {CCI_REG8(0x99f6), 0x64},
+       {CCI_REG8(0x99f7), 0x64},
+       {CCI_REG8(0x99f8), 0x64},
+       {CCI_REG8(0x99f9), 0x64},
+       {CCI_REG8(0x99fa), 0x64},
+       {CCI_REG8(0x99fb), 0x64},
+       {CCI_REG8(0x99fc), 0x64},
+       {CCI_REG8(0x99fd), 0x64},
+       {CCI_REG8(0x99fe), 0x64},
+       {CCI_REG8(0x99ff), 0x64},
+       {CCI_REG8(0x9a00), 0x64},
+       {CCI_REG8(0x9a01), 0x64},
+       {CCI_REG8(0x9a02), 0x64},
+       {CCI_REG8(0x9a03), 0x64},
+       {CCI_REG8(0x9a04), 0x64},
+       {CCI_REG8(0x9a05), 0x64},
+       {CCI_REG8(0x9a07), 0x64},
+       {CCI_REG8(0x9a08), 0x64},
+       {CCI_REG8(0x9a09), 0x64},
+       {CCI_REG8(0x9a0a), 0x64},
+       {CCI_REG8(0x9a0b), 0x64},
+       {CCI_REG8(0x9a0c), 0x64},
+       {CCI_REG8(0x9a0d), 0x64},
+       {CCI_REG8(0x9a0e), 0x64},
+       {CCI_REG8(0x9a0f), 0x64},
+       {CCI_REG8(0x9a10), 0x64},
+       {CCI_REG8(0x9a11), 0x64},
+       {CCI_REG8(0x9a12), 0x64},
+       {CCI_REG8(0x9a13), 0x64},
+       {CCI_REG8(0x9a14), 0x64},
+       {CCI_REG8(0x9a15), 0x64},
+       {CCI_REG8(0x9a16), 0x64},
+       {CCI_REG8(0x9a17), 0x64},
+       {CCI_REG8(0x9a18), 0x64},
+       {CCI_REG8(0x9a19), 0x64},
+       {CCI_REG8(0x9a1a), 0x64},
+       {CCI_REG8(0x9a1b), 0x64},
+       {CCI_REG8(0x9a1c), 0x64},
+       {CCI_REG8(0x9a3a), 0x20},
+       {CCI_REG8(0x9a3b), 0x00},
+       {CCI_REG8(0x9a3c), 0x20},
+       {CCI_REG8(0x9a3d), 0x00},
+       {CCI_REG8(0x9a3e), 0x20},
+       {CCI_REG8(0x9a3f), 0x00},
+       {CCI_REG8(0x9a40), 0x20},
+       {CCI_REG8(0x9a41), 0x00},
+       {CCI_REG8(0x9a42), 0x20},
+       {CCI_REG8(0x9a43), 0x00},
+       {CCI_REG8(0x9a44), 0x20},
+       {CCI_REG8(0x9a45), 0x00},
+       {CCI_REG8(0x9a46), 0x20},
+       {CCI_REG8(0x9a47), 0x00},
+       {CCI_REG8(0x9a48), 0x30},
+       {CCI_REG8(0x9a49), 0x00},
+       {CCI_REG8(0x9a4a), 0x40},
+       {CCI_REG8(0x9a4b), 0x00},
+       {CCI_REG8(0x9a4c), 0x50},
+       {CCI_REG8(0x9a4d), 0x00},
+       {CCI_REG8(0x9a4e), 0x60},
+       {CCI_REG8(0x9a4f), 0x00},
+       {CCI_REG8(0x9a50), 0x70},
+       {CCI_REG8(0x9a51), 0x00},
+       {CCI_REG8(0x9a52), 0x80},
+       {CCI_REG8(0x9a53), 0x00},
+       {CCI_REG8(0x9a54), 0x90},
+       {CCI_REG8(0x9a55), 0x00},
+       {CCI_REG8(0x9a56), 0xa0},
+       {CCI_REG8(0x9a57), 0x00},
+       {CCI_REG8(0x9a58), 0xb0},
+       {CCI_REG8(0x9a59), 0x00},
+       {CCI_REG8(0x9a5a), 0xc0},
+       {CCI_REG8(0x9a5b), 0x00},
+       {CCI_REG8(0x9a5c), 0xc0},
+       {CCI_REG8(0x9a5d), 0x00},
+       {CCI_REG8(0x9a5f), 0x10},
+       {CCI_REG8(0x9a64), 0xff},
+       {CCI_REG8(0x9a65), 0xff},
+       {CCI_REG8(0x9a66), 0xff},
+       {CCI_REG8(0x9a67), 0xff},
+       {CCI_REG8(0x9be4), 0x02},
+       {CCI_REG8(0x9be5), 0x00},
+       {CCI_REG8(0x9be6), 0x00},
+       {CCI_REG8(0x9be7), 0x00},
+       {CCI_REG8(0x9bea), 0x54},
+       {CCI_REG8(0x9beb), 0x00},
+       {CCI_REG8(0x9bec), 0x54},
+       {CCI_REG8(0x9bed), 0x00},
+       {CCI_REG8(0x9bfa), 0x01},
+       {CCI_REG8(0x9bfc), 0x00},
+       {CCI_REG8(0x9bfd), 0x10},
+       {CCI_REG8(0x9bfe), 0x00},
+       {CCI_REG8(0x9c00), 0x00},
+       {CCI_REG8(0x9c01), 0x10},
+       {CCI_REG8(0x9c02), 0x00},
+       {CCI_REG8(0x9c04), 0x00},
+       {CCI_REG8(0x9c05), 0x10},
+       {CCI_REG8(0x9c06), 0x00},
+       {CCI_REG8(0x9c08), 0x00},
+       {CCI_REG8(0x9c09), 0x10},
+       {CCI_REG8(0x9c0a), 0x00},
+       {CCI_REG8(0x9c0c), 0x00},
+       {CCI_REG8(0x9c0d), 0x10},
+       {CCI_REG8(0x9c0e), 0x00},
+       {CCI_REG8(0x9c10), 0x00},
+       {CCI_REG8(0x9c11), 0x10},
+       {CCI_REG8(0x9c12), 0x00},
+       {CCI_REG8(0x9c14), 0x00},
+       {CCI_REG8(0x9c15), 0x10},
+       {CCI_REG8(0x9c16), 0x00},
+       {CCI_REG8(0x9c18), 0x00},
+       {CCI_REG8(0x9c19), 0x10},
+       {CCI_REG8(0x9c1a), 0x00},
+       {CCI_REG8(0x9c1c), 0x00},
+       {CCI_REG8(0x9c1d), 0x10},
+       {CCI_REG8(0x9c1e), 0x00},
+       {CCI_REG8(0x9c20), 0x00},
+       {CCI_REG8(0x9c21), 0x10},
+       {CCI_REG8(0x9c22), 0x00},
+       {CCI_REG8(0x9c24), 0x00},
+       {CCI_REG8(0x9c25), 0x10},
+       {CCI_REG8(0x9c26), 0x00},
+       {CCI_REG8(0x9c28), 0x00},
+       {CCI_REG8(0x9c29), 0x10},
+       {CCI_REG8(0x9c2a), 0x00},
+       {CCI_REG8(0x9c58), 0x21},
+       {CCI_REG8(0x9c5a), 0xc0},
+       {CCI_REG8(0xc1cc), 0xc0},
+       {CCI_REG8(0xc2e0), 0xc0},
+       {CCI_REG8(0xc3f4), 0xc0},
+       {CCI_REG8(0xc508), 0xc0},
+       {CCI_REG8(0xc61c), 0xc0},
+       {CCI_REG8(0xc730), 0xc0},
+       {CCI_REG8(0x9c5b), 0x5d},
+       {CCI_REG8(0xc1cd), 0x5d},
+       {CCI_REG8(0xc2e1), 0x5d},
+       {CCI_REG8(0xc3f5), 0x5d},
+       {CCI_REG8(0xc509), 0x5d},
+       {CCI_REG8(0xc61d), 0x5d},
+       {CCI_REG8(0xc731), 0x5d},
+       {CCI_REG8(0x9c5c), 0x80},
+       {CCI_REG8(0xc1ce), 0x80},
+       {CCI_REG8(0xc2e2), 0x80},
+       {CCI_REG8(0xc3f6), 0x80},
+       {CCI_REG8(0xc50a), 0x80},
+       {CCI_REG8(0xc61e), 0x80},
+       {CCI_REG8(0xc732), 0x80},
+       {CCI_REG8(0x9c5d), 0x57},
+       {CCI_REG8(0xc1cf), 0x57},
+       {CCI_REG8(0xc2e3), 0x57},
+       {CCI_REG8(0xc3f7), 0x57},
+       {CCI_REG8(0xc50b), 0x57},
+       {CCI_REG8(0xc61f), 0x57},
+       {CCI_REG8(0xc733), 0x57},
+       {CCI_REG8(0x9c60), 0x00},
+       {CCI_REG8(0xc1d2), 0x00},
+       {CCI_REG8(0xc2e6), 0x00},
+       {CCI_REG8(0xc3fa), 0x00},
+       {CCI_REG8(0xc50e), 0x00},
+       {CCI_REG8(0xc622), 0x00},
+       {CCI_REG8(0xc736), 0x00},
+       {CCI_REG8(0x9c61), 0x30},
+       {CCI_REG8(0xc1d3), 0x30},
+       {CCI_REG8(0xc2e7), 0x30},
+       {CCI_REG8(0xc3fb), 0x30},
+       {CCI_REG8(0xc50f), 0x30},
+       {CCI_REG8(0xc623), 0x30},
+       {CCI_REG8(0xc737), 0x30},
+       {CCI_REG8(0x9c62), 0x00},
+       {CCI_REG8(0xc1d4), 0x00},
+       {CCI_REG8(0xc2e8), 0x00},
+       {CCI_REG8(0xc3fc), 0x00},
+       {CCI_REG8(0xc510), 0x00},
+       {CCI_REG8(0xc624), 0x00},
+       {CCI_REG8(0xc738), 0x00},
+       {CCI_REG8(0x9c63), 0x00},
+       {CCI_REG8(0xc1d5), 0x00},
+       {CCI_REG8(0xc2e9), 0x00},
+       {CCI_REG8(0xc3fd), 0x00},
+       {CCI_REG8(0xc511), 0x00},
+       {CCI_REG8(0xc625), 0x00},
+       {CCI_REG8(0xc739), 0x00},
+       {CCI_REG8(0x9c64), 0x00},
+       {CCI_REG8(0xc1d6), 0x00},
+       {CCI_REG8(0xc2ea), 0x00},
+       {CCI_REG8(0xc3fe), 0x00},
+       {CCI_REG8(0xc512), 0x00},
+       {CCI_REG8(0xc626), 0x00},
+       {CCI_REG8(0xc73a), 0x00},
+       {CCI_REG8(0x9c65), 0x50},
+       {CCI_REG8(0xc1d7), 0x50},
+       {CCI_REG8(0xc2eb), 0x50},
+       {CCI_REG8(0xc3ff), 0x50},
+       {CCI_REG8(0xc513), 0x50},
+       {CCI_REG8(0xc627), 0x50},
+       {CCI_REG8(0xc73b), 0x50},
+       {CCI_REG8(0x9c66), 0x00},
+       {CCI_REG8(0xc1d8), 0x00},
+       {CCI_REG8(0xc2ec), 0x00},
+       {CCI_REG8(0xc400), 0x00},
+       {CCI_REG8(0xc514), 0x00},
+       {CCI_REG8(0xc628), 0x00},
+       {CCI_REG8(0xc73c), 0x00},
+       {CCI_REG8(0x9c67), 0x00},
+       {CCI_REG8(0xc1d9), 0x00},
+       {CCI_REG8(0xc2ed), 0x00},
+       {CCI_REG8(0xc401), 0x00},
+       {CCI_REG8(0xc515), 0x00},
+       {CCI_REG8(0xc629), 0x00},
+       {CCI_REG8(0xc73d), 0x00},
+       {CCI_REG8(0x9c6a), 0x00},
+       {CCI_REG8(0xc1dc), 0x00},
+       {CCI_REG8(0xc2f0), 0x00},
+       {CCI_REG8(0xc404), 0x00},
+       {CCI_REG8(0xc518), 0x00},
+       {CCI_REG8(0xc62c), 0x00},
+       {CCI_REG8(0xc740), 0x00},
+       {CCI_REG8(0x9c6b), 0xe0},
+       {CCI_REG8(0xc1dd), 0xe0},
+       {CCI_REG8(0xc2f1), 0xe0},
+       {CCI_REG8(0xc405), 0xe0},
+       {CCI_REG8(0xc519), 0xe0},
+       {CCI_REG8(0xc62d), 0xe0},
+       {CCI_REG8(0xc741), 0xe0},
+       {CCI_REG8(0x9c6c), 0x00},
+       {CCI_REG8(0xc1de), 0x00},
+       {CCI_REG8(0xc2f2), 0x00},
+       {CCI_REG8(0xc406), 0x00},
+       {CCI_REG8(0xc51a), 0x00},
+       {CCI_REG8(0xc62e), 0x00},
+       {CCI_REG8(0xc742), 0x00},
+       {CCI_REG8(0x9c6d), 0x30},
+       {CCI_REG8(0xc1df), 0x30},
+       {CCI_REG8(0xc2f3), 0x30},
+       {CCI_REG8(0xc407), 0x30},
+       {CCI_REG8(0xc51b), 0x30},
+       {CCI_REG8(0xc62f), 0x30},
+       {CCI_REG8(0xc743), 0x30},
+       {CCI_REG8(0x9c6e), 0x00},
+       {CCI_REG8(0xc1e0), 0x00},
+       {CCI_REG8(0xc2f4), 0x00},
+       {CCI_REG8(0xc408), 0x00},
+       {CCI_REG8(0xc51c), 0x00},
+       {CCI_REG8(0xc630), 0x00},
+       {CCI_REG8(0xc744), 0x00},
+       {CCI_REG8(0x9c6f), 0x00},
+       {CCI_REG8(0xc1e1), 0x00},
+       {CCI_REG8(0xc2f5), 0x00},
+       {CCI_REG8(0xc409), 0x00},
+       {CCI_REG8(0xc51d), 0x00},
+       {CCI_REG8(0xc631), 0x00},
+       {CCI_REG8(0xc745), 0x00},
+       {CCI_REG8(0x9c70), 0x00},
+       {CCI_REG8(0xc1e2), 0x00},
+       {CCI_REG8(0xc2f6), 0x00},
+       {CCI_REG8(0xc40a), 0x00},
+       {CCI_REG8(0xc51e), 0x00},
+       {CCI_REG8(0xc632), 0x00},
+       {CCI_REG8(0xc746), 0x00},
+       {CCI_REG8(0x9c71), 0x50},
+       {CCI_REG8(0xc1e3), 0x50},
+       {CCI_REG8(0xc2f7), 0x50},
+       {CCI_REG8(0xc40b), 0x50},
+       {CCI_REG8(0xc51f), 0x50},
+       {CCI_REG8(0xc633), 0x50},
+       {CCI_REG8(0xc747), 0x50},
+       {CCI_REG8(0x9c72), 0x00},
+       {CCI_REG8(0xc1e4), 0x00},
+       {CCI_REG8(0xc2f8), 0x00},
+       {CCI_REG8(0xc40c), 0x00},
+       {CCI_REG8(0xc520), 0x00},
+       {CCI_REG8(0xc634), 0x00},
+       {CCI_REG8(0xc748), 0x00},
+       {CCI_REG8(0x9c73), 0x00},
+       {CCI_REG8(0xc1e5), 0x00},
+       {CCI_REG8(0xc2f9), 0x00},
+       {CCI_REG8(0xc40d), 0x00},
+       {CCI_REG8(0xc521), 0x00},
+       {CCI_REG8(0xc635), 0x00},
+       {CCI_REG8(0xc749), 0x00},
+       {CCI_REG8(0x9c76), 0x00},
+       {CCI_REG8(0xc1e8), 0x00},
+       {CCI_REG8(0xc2fc), 0x00},
+       {CCI_REG8(0xc410), 0x00},
+       {CCI_REG8(0xc524), 0x00},
+       {CCI_REG8(0xc638), 0x00},
+       {CCI_REG8(0xc74c), 0x00},
+       {CCI_REG8(0x9c77), 0xe0},
+       {CCI_REG8(0xc1e9), 0xe0},
+       {CCI_REG8(0xc2fd), 0xe0},
+       {CCI_REG8(0xc411), 0xe0},
+       {CCI_REG8(0xc525), 0xe0},
+       {CCI_REG8(0xc639), 0xe0},
+       {CCI_REG8(0xc74d), 0xe0},
+       {CCI_REG8(0x9d00), 0x00},
+       {CCI_REG8(0x9d01), 0x10},
+       {CCI_REG8(0x9d02), 0x00},
+       {CCI_REG8(0x9d04), 0x00},
+       {CCI_REG8(0x9d05), 0x10},
+       {CCI_REG8(0x9d06), 0x00},
+       {CCI_REG8(0x9d08), 0x00},
+       {CCI_REG8(0x9d09), 0x10},
+       {CCI_REG8(0x9d0a), 0x00},
+       {CCI_REG8(0x9d0c), 0x00},
+       {CCI_REG8(0x9d0d), 0x10},
+       {CCI_REG8(0x9d0e), 0x00},
+       {CCI_REG8(0x9d10), 0x00},
+       {CCI_REG8(0x9d11), 0x10},
+       {CCI_REG8(0x9d12), 0x00},
+       {CCI_REG8(0x9d14), 0x00},
+       {CCI_REG8(0x9d15), 0x10},
+       {CCI_REG8(0x9d16), 0x00},
+       {CCI_REG8(0x9d18), 0x00},
+       {CCI_REG8(0x9d19), 0x10},
+       {CCI_REG8(0x9d1a), 0x00},
+       {CCI_REG8(0x9d1c), 0x00},
+       {CCI_REG8(0x9d1d), 0x10},
+       {CCI_REG8(0x9d1e), 0x00},
+       {CCI_REG8(0x9d20), 0x00},
+       {CCI_REG8(0x9d21), 0x10},
+       {CCI_REG8(0x9d22), 0x00},
+       {CCI_REG8(0x9d23), 0x00},
+       {CCI_REG8(0x9d24), 0x00},
+       {CCI_REG8(0x9d25), 0x10},
+       {CCI_REG8(0x9d26), 0x00},
+       {CCI_REG8(0x9d27), 0x00},
+       {CCI_REG8(0x9d28), 0x00},
+       {CCI_REG8(0x9d29), 0x10},
+       {CCI_REG8(0x9d2a), 0x00},
+       {CCI_REG8(0x9d2b), 0x00},
+       {CCI_REG8(0x9d2c), 0x00},
+       {CCI_REG8(0x9d2d), 0x10},
+       {CCI_REG8(0x9d2e), 0x00},
+       {CCI_REG8(0x9d2f), 0x00},
+       {CCI_REG8(0x9d30), 0x01},
+       {CCI_REG8(0x9d31), 0x00},
+       {CCI_REG8(0x9d32), 0x00},
+       {CCI_REG8(0x9d33), 0x00},
+       {CCI_REG8(0x9d34), 0x00},
+       {CCI_REG8(0x9d35), 0x00},
+       {CCI_REG8(0x9d38), 0x01},
+       {CCI_REG8(0x9d39), 0x00},
+       {CCI_REG8(0x9d3a), 0x00},
+       {CCI_REG8(0x9d3b), 0x00},
+       {CCI_REG8(0x9d3c), 0x00},
+       {CCI_REG8(0x9d3d), 0x00},
+       {CCI_REG8(0x9d40), 0x01},
+       {CCI_REG8(0x9d41), 0x00},
+       {CCI_REG8(0x9d42), 0x00},
+       {CCI_REG8(0x9d43), 0x00},
+       {CCI_REG8(0x9d44), 0x00},
+       {CCI_REG8(0x9d45), 0x00},
+       {CCI_REG8(0x9d48), 0x01},
+       {CCI_REG8(0x9d49), 0x00},
+       {CCI_REG8(0x9d4a), 0x00},
+       {CCI_REG8(0x9d4b), 0x00},
+       {CCI_REG8(0x9d4c), 0x00},
+       {CCI_REG8(0x9d4d), 0x00},
+       {CCI_REG8(0xa2e4), 0x23},
+       {CCI_REG8(0xa2e7), 0x01},
+       {CCI_REG8(0xa3cc), 0xaa},
+       {CCI_REG8(0xa3cd), 0x0f},
+       {CCI_REG8(0xa3ce), 0x81},
+       {CCI_REG8(0xa3cf), 0x0d},
+       {CCI_REG8(0xa3d0), 0xfc},
+       {CCI_REG8(0xa3d1), 0x00},
+       {CCI_REG8(0xa3d2), 0xc5},
+       {CCI_REG8(0xa3d3), 0x02},
+       {CCI_REG8(0xa3b0), 0xe6},
+       {CCI_REG8(0xc204), 0xe6},
+       {CCI_REG8(0xc318), 0xe6},
+       {CCI_REG8(0xc42c), 0xe6},
+       {CCI_REG8(0xc540), 0xe6},
+       {CCI_REG8(0xc654), 0xe6},
+       {CCI_REG8(0xc768), 0xe6},
+       {CCI_REG8(0xa3b1), 0x00},
+       {CCI_REG8(0xc205), 0x00},
+       {CCI_REG8(0xc319), 0x00},
+       {CCI_REG8(0xc42d), 0x00},
+       {CCI_REG8(0xc541), 0x00},
+       {CCI_REG8(0xc655), 0x00},
+       {CCI_REG8(0xc769), 0x00},
+       {CCI_REG8(0xa3b2), 0xe6},
+       {CCI_REG8(0xc206), 0xe6},
+       {CCI_REG8(0xc31a), 0xe6},
+       {CCI_REG8(0xc42e), 0xe6},
+       {CCI_REG8(0xc542), 0xe6},
+       {CCI_REG8(0xc656), 0xe6},
+       {CCI_REG8(0xc76a), 0xe6},
+       {CCI_REG8(0xa3b3), 0x00},
+       {CCI_REG8(0xc207), 0x00},
+       {CCI_REG8(0xc31b), 0x00},
+       {CCI_REG8(0xc42f), 0x00},
+       {CCI_REG8(0xc543), 0x00},
+       {CCI_REG8(0xc657), 0x00},
+       {CCI_REG8(0xc76b), 0x00},
+       {CCI_REG8(0x9e7c), 0x87},
+       {CCI_REG8(0x9e88), 0x6e},
+       {CCI_REG8(0x9e89), 0x87},
+       {CCI_REG8(0x9e8a), 0x9b},
+       {CCI_REG8(0x9e8b), 0xaf},
+       {CCI_REG8(0x9e8c), 0x6e},
+       {CCI_REG8(0x9e8d), 0x87},
+       {CCI_REG8(0x9e8e), 0x9b},
+       {CCI_REG8(0x9e8f), 0xaf},
+       {CCI_REG8(0x9e90), 0x28},
+       {CCI_REG8(0x9e91), 0x00},
+       {CCI_REG8(0x9e92), 0x50},
+       {CCI_REG8(0x9e93), 0x00},
+       {CCI_REG8(0x9e94), 0xb2},
+       {CCI_REG8(0x9e95), 0x0c},
+       {CCI_REG8(0x9e96), 0xa6},
+       {CCI_REG8(0x9e97), 0x0e},
+       {CCI_REG8(0x9e98), 0x28},
+       {CCI_REG8(0x9e99), 0x00},
+       {CCI_REG8(0x9e9a), 0x50},
+       {CCI_REG8(0x9e9b), 0x00},
+       {CCI_REG8(0x9e9c), 0xb2},
+       {CCI_REG8(0x9e9d), 0x0c},
+       {CCI_REG8(0x9e9e), 0xa6},
+       {CCI_REG8(0x9e9f), 0x0e},
+       {CCI_REG8(0x9ea0), 0x28},
+       {CCI_REG8(0x9ea1), 0x00},
+       {CCI_REG8(0x9ea2), 0x50},
+       {CCI_REG8(0x9ea3), 0x00},
+       {CCI_REG8(0x9ea4), 0xb2},
+       {CCI_REG8(0x9ea5), 0x0c},
+       {CCI_REG8(0x9ea6), 0xa6},
+       {CCI_REG8(0x9ea7), 0x0e},
+       {CCI_REG8(0x9ea8), 0x28},
+       {CCI_REG8(0x9ea9), 0x00},
+       {CCI_REG8(0x9eaa), 0x50},
+       {CCI_REG8(0x9eab), 0x00},
+       {CCI_REG8(0x9eac), 0xb2},
+       {CCI_REG8(0x9ead), 0x0c},
+       {CCI_REG8(0x9eae), 0xa6},
+       {CCI_REG8(0x9eaf), 0x0e},
+       {CCI_REG8(0x9eb0), 0x28},
+       {CCI_REG8(0x9eb1), 0x00},
+       {CCI_REG8(0x9eb2), 0x50},
+       {CCI_REG8(0x9eb3), 0x00},
+       {CCI_REG8(0x9eb4), 0xb2},
+       {CCI_REG8(0x9eb5), 0x0c},
+       {CCI_REG8(0x9eb6), 0xa6},
+       {CCI_REG8(0x9eb7), 0x0e},
+       {CCI_REG8(0x9eb8), 0x28},
+       {CCI_REG8(0x9eb9), 0x00},
+       {CCI_REG8(0x9eba), 0x50},
+       {CCI_REG8(0x9ebb), 0x00},
+       {CCI_REG8(0x9ebc), 0xb2},
+       {CCI_REG8(0x9ebd), 0x0c},
+       {CCI_REG8(0x9ebe), 0xa6},
+       {CCI_REG8(0x9ebf), 0x0e},
+       {CCI_REG8(0x9ec0), 0x28},
+       {CCI_REG8(0x9ec1), 0x00},
+       {CCI_REG8(0x9ec2), 0x50},
+       {CCI_REG8(0x9ec3), 0x00},
+       {CCI_REG8(0x9ec4), 0xb2},
+       {CCI_REG8(0x9ec5), 0x0c},
+       {CCI_REG8(0x9ec6), 0xa6},
+       {CCI_REG8(0x9ec7), 0x0e},
+       {CCI_REG8(0x9ed2), 0x01},
+       {CCI_REG8(0x9ed3), 0x01},
+       {CCI_REG8(0x9ed4), 0x01},
+       {CCI_REG8(0x9ed5), 0x01},
+       {CCI_REG8(0x9ed6), 0x01},
+       {CCI_REG8(0x9ed7), 0x01},
+       {CCI_REG8(0x9ed8), 0x01},
+       {CCI_REG8(0x9eda), 0xb2},
+       {CCI_REG8(0x9edb), 0x0c},
+       {CCI_REG8(0x9edc), 0xb2},
+       {CCI_REG8(0x9edd), 0x0c},
+       {CCI_REG8(0x9ede), 0xb2},
+       {CCI_REG8(0x9edf), 0x0c},
+       {CCI_REG8(0x9ee0), 0xb2},
+       {CCI_REG8(0x9ee1), 0x0c},
+       {CCI_REG8(0x9ee2), 0xa6},
+       {CCI_REG8(0x9ee3), 0x0e},
+       {CCI_REG8(0x9ee4), 0xa6},
+       {CCI_REG8(0x9ee5), 0x0e},
+       {CCI_REG8(0x9ee6), 0xa6},
+       {CCI_REG8(0x9ee7), 0x0e},
+       {CCI_REG8(0x9ee8), 0xa6},
+       {CCI_REG8(0x9ee9), 0x0e},
+       {CCI_REG8(0x9eea), 0xb2},
+       {CCI_REG8(0x9eeb), 0x0c},
+       {CCI_REG8(0x9eec), 0xb2},
+       {CCI_REG8(0x9eed), 0x0c},
+       {CCI_REG8(0x9eee), 0xb2},
+       {CCI_REG8(0x9eef), 0x0c},
+       {CCI_REG8(0x9ef0), 0xb2},
+       {CCI_REG8(0x9ef1), 0x0c},
+       {CCI_REG8(0x9ef2), 0xa6},
+       {CCI_REG8(0x9ef3), 0x0e},
+       {CCI_REG8(0x9ef4), 0xa6},
+       {CCI_REG8(0x9ef5), 0x0e},
+       {CCI_REG8(0x9ef6), 0xa6},
+       {CCI_REG8(0x9ef7), 0x0e},
+       {CCI_REG8(0x9ef8), 0xa6},
+       {CCI_REG8(0x9ef9), 0x0e},
+       {CCI_REG8(0x9efa), 0xb2},
+       {CCI_REG8(0x9efb), 0x0c},
+       {CCI_REG8(0x9efc), 0xb2},
+       {CCI_REG8(0x9efd), 0x0c},
+       {CCI_REG8(0x9efe), 0xb2},
+       {CCI_REG8(0x9eff), 0x0c},
+       {CCI_REG8(0x9f00), 0xb2},
+       {CCI_REG8(0x9f01), 0x0c},
+       {CCI_REG8(0x9f02), 0xa6},
+       {CCI_REG8(0x9f03), 0x0e},
+       {CCI_REG8(0x9f04), 0xa6},
+       {CCI_REG8(0x9f05), 0x0e},
+       {CCI_REG8(0x9f06), 0xa6},
+       {CCI_REG8(0x9f07), 0x0e},
+       {CCI_REG8(0x9f08), 0xa6},
+       {CCI_REG8(0x9f09), 0x0e},
+       {CCI_REG8(0x9f0a), 0xb2},
+       {CCI_REG8(0x9f0b), 0x0c},
+       {CCI_REG8(0x9f0c), 0xb2},
+       {CCI_REG8(0x9f0d), 0x0c},
+       {CCI_REG8(0x9f0e), 0xb2},
+       {CCI_REG8(0x9f0f), 0x0c},
+       {CCI_REG8(0x9f10), 0xb2},
+       {CCI_REG8(0x9f11), 0x0c},
+       {CCI_REG8(0x9f12), 0xa6},
+       {CCI_REG8(0x9f13), 0x0e},
+       {CCI_REG8(0x9f14), 0xa6},
+       {CCI_REG8(0x9f15), 0x0e},
+       {CCI_REG8(0x9f16), 0xa6},
+       {CCI_REG8(0x9f17), 0x0e},
+       {CCI_REG8(0x9f18), 0xa6},
+       {CCI_REG8(0x9f19), 0x0e},
+       {CCI_REG8(0x9f1a), 0xb2},
+       {CCI_REG8(0x9f1b), 0x0c},
+       {CCI_REG8(0x9f1c), 0xb2},
+       {CCI_REG8(0x9f1d), 0x0c},
+       {CCI_REG8(0x9f1e), 0xb2},
+       {CCI_REG8(0x9f1f), 0x0c},
+       {CCI_REG8(0x9f20), 0xb2},
+       {CCI_REG8(0x9f21), 0x0c},
+       {CCI_REG8(0x9f22), 0xa6},
+       {CCI_REG8(0x9f23), 0x0e},
+       {CCI_REG8(0x9f24), 0xa6},
+       {CCI_REG8(0x9f25), 0x0e},
+       {CCI_REG8(0x9f26), 0xa6},
+       {CCI_REG8(0x9f27), 0x0e},
+       {CCI_REG8(0x9f28), 0xa6},
+       {CCI_REG8(0x9f29), 0x0e},
+       {CCI_REG8(0x9f2a), 0xb2},
+       {CCI_REG8(0x9f2b), 0x0c},
+       {CCI_REG8(0x9f2c), 0xb2},
+       {CCI_REG8(0x9f2d), 0x0c},
+       {CCI_REG8(0x9f2e), 0xb2},
+       {CCI_REG8(0x9f2f), 0x0c},
+       {CCI_REG8(0x9f30), 0xb2},
+       {CCI_REG8(0x9f31), 0x0c},
+       {CCI_REG8(0x9f32), 0xa6},
+       {CCI_REG8(0x9f33), 0x0e},
+       {CCI_REG8(0x9f34), 0xa6},
+       {CCI_REG8(0x9f35), 0x0e},
+       {CCI_REG8(0x9f36), 0xa6},
+       {CCI_REG8(0x9f37), 0x0e},
+       {CCI_REG8(0x9f38), 0xa6},
+       {CCI_REG8(0x9f39), 0x0e},
+       {CCI_REG8(0x9f3a), 0xb2},
+       {CCI_REG8(0x9f3b), 0x0c},
+       {CCI_REG8(0x9f3c), 0xb2},
+       {CCI_REG8(0x9f3d), 0x0c},
+       {CCI_REG8(0x9f3e), 0xb2},
+       {CCI_REG8(0x9f3f), 0x0c},
+       {CCI_REG8(0x9f40), 0xb2},
+       {CCI_REG8(0x9f41), 0x0c},
+       {CCI_REG8(0x9f42), 0xa6},
+       {CCI_REG8(0x9f43), 0x0e},
+       {CCI_REG8(0x9f44), 0xa6},
+       {CCI_REG8(0x9f45), 0x0e},
+       {CCI_REG8(0x9f46), 0xa6},
+       {CCI_REG8(0x9f47), 0x0e},
+       {CCI_REG8(0x9f48), 0xa6},
+       {CCI_REG8(0x9f49), 0x0e},
+       {CCI_REG8(0x9f4a), 0xb2},
+       {CCI_REG8(0x9f4b), 0x0c},
+       {CCI_REG8(0x9f4c), 0xb2},
+       {CCI_REG8(0x9f4d), 0x0c},
+       {CCI_REG8(0x9f4e), 0xb2},
+       {CCI_REG8(0x9f4f), 0x0c},
+       {CCI_REG8(0x9f50), 0xb2},
+       {CCI_REG8(0x9f51), 0x0c},
+       {CCI_REG8(0x9f52), 0xa6},
+       {CCI_REG8(0x9f53), 0x0e},
+       {CCI_REG8(0x9f54), 0xa6},
+       {CCI_REG8(0x9f55), 0x0e},
+       {CCI_REG8(0x9f56), 0xa6},
+       {CCI_REG8(0x9f57), 0x0e},
+       {CCI_REG8(0x9f58), 0xa6},
+       {CCI_REG8(0x9f59), 0x0e},
+       {CCI_REG8(0x9f5a), 0xd0},
+       {CCI_REG8(0x9f5b), 0x07},
+       {CCI_REG8(0x9f5c), 0xd0},
+       {CCI_REG8(0x9f5d), 0x07},
+       {CCI_REG8(0x9f5e), 0xd0},
+       {CCI_REG8(0x9f5f), 0x07},
+       {CCI_REG8(0x9f60), 0xd0},
+       {CCI_REG8(0x9f61), 0x07},
+       {CCI_REG8(0x9f62), 0xc4},
+       {CCI_REG8(0x9f63), 0x09},
+       {CCI_REG8(0x9f64), 0xc4},
+       {CCI_REG8(0x9f65), 0x09},
+       {CCI_REG8(0x9f66), 0xc4},
+       {CCI_REG8(0x9f67), 0x09},
+       {CCI_REG8(0x9f68), 0xc4},
+       {CCI_REG8(0x9f69), 0x09},
+       {CCI_REG8(0x9f6a), 0xd0},
+       {CCI_REG8(0x9f6b), 0x07},
+       {CCI_REG8(0x9f6c), 0xd0},
+       {CCI_REG8(0x9f6d), 0x07},
+       {CCI_REG8(0x9f6e), 0xd0},
+       {CCI_REG8(0x9f6f), 0x07},
+       {CCI_REG8(0x9f70), 0xd0},
+       {CCI_REG8(0x9f71), 0x07},
+       {CCI_REG8(0x9f72), 0xc4},
+       {CCI_REG8(0x9f73), 0x09},
+       {CCI_REG8(0x9f74), 0xc4},
+       {CCI_REG8(0x9f75), 0x09},
+       {CCI_REG8(0x9f76), 0xc4},
+       {CCI_REG8(0x9f77), 0x09},
+       {CCI_REG8(0x9f78), 0xc4},
+       {CCI_REG8(0x9f79), 0x09},
+       {CCI_REG8(0x9f7a), 0xd0},
+       {CCI_REG8(0x9f7b), 0x07},
+       {CCI_REG8(0x9f7c), 0xd0},
+       {CCI_REG8(0x9f7d), 0x07},
+       {CCI_REG8(0x9f7e), 0xd0},
+       {CCI_REG8(0x9f7f), 0x07},
+       {CCI_REG8(0x9f80), 0xd0},
+       {CCI_REG8(0x9f81), 0x07},
+       {CCI_REG8(0x9f82), 0xc4},
+       {CCI_REG8(0x9f83), 0x09},
+       {CCI_REG8(0x9f84), 0xc4},
+       {CCI_REG8(0x9f85), 0x09},
+       {CCI_REG8(0x9f86), 0xc4},
+       {CCI_REG8(0x9f87), 0x09},
+       {CCI_REG8(0x9f88), 0xc4},
+       {CCI_REG8(0x9f89), 0x09},
+       {CCI_REG8(0x9f8a), 0xd0},
+       {CCI_REG8(0x9f8b), 0x07},
+       {CCI_REG8(0x9f8c), 0xd0},
+       {CCI_REG8(0x9f8d), 0x07},
+       {CCI_REG8(0x9f8e), 0xd0},
+       {CCI_REG8(0x9f8f), 0x07},
+       {CCI_REG8(0x9f90), 0xd0},
+       {CCI_REG8(0x9f91), 0x07},
+       {CCI_REG8(0x9f92), 0xc4},
+       {CCI_REG8(0x9f93), 0x09},
+       {CCI_REG8(0x9f94), 0xc4},
+       {CCI_REG8(0x9f95), 0x09},
+       {CCI_REG8(0x9f96), 0xc4},
+       {CCI_REG8(0x9f97), 0x09},
+       {CCI_REG8(0x9f98), 0xc4},
+       {CCI_REG8(0x9f99), 0x09},
+       {CCI_REG8(0x9f9a), 0xd0},
+       {CCI_REG8(0x9f9b), 0x07},
+       {CCI_REG8(0x9f9c), 0xd0},
+       {CCI_REG8(0x9f9d), 0x07},
+       {CCI_REG8(0x9f9e), 0xd0},
+       {CCI_REG8(0x9f9f), 0x07},
+       {CCI_REG8(0x9fa0), 0xd0},
+       {CCI_REG8(0x9fa1), 0x07},
+       {CCI_REG8(0x9fa2), 0xc4},
+       {CCI_REG8(0x9fa3), 0x09},
+       {CCI_REG8(0x9fa4), 0xc4},
+       {CCI_REG8(0x9fa5), 0x09},
+       {CCI_REG8(0x9fa6), 0xc4},
+       {CCI_REG8(0x9fa7), 0x09},
+       {CCI_REG8(0x9fa8), 0xc4},
+       {CCI_REG8(0x9fa9), 0x09},
+       {CCI_REG8(0x9faa), 0xd0},
+       {CCI_REG8(0x9fab), 0x07},
+       {CCI_REG8(0x9fac), 0xd0},
+       {CCI_REG8(0x9fad), 0x07},
+       {CCI_REG8(0x9fae), 0xd0},
+       {CCI_REG8(0x9faf), 0x07},
+       {CCI_REG8(0x9fb0), 0xd0},
+       {CCI_REG8(0x9fb1), 0x07},
+       {CCI_REG8(0x9fb2), 0xc4},
+       {CCI_REG8(0x9fb3), 0x09},
+       {CCI_REG8(0x9fb4), 0xc4},
+       {CCI_REG8(0x9fb5), 0x09},
+       {CCI_REG8(0x9fb6), 0xc4},
+       {CCI_REG8(0x9fb7), 0x09},
+       {CCI_REG8(0x9fb8), 0xc4},
+       {CCI_REG8(0x9fb9), 0x09},
+       {CCI_REG8(0x9fba), 0xd0},
+       {CCI_REG8(0x9fbb), 0x07},
+       {CCI_REG8(0x9fbc), 0xd0},
+       {CCI_REG8(0x9fbd), 0x07},
+       {CCI_REG8(0x9fbe), 0xd0},
+       {CCI_REG8(0x9fbf), 0x07},
+       {CCI_REG8(0x9fc0), 0xd0},
+       {CCI_REG8(0x9fc1), 0x07},
+       {CCI_REG8(0x9fc2), 0xc4},
+       {CCI_REG8(0x9fc3), 0x09},
+       {CCI_REG8(0x9fc4), 0xc4},
+       {CCI_REG8(0x9fc5), 0x09},
+       {CCI_REG8(0x9fc6), 0xc4},
+       {CCI_REG8(0x9fc7), 0x09},
+       {CCI_REG8(0x9fc8), 0xc4},
+       {CCI_REG8(0x9fc9), 0x09},
+       {CCI_REG8(0x9fca), 0xd0},
+       {CCI_REG8(0x9fcb), 0x07},
+       {CCI_REG8(0x9fcc), 0xd0},
+       {CCI_REG8(0x9fcd), 0x07},
+       {CCI_REG8(0x9fce), 0xd0},
+       {CCI_REG8(0x9fcf), 0x07},
+       {CCI_REG8(0x9fd0), 0xd0},
+       {CCI_REG8(0x9fd1), 0x07},
+       {CCI_REG8(0x9fd2), 0xc4},
+       {CCI_REG8(0x9fd3), 0x09},
+       {CCI_REG8(0x9fd4), 0xc4},
+       {CCI_REG8(0x9fd5), 0x09},
+       {CCI_REG8(0x9fd6), 0xc4},
+       {CCI_REG8(0x9fd7), 0x09},
+       {CCI_REG8(0x9fd8), 0xc4},
+       {CCI_REG8(0x9fd9), 0x09},
+       {CCI_REG8(0x9fda), 0xd0},
+       {CCI_REG8(0x9fdb), 0x07},
+       {CCI_REG8(0x9fdc), 0xd0},
+       {CCI_REG8(0x9fdd), 0x07},
+       {CCI_REG8(0x9fde), 0xd0},
+       {CCI_REG8(0x9fdf), 0x07},
+       {CCI_REG8(0x9fe0), 0xd0},
+       {CCI_REG8(0x9fe1), 0x07},
+       {CCI_REG8(0x9fe2), 0xc4},
+       {CCI_REG8(0x9fe3), 0x09},
+       {CCI_REG8(0x9fe4), 0xc4},
+       {CCI_REG8(0x9fe5), 0x09},
+       {CCI_REG8(0x9fe6), 0xc4},
+       {CCI_REG8(0x9fe7), 0x09},
+       {CCI_REG8(0x9fe8), 0xc4},
+       {CCI_REG8(0x9fe9), 0x09},
+       {CCI_REG8(0x9fea), 0xd0},
+       {CCI_REG8(0x9feb), 0x07},
+       {CCI_REG8(0x9fec), 0xd0},
+       {CCI_REG8(0x9fed), 0x07},
+       {CCI_REG8(0x9fee), 0xd0},
+       {CCI_REG8(0x9fef), 0x07},
+       {CCI_REG8(0x9ff0), 0xd0},
+       {CCI_REG8(0x9ff1), 0x07},
+       {CCI_REG8(0x9ff2), 0xc4},
+       {CCI_REG8(0x9ff3), 0x09},
+       {CCI_REG8(0x9ff4), 0xc4},
+       {CCI_REG8(0x9ff5), 0x09},
+       {CCI_REG8(0x9ff6), 0xc4},
+       {CCI_REG8(0x9ff7), 0x09},
+       {CCI_REG8(0x9ff8), 0xc4},
+       {CCI_REG8(0x9ff9), 0x09},
+       {CCI_REG8(0x9ffa), 0xd0},
+       {CCI_REG8(0x9ffb), 0x07},
+       {CCI_REG8(0x9ffc), 0xd0},
+       {CCI_REG8(0x9ffd), 0x07},
+       {CCI_REG8(0x9ffe), 0xd0},
+       {CCI_REG8(0x9fff), 0x07},
+       {CCI_REG8(0xa000), 0xd0},
+       {CCI_REG8(0xa001), 0x07},
+       {CCI_REG8(0xa002), 0xc4},
+       {CCI_REG8(0xa003), 0x09},
+       {CCI_REG8(0xa004), 0xc4},
+       {CCI_REG8(0xa005), 0x09},
+       {CCI_REG8(0xa006), 0xc4},
+       {CCI_REG8(0xa007), 0x09},
+       {CCI_REG8(0xa008), 0xc4},
+       {CCI_REG8(0xa009), 0x09},
+       {CCI_REG8(0xa00a), 0xd0},
+       {CCI_REG8(0xa00b), 0x07},
+       {CCI_REG8(0xa00c), 0xd0},
+       {CCI_REG8(0xa00d), 0x07},
+       {CCI_REG8(0xa00e), 0xd0},
+       {CCI_REG8(0xa00f), 0x07},
+       {CCI_REG8(0xa010), 0xd0},
+       {CCI_REG8(0xa011), 0x07},
+       {CCI_REG8(0xa012), 0xc4},
+       {CCI_REG8(0xa013), 0x09},
+       {CCI_REG8(0xa014), 0xc4},
+       {CCI_REG8(0xa015), 0x09},
+       {CCI_REG8(0xa016), 0xc4},
+       {CCI_REG8(0xa017), 0x09},
+       {CCI_REG8(0xa018), 0xc4},
+       {CCI_REG8(0xa019), 0x09},
+       {CCI_REG8(0xa044), 0x4b},
+       {CCI_REG8(0xa045), 0x00},
+       {CCI_REG8(0xa046), 0x4b},
+       {CCI_REG8(0xa047), 0x00},
+       {CCI_REG8(0xa048), 0x4b},
+       {CCI_REG8(0xa049), 0x00},
+       {CCI_REG8(0xa04a), 0x4b},
+       {CCI_REG8(0xa04b), 0x00},
+       {CCI_REG8(0xa04c), 0x15},
+       {CCI_REG8(0xa04d), 0x00},
+       {CCI_REG8(0xa04e), 0x15},
+       {CCI_REG8(0xa04f), 0x00},
+       {CCI_REG8(0xa050), 0x15},
+       {CCI_REG8(0xa051), 0x00},
+       {CCI_REG8(0xa052), 0x15},
+       {CCI_REG8(0xa053), 0x00},
+       {CCI_REG8(0xa054), 0x28},
+       {CCI_REG8(0xa055), 0x00},
+       {CCI_REG8(0xa056), 0x28},
+       {CCI_REG8(0xa057), 0x00},
+       {CCI_REG8(0xa058), 0x28},
+       {CCI_REG8(0xa059), 0x00},
+       {CCI_REG8(0xa05a), 0x28},
+       {CCI_REG8(0xa05b), 0x00},
+       {CCI_REG8(0xa05c), 0x28},
+       {CCI_REG8(0xa05d), 0x00},
+       {CCI_REG8(0xa05e), 0x28},
+       {CCI_REG8(0xa05f), 0x00},
+       {CCI_REG8(0xa060), 0x28},
+       {CCI_REG8(0xa061), 0x00},
+       {CCI_REG8(0xa062), 0x28},
+       {CCI_REG8(0xa063), 0x00},
+       {CCI_REG8(0xa064), 0x21},
+       {CCI_REG8(0xa065), 0x00},
+       {CCI_REG8(0xa066), 0x21},
+       {CCI_REG8(0xa067), 0x00},
+       {CCI_REG8(0xa068), 0x21},
+       {CCI_REG8(0xa069), 0x00},
+       {CCI_REG8(0xa06a), 0x21},
+       {CCI_REG8(0xa06b), 0x00},
+       {CCI_REG8(0xa076), 0x21},
+       {CCI_REG8(0xa077), 0x00},
+       {CCI_REG8(0xa078), 0x21},
+       {CCI_REG8(0xa079), 0x00},
+       {CCI_REG8(0xa07a), 0x21},
+       {CCI_REG8(0xa07b), 0x00},
+       {CCI_REG8(0xa07c), 0x21},
+       {CCI_REG8(0xa07d), 0x00},
+       {CCI_REG8(0xa07e), 0x28},
+       {CCI_REG8(0xa07f), 0x00},
+       {CCI_REG8(0xa080), 0x28},
+       {CCI_REG8(0xa081), 0x00},
+       {CCI_REG8(0xa082), 0x28},
+       {CCI_REG8(0xa083), 0x00},
+       {CCI_REG8(0xa084), 0x28},
+       {CCI_REG8(0xa085), 0x00},
+       {CCI_REG8(0xa086), 0x54},
+       {CCI_REG8(0xa087), 0x00},
+       {CCI_REG8(0xa088), 0x54},
+       {CCI_REG8(0xa089), 0x00},
+       {CCI_REG8(0xa08a), 0x54},
+       {CCI_REG8(0xa08b), 0x00},
+       {CCI_REG8(0xa08c), 0x54},
+       {CCI_REG8(0xa08d), 0x00},
+       {CCI_REG8(0xa09a), 0xa6},
+       {CCI_REG8(0xa09b), 0x0e},
+       {CCI_REG8(0xa09c), 0xa6},
+       {CCI_REG8(0xa09d), 0x0e},
+       {CCI_REG8(0xa09e), 0xa6},
+       {CCI_REG8(0xa09f), 0x0e},
+       {CCI_REG8(0xa0a0), 0xa6},
+       {CCI_REG8(0xa0a1), 0x0e},
+       {CCI_REG8(0xa0a2), 0xa6},
+       {CCI_REG8(0xa0a3), 0x0e},
+       {CCI_REG8(0xa0a4), 0xa6},
+       {CCI_REG8(0xa0a5), 0x0e},
+       {CCI_REG8(0xa0a6), 0xa6},
+       {CCI_REG8(0xa0a7), 0x0e},
+       {CCI_REG8(0xa0a8), 0xa6},
+       {CCI_REG8(0xa0a9), 0x0e},
+       {CCI_REG8(0xa0aa), 0xa6},
+       {CCI_REG8(0xa0ab), 0x0e},
+       {CCI_REG8(0xa0ac), 0xa6},
+       {CCI_REG8(0xa0ad), 0x0e},
+       {CCI_REG8(0xa0ae), 0xa6},
+       {CCI_REG8(0xa0af), 0x0e},
+       {CCI_REG8(0xa0b0), 0xa6},
+       {CCI_REG8(0xa0b1), 0x0e},
+       {CCI_REG8(0xa0bc), 0xfe},
+       {CCI_REG8(0xa0bd), 0x01},
+       {CCI_REG8(0xa0be), 0xfe},
+       {CCI_REG8(0xa0bf), 0x01},
+       {CCI_REG8(0xa0c0), 0xfe},
+       {CCI_REG8(0xa0c1), 0x01},
+       {CCI_REG8(0xa0c2), 0xfe},
+       {CCI_REG8(0xa0c3), 0x01},
+       {CCI_REG8(0xa0c4), 0xfc},
+       {CCI_REG8(0xa0c5), 0x03},
+       {CCI_REG8(0xa0c6), 0xfc},
+       {CCI_REG8(0xa0c7), 0x03},
+       {CCI_REG8(0xa0c8), 0xfc},
+       {CCI_REG8(0xa0c9), 0x03},
+       {CCI_REG8(0xa0ca), 0xfc},
+       {CCI_REG8(0xa0cb), 0x03},
+       {CCI_REG8(0xa0cc), 0xfe},
+       {CCI_REG8(0xa0cd), 0x01},
+       {CCI_REG8(0xa0ce), 0xfe},
+       {CCI_REG8(0xa0cf), 0x01},
+       {CCI_REG8(0xa0d0), 0xfe},
+       {CCI_REG8(0xa0d1), 0x01},
+       {CCI_REG8(0xa0d2), 0xfe},
+       {CCI_REG8(0xa0d3), 0x01},
+       {CCI_REG8(0xa0d4), 0xfc},
+       {CCI_REG8(0xa0d5), 0x03},
+       {CCI_REG8(0xa0d6), 0xfc},
+       {CCI_REG8(0xa0d7), 0x03},
+       {CCI_REG8(0xa0d8), 0xfc},
+       {CCI_REG8(0xa0d9), 0x03},
+       {CCI_REG8(0xa0da), 0xfc},
+       {CCI_REG8(0xa0db), 0x03},
+       {CCI_REG8(0xa0dc), 0xfe},
+       {CCI_REG8(0xa0dd), 0x01},
+       {CCI_REG8(0xa0de), 0xfe},
+       {CCI_REG8(0xa0df), 0x01},
+       {CCI_REG8(0xa0e0), 0xfe},
+       {CCI_REG8(0xa0e1), 0x01},
+       {CCI_REG8(0xa0e2), 0xfe},
+       {CCI_REG8(0xa0e3), 0x01},
+       {CCI_REG8(0xa0e4), 0xfc},
+       {CCI_REG8(0xa0e5), 0x03},
+       {CCI_REG8(0xa0e6), 0xfc},
+       {CCI_REG8(0xa0e7), 0x03},
+       {CCI_REG8(0xa0e8), 0xfc},
+       {CCI_REG8(0xa0e9), 0x03},
+       {CCI_REG8(0xa0ea), 0xfc},
+       {CCI_REG8(0xa0eb), 0x03},
+       {CCI_REG8(0xa0ec), 0xfe},
+       {CCI_REG8(0xa0ed), 0x01},
+       {CCI_REG8(0xa0ee), 0xfe},
+       {CCI_REG8(0xa0ef), 0x01},
+       {CCI_REG8(0xa0f0), 0xfe},
+       {CCI_REG8(0xa0f1), 0x01},
+       {CCI_REG8(0xa0f2), 0xfe},
+       {CCI_REG8(0xa0f3), 0x01},
+       {CCI_REG8(0xa0f4), 0xfc},
+       {CCI_REG8(0xa0f5), 0x03},
+       {CCI_REG8(0xa0f6), 0xfc},
+       {CCI_REG8(0xa0f7), 0x03},
+       {CCI_REG8(0xa0f8), 0xfc},
+       {CCI_REG8(0xa0f9), 0x03},
+       {CCI_REG8(0xa0fa), 0xfc},
+       {CCI_REG8(0xa0fb), 0x03},
+       {CCI_REG8(0xa11c), 0x01},
+       {CCI_REG8(0xa126), 0x00},
+       {CCI_REG8(0xa127), 0x04},
+       {CCI_REG8(0xa128), 0x00},
+       {CCI_REG8(0xa129), 0x02},
+       {CCI_REG8(0xa12a), 0x00},
+       {CCI_REG8(0xa12b), 0x02},
+       {CCI_REG8(0xa12c), 0x00},
+       {CCI_REG8(0xa12d), 0x02},
+       {CCI_REG8(0xa12e), 0x00},
+       {CCI_REG8(0xa12f), 0x02},
+       {CCI_REG8(0xa130), 0x00},
+       {CCI_REG8(0xa131), 0x02},
+       {CCI_REG8(0xa132), 0x00},
+       {CCI_REG8(0xa133), 0x02},
+       {CCI_REG8(0xa134), 0x00},
+       {CCI_REG8(0xa135), 0x02},
+       {CCI_REG8(0xa136), 0x00},
+       {CCI_REG8(0xa137), 0x02},
+       {CCI_REG8(0xa138), 0xa6},
+       {CCI_REG8(0xa139), 0x0e},
+       {CCI_REG8(0xa13a), 0xa6},
+       {CCI_REG8(0xa13b), 0x0e},
+       {CCI_REG8(0xa13c), 0xa6},
+       {CCI_REG8(0xa13d), 0x0e},
+       {CCI_REG8(0xa13e), 0xa6},
+       {CCI_REG8(0xa13f), 0x0e},
+       {CCI_REG8(0xa140), 0xa6},
+       {CCI_REG8(0xa141), 0x0e},
+       {CCI_REG8(0xa142), 0xa6},
+       {CCI_REG8(0xa143), 0x0e},
+       {CCI_REG8(0xa144), 0xa6},
+       {CCI_REG8(0xa145), 0x0e},
+       {CCI_REG8(0xa146), 0xa6},
+       {CCI_REG8(0xa147), 0x0e},
+       {CCI_REG8(0xa148), 0xa6},
+       {CCI_REG8(0xa149), 0x0e},
+       {CCI_REG8(0xa14a), 0xa6},
+       {CCI_REG8(0xa14b), 0x0e},
+       {CCI_REG8(0xa14c), 0xa6},
+       {CCI_REG8(0xa14d), 0x0e},
+       {CCI_REG8(0xa14e), 0xa6},
+       {CCI_REG8(0xa14f), 0x0e},
+       {CCI_REG8(0xa150), 0xa6},
+       {CCI_REG8(0xa151), 0x0e},
+       {CCI_REG8(0xa152), 0xa6},
+       {CCI_REG8(0xa153), 0x0e},
+       {CCI_REG8(0xa154), 0xa6},
+       {CCI_REG8(0xa155), 0x0e},
+       {CCI_REG8(0xa156), 0xa6},
+       {CCI_REG8(0xa157), 0x0e},
+       {CCI_REG8(0xa15e), 0x09},
+       {CCI_REG8(0xa15f), 0x08},
+       {CCI_REG8(0xa160), 0x10},
+       {CCI_REG8(0xa161), 0x09},
+       {CCI_REG8(0xa162), 0x01},
+       {CCI_REG8(0xa163), 0x00},
+       {CCI_REG8(0xa166), 0x2f},
+       {CCI_REG8(0xa167), 0x00},
+       {CCI_REG8(0xa168), 0x01},
+       {CCI_REG8(0xa169), 0x00},
+       {CCI_REG8(0xa16a), 0x00},
+       {CCI_REG8(0xa16b), 0x00},
+       {CCI_REG8(0xa16c), 0x00},
+       {CCI_REG8(0xa16d), 0x00},
+       {CCI_REG8(0xa16e), 0x00},
+       {CCI_REG8(0xa16f), 0x00},
+       {CCI_REG8(0xa170), 0x00},
+       {CCI_REG8(0xa171), 0x00},
+       {CCI_REG8(0xa172), 0x33},
+       {CCI_REG8(0xa173), 0x00},
+       {CCI_REG8(0xa174), 0x33},
+       {CCI_REG8(0xa175), 0x00},
+       {CCI_REG8(0xa176), 0x33},
+       {CCI_REG8(0xa177), 0x00},
+       {CCI_REG8(0xa178), 0x33},
+       {CCI_REG8(0xa179), 0x00},
+       {CCI_REG8(0xa17c), 0xde},
+       {CCI_REG8(0xa17d), 0x00},
+       {CCI_REG8(0xa17e), 0xea},
+       {CCI_REG8(0xa17f), 0x00},
+       {CCI_REG8(0xa180), 0xde},
+       {CCI_REG8(0xa181), 0x00},
+       {CCI_REG8(0xa182), 0xea},
+       {CCI_REG8(0xa183), 0x00},
+       {CCI_REG8(0xa184), 0xde},
+       {CCI_REG8(0xa185), 0x00},
+       {CCI_REG8(0xa186), 0xea},
+       {CCI_REG8(0xa187), 0x00},
+       {CCI_REG8(0xa18a), 0x87},
+       {CCI_REG8(0xa18b), 0x87},
+       {CCI_REG8(0xa414), 0x67},
+       {CCI_REG8(0xa415), 0x09},
+       {CCI_REG8(0xa416), 0xd8},
+       {CCI_REG8(0xa417), 0x1a},
+       {CCI_REG8(0xa418), 0xb4},
+       {CCI_REG8(0xa419), 0x0c},
+       {CCI_REG8(0xa41a), 0x7e},
+       {CCI_REG8(0xa41b), 0x15},
+       {CCI_REG8(0xa41c), 0x01},
+       {CCI_REG8(0xa41d), 0x10},
+       {CCI_REG8(0xa41e), 0x24},
+       {CCI_REG8(0xa41f), 0x10},
+       {CCI_REG8(0xa420), 0x1a},
+       {CCI_REG8(0xa421), 0x14},
+       {CCI_REG8(0xa422), 0x6a},
+       {CCI_REG8(0xa423), 0x0e},
+       {CCI_REG8(0xa424), 0xd5},
+       {CCI_REG8(0xa425), 0x19},
+       {CCI_REG8(0xa426), 0xd5},
+       {CCI_REG8(0xa427), 0x0c},
+       {CCI_REG8(0xa428), 0xa9},
+       {CCI_REG8(0xa429), 0x0d},
+       {CCI_REG8(0xa42a), 0xe1},
+       {CCI_REG8(0xa42b), 0x13},
+       {CCI_REG8(0xa42c), 0x10},
+       {CCI_REG8(0xa42d), 0x0e},
+       {CCI_REG8(0xa42e), 0x47},
+       {CCI_REG8(0xa42f), 0x0f},
+       {CCI_REG8(0xa6b1), 0x01},
+       {CCI_REG8(0xa6da), 0x23},
+       {CCI_REG8(0xa6db), 0x00},
+       {CCI_REG8(0xa6dc), 0x20},
+       {CCI_REG8(0xa6dd), 0x00},
+       {CCI_REG8(0xa6de), 0x1c},
+       {CCI_REG8(0xa6df), 0x00},
+       {CCI_REG8(0xa6e0), 0x18},
+       {CCI_REG8(0xa6e1), 0x00},
+       {CCI_REG8(0xa6e2), 0x46},
+       {CCI_REG8(0xa6e3), 0x00},
+       {CCI_REG8(0xa6e4), 0x40},
+       {CCI_REG8(0xa6e5), 0x00},
+       {CCI_REG8(0xa6e6), 0x39},
+       {CCI_REG8(0xa6e7), 0x00},
+       {CCI_REG8(0xa6e8), 0x31},
+       {CCI_REG8(0xa6e9), 0x00},
+       {CCI_REG8(0xa6ea), 0x8c},
+       {CCI_REG8(0xa6eb), 0x00},
+       {CCI_REG8(0xa6ec), 0x7f},
+       {CCI_REG8(0xa6ed), 0x00},
+       {CCI_REG8(0xa6ee), 0x71},
+       {CCI_REG8(0xa6ef), 0x00},
+       {CCI_REG8(0xa6f0), 0x61},
+       {CCI_REG8(0xa6f1), 0x00},
+       {CCI_REG8(0xa6f2), 0x18},
+       {CCI_REG8(0xa6f3), 0x01},
+       {CCI_REG8(0xa6f4), 0xff},
+       {CCI_REG8(0xa6f5), 0x00},
+       {CCI_REG8(0xa6f6), 0xe2},
+       {CCI_REG8(0xa6f7), 0x00},
+       {CCI_REG8(0xa6f8), 0xc2},
+       {CCI_REG8(0xa6f9), 0x00},
+       {CCI_REG8(0xa702), 0x02},
+       {CCI_REG8(0xa703), 0x00},
+       {CCI_REG8(0xa704), 0x02},
+       {CCI_REG8(0xa705), 0x00},
+       {CCI_REG8(0xa706), 0x02},
+       {CCI_REG8(0xa707), 0x00},
+       {CCI_REG8(0xa708), 0x02},
+       {CCI_REG8(0xa709), 0x00},
+       {CCI_REG8(0xa72e), 0x40},
+       {CCI_REG8(0xa72f), 0x40},
+       {CCI_REG8(0xa730), 0x40},
+       {CCI_REG8(0xa731), 0x40},
+       {CCI_REG8(0xa732), 0x05},
+       {CCI_REG8(0xa733), 0x00},
+       {CCI_REG8(0xa734), 0x05},
+       {CCI_REG8(0xa735), 0x00},
+       {CCI_REG8(0xa736), 0x05},
+       {CCI_REG8(0xa737), 0x00},
+       {CCI_REG8(0xa738), 0x05},
+       {CCI_REG8(0xa739), 0x00},
+       {CCI_REG8(0xa73a), 0x09},
+       {CCI_REG8(0xa73b), 0x00},
+       {CCI_REG8(0xa73c), 0x09},
+       {CCI_REG8(0xa73d), 0x00},
+       {CCI_REG8(0xa73e), 0x09},
+       {CCI_REG8(0xa73f), 0x00},
+       {CCI_REG8(0xa740), 0x09},
+       {CCI_REG8(0xa741), 0x00},
+       {CCI_REG8(0xa742), 0x13},
+       {CCI_REG8(0xa743), 0x00},
+       {CCI_REG8(0xa744), 0x13},
+       {CCI_REG8(0xa745), 0x00},
+       {CCI_REG8(0xa746), 0x13},
+       {CCI_REG8(0xa747), 0x00},
+       {CCI_REG8(0xa748), 0x13},
+       {CCI_REG8(0xa749), 0x00},
+       {CCI_REG8(0xa74a), 0x25},
+       {CCI_REG8(0xa74b), 0x00},
+       {CCI_REG8(0xa74c), 0x25},
+       {CCI_REG8(0xa74d), 0x00},
+       {CCI_REG8(0xa74e), 0x25},
+       {CCI_REG8(0xa74f), 0x00},
+       {CCI_REG8(0xa750), 0x25},
+       {CCI_REG8(0xa751), 0x00},
+       {CCI_REG8(0xa75a), 0x02},
+       {CCI_REG8(0xa75b), 0x00},
+       {CCI_REG8(0xa75c), 0x02},
+       {CCI_REG8(0xa75d), 0x00},
+       {CCI_REG8(0xa75e), 0x02},
+       {CCI_REG8(0xa75f), 0x00},
+       {CCI_REG8(0xa760), 0x02},
+       {CCI_REG8(0xa761), 0x00},
+       {CCI_REG8(0xa782), 0x40},
+       {CCI_REG8(0xa783), 0x40},
+       {CCI_REG8(0xa784), 0x40},
+       {CCI_REG8(0xa785), 0x40},
+       {CCI_REG8(0xa786), 0x40},
+       {CCI_REG8(0xa787), 0x40},
+       {CCI_REG8(0xa788), 0x40},
+       {CCI_REG8(0xa789), 0x40},
+       {CCI_REG8(0xa78a), 0x03},
+       {CCI_REG8(0xa78b), 0x00},
+       {CCI_REG8(0xa78c), 0x03},
+       {CCI_REG8(0xa78d), 0x00},
+       {CCI_REG8(0xa78e), 0x03},
+       {CCI_REG8(0xa78f), 0x00},
+       {CCI_REG8(0xa790), 0x03},
+       {CCI_REG8(0xa791), 0x00},
+       {CCI_REG8(0xa792), 0x06},
+       {CCI_REG8(0xa793), 0x00},
+       {CCI_REG8(0xa794), 0x06},
+       {CCI_REG8(0xa795), 0x00},
+       {CCI_REG8(0xa796), 0x06},
+       {CCI_REG8(0xa797), 0x00},
+       {CCI_REG8(0xa798), 0x06},
+       {CCI_REG8(0xa799), 0x00},
+       {CCI_REG8(0xa79a), 0x0c},
+       {CCI_REG8(0xa79b), 0x00},
+       {CCI_REG8(0xa79c), 0x0c},
+       {CCI_REG8(0xa79d), 0x00},
+       {CCI_REG8(0xa79e), 0x0c},
+       {CCI_REG8(0xa79f), 0x00},
+       {CCI_REG8(0xa7a0), 0x0c},
+       {CCI_REG8(0xa7a1), 0x00},
+       {CCI_REG8(0xa7a2), 0x19},
+       {CCI_REG8(0xa7a3), 0x00},
+       {CCI_REG8(0xa7a4), 0x19},
+       {CCI_REG8(0xa7a5), 0x00},
+       {CCI_REG8(0xa7a6), 0x19},
+       {CCI_REG8(0xa7a7), 0x00},
+       {CCI_REG8(0xa7a8), 0x19},
+       {CCI_REG8(0xa7a9), 0x00},
+       {CCI_REG8(0xa7b2), 0x02},
+       {CCI_REG8(0xa7b3), 0x00},
+       {CCI_REG8(0xa7b4), 0x02},
+       {CCI_REG8(0xa7b5), 0x00},
+       {CCI_REG8(0xa7b6), 0x02},
+       {CCI_REG8(0xa7b7), 0x00},
+       {CCI_REG8(0xa7b8), 0x02},
+       {CCI_REG8(0xa7b9), 0x00},
+       {CCI_REG8(0xa7e2), 0x01},
+       {CCI_REG8(0xa7e3), 0x00},
+       {CCI_REG8(0xa7e4), 0x01},
+       {CCI_REG8(0xa7e5), 0x00},
+       {CCI_REG8(0xa7e6), 0x01},
+       {CCI_REG8(0xa7e7), 0x00},
+       {CCI_REG8(0xa7e8), 0x01},
+       {CCI_REG8(0xa7e9), 0x00},
+       {CCI_REG8(0xa7ea), 0x03},
+       {CCI_REG8(0xa7eb), 0x00},
+       {CCI_REG8(0xa7ec), 0x03},
+       {CCI_REG8(0xa7ed), 0x00},
+       {CCI_REG8(0xa7ee), 0x03},
+       {CCI_REG8(0xa7ef), 0x00},
+       {CCI_REG8(0xa7f0), 0x03},
+       {CCI_REG8(0xa7f1), 0x00},
+       {CCI_REG8(0xa7f2), 0x0b},
+       {CCI_REG8(0xa7f3), 0x00},
+       {CCI_REG8(0xa7f4), 0x0b},
+       {CCI_REG8(0xa7f5), 0x00},
+       {CCI_REG8(0xa7f6), 0x0b},
+       {CCI_REG8(0xa7f7), 0x00},
+       {CCI_REG8(0xa7f8), 0x0b},
+       {CCI_REG8(0xa7f9), 0x00},
+       {CCI_REG8(0xa7fa), 0x2e},
+       {CCI_REG8(0xa7fb), 0x00},
+       {CCI_REG8(0xa7fc), 0x2e},
+       {CCI_REG8(0xa7fd), 0x00},
+       {CCI_REG8(0xa7fe), 0x2e},
+       {CCI_REG8(0xa7ff), 0x00},
+       {CCI_REG8(0xa800), 0x2e},
+       {CCI_REG8(0xa801), 0x00},
+       {CCI_REG8(0xa80a), 0x0a},
+       {CCI_REG8(0xa80b), 0x00},
+       {CCI_REG8(0xa80c), 0x0a},
+       {CCI_REG8(0xa80d), 0x00},
+       {CCI_REG8(0xa80e), 0x0a},
+       {CCI_REG8(0xa80f), 0x00},
+       {CCI_REG8(0xa810), 0x0a},
+       {CCI_REG8(0xa811), 0x00},
+       {CCI_REG8(0xa832), 0x40},
+       {CCI_REG8(0xa833), 0x40},
+       {CCI_REG8(0xa834), 0x40},
+       {CCI_REG8(0xa835), 0x40},
+       {CCI_REG8(0xa836), 0x40},
+       {CCI_REG8(0xa837), 0x40},
+       {CCI_REG8(0xa838), 0x40},
+       {CCI_REG8(0xa839), 0x40},
+       {CCI_REG8(0xa83a), 0x05},
+       {CCI_REG8(0xa83b), 0x00},
+       {CCI_REG8(0xa83c), 0x05},
+       {CCI_REG8(0xa83d), 0x00},
+       {CCI_REG8(0xa83e), 0x05},
+       {CCI_REG8(0xa83f), 0x00},
+       {CCI_REG8(0xa840), 0x05},
+       {CCI_REG8(0xa841), 0x00},
+       {CCI_REG8(0xa842), 0x0a},
+       {CCI_REG8(0xa843), 0x00},
+       {CCI_REG8(0xa844), 0x0a},
+       {CCI_REG8(0xa845), 0x00},
+       {CCI_REG8(0xa846), 0x0a},
+       {CCI_REG8(0xa847), 0x00},
+       {CCI_REG8(0xa848), 0x0a},
+       {CCI_REG8(0xa849), 0x00},
+       {CCI_REG8(0xa84a), 0x13},
+       {CCI_REG8(0xa84b), 0x00},
+       {CCI_REG8(0xa84c), 0x13},
+       {CCI_REG8(0xa84d), 0x00},
+       {CCI_REG8(0xa84e), 0x13},
+       {CCI_REG8(0xa84f), 0x00},
+       {CCI_REG8(0xa850), 0x13},
+       {CCI_REG8(0xa851), 0x00},
+       {CCI_REG8(0xa852), 0x26},
+       {CCI_REG8(0xa853), 0x00},
+       {CCI_REG8(0xa854), 0x26},
+       {CCI_REG8(0xa855), 0x00},
+       {CCI_REG8(0xa856), 0x26},
+       {CCI_REG8(0xa857), 0x00},
+       {CCI_REG8(0xa858), 0x26},
+       {CCI_REG8(0xa859), 0x00},
+       {CCI_REG8(0xa862), 0x02},
+       {CCI_REG8(0xa863), 0x00},
+       {CCI_REG8(0xa864), 0x02},
+       {CCI_REG8(0xa865), 0x00},
+       {CCI_REG8(0xa866), 0x02},
+       {CCI_REG8(0xa867), 0x00},
+       {CCI_REG8(0xa868), 0x02},
+       {CCI_REG8(0xa869), 0x00},
+       {CCI_REG8(0xa455), 0x00},
+       {CCI_REG8(0xa456), 0x01},
+       {CCI_REG8(0xa470), 0xaf},
+       {CCI_REG8(0xa471), 0x9b},
+       {CCI_REG8(0xa472), 0x87},
+       {CCI_REG8(0xa473), 0x6e},
+       {CCI_REG8(0xa474), 0xaf},
+       {CCI_REG8(0xa475), 0x9b},
+       {CCI_REG8(0xa476), 0x87},
+       {CCI_REG8(0xa477), 0x6e},
+       {CCI_REG8(0xa478), 0xaf},
+       {CCI_REG8(0xa479), 0x9b},
+       {CCI_REG8(0xa47a), 0x87},
+       {CCI_REG8(0xa47b), 0x6e},
+       {CCI_REG8(0xa4b4), 0x70},
+       {CCI_REG8(0xa4b5), 0x70},
+       {CCI_REG8(0xa4b6), 0x70},
+       {CCI_REG8(0xa4b7), 0x70},
+       {CCI_REG8(0xa4b9), 0x4a},
+       {CCI_REG8(0xa4ba), 0x44},
+       {CCI_REG8(0xa4bb), 0x3c},
+       {CCI_REG8(0xa4bc), 0x19},
+       {CCI_REG8(0xa4bd), 0x19},
+       {CCI_REG8(0xa4be), 0x19},
+       {CCI_REG8(0xa4bf), 0x19},
+       {CCI_REG8(0xa4c0), 0x07},
+       {CCI_REG8(0xa4c1), 0x07},
+       {CCI_REG8(0xa4c2), 0x07},
+       {CCI_REG8(0xa4c3), 0x07},
+       {CCI_REG8(0xa4c4), 0x0b},
+       {CCI_REG8(0xa4c5), 0x0b},
+       {CCI_REG8(0xa4c6), 0x0b},
+       {CCI_REG8(0xa4c7), 0x0b},
+       {CCI_REG8(0xa4c8), 0x1c},
+       {CCI_REG8(0xa4c9), 0x1c},
+       {CCI_REG8(0xa4ca), 0x1c},
+       {CCI_REG8(0xa4cb), 0x1c},
+       {CCI_REG8(0xb220), 0x00},
+       {CCI_REG8(0xb221), 0x01},
+       {CCI_REG8(0xb222), 0x00},
+       {CCI_REG8(0xb223), 0x01},
+       {CCI_REG8(0xb224), 0x00},
+       {CCI_REG8(0xb225), 0x01},
+       {CCI_REG8(0xb226), 0x00},
+       {CCI_REG8(0xb227), 0x01},
+       {CCI_REG8(0xb228), 0x00},
+       {CCI_REG8(0xb229), 0x01},
+       {CCI_REG8(0xb22a), 0x00},
+       {CCI_REG8(0xb22b), 0x01},
+       {CCI_REG8(0xb22c), 0x00},
+       {CCI_REG8(0xb22d), 0x01},
+       {CCI_REG8(0xb22e), 0x00},
+       {CCI_REG8(0xb22f), 0x01},
+       {CCI_REG8(0xb230), 0x00},
+       {CCI_REG8(0xb231), 0x01},
+       {CCI_REG8(0xb232), 0x00},
+       {CCI_REG8(0xb233), 0x01},
+       {CCI_REG8(0xb234), 0x00},
+       {CCI_REG8(0xb235), 0x01},
+       {CCI_REG8(0xb236), 0x00},
+       {CCI_REG8(0xb237), 0x01},
+       {CCI_REG8(0xb238), 0x00},
+       {CCI_REG8(0xb239), 0x01},
+       {CCI_REG8(0xb23a), 0x00},
+       {CCI_REG8(0xb23b), 0x01},
+       {CCI_REG8(0xb23c), 0x00},
+       {CCI_REG8(0xb23d), 0x01},
+       {CCI_REG8(0xb23e), 0x00},
+       {CCI_REG8(0xb23f), 0x01},
+       {CCI_REG8(0xb240), 0x80},
+       {CCI_REG8(0xb241), 0x00},
+       {CCI_REG8(0xb242), 0x80},
+       {CCI_REG8(0xb243), 0x00},
+       {CCI_REG8(0xb244), 0x80},
+       {CCI_REG8(0xb245), 0x00},
+       {CCI_REG8(0xb246), 0x80},
+       {CCI_REG8(0xb247), 0x00},
+       {CCI_REG8(0xb248), 0x80},
+       {CCI_REG8(0xb249), 0x00},
+       {CCI_REG8(0xb24a), 0x80},
+       {CCI_REG8(0xb24b), 0x00},
+       {CCI_REG8(0xb24c), 0x80},
+       {CCI_REG8(0xb24d), 0x00},
+       {CCI_REG8(0xb24e), 0x80},
+       {CCI_REG8(0xb24f), 0x00},
+       {CCI_REG8(0xb250), 0x80},
+       {CCI_REG8(0xb251), 0x00},
+       {CCI_REG8(0xb252), 0x80},
+       {CCI_REG8(0xb253), 0x00},
+       {CCI_REG8(0xb254), 0x80},
+       {CCI_REG8(0xb255), 0x00},
+       {CCI_REG8(0xb256), 0x80},
+       {CCI_REG8(0xb257), 0x00},
+       {CCI_REG8(0xb258), 0x80},
+       {CCI_REG8(0xb259), 0x00},
+       {CCI_REG8(0xb25a), 0x80},
+       {CCI_REG8(0xb25b), 0x00},
+       {CCI_REG8(0xb25c), 0x80},
+       {CCI_REG8(0xb25d), 0x00},
+       {CCI_REG8(0xb25e), 0x80},
+       {CCI_REG8(0xb25f), 0x00},
+       {CCI_REG8(0xb260), 0x00},
+       {CCI_REG8(0xb261), 0x01},
+       {CCI_REG8(0xb262), 0x00},
+       {CCI_REG8(0xb263), 0x01},
+       {CCI_REG8(0xb264), 0x00},
+       {CCI_REG8(0xb265), 0x01},
+       {CCI_REG8(0xb266), 0x00},
+       {CCI_REG8(0xb267), 0x01},
+       {CCI_REG8(0xb268), 0x00},
+       {CCI_REG8(0xb269), 0x01},
+       {CCI_REG8(0xb26a), 0x00},
+       {CCI_REG8(0xb26b), 0x01},
+       {CCI_REG8(0xb26c), 0x00},
+       {CCI_REG8(0xb26d), 0x01},
+       {CCI_REG8(0xb26e), 0x00},
+       {CCI_REG8(0xb26f), 0x01},
+       {CCI_REG8(0xb270), 0x00},
+       {CCI_REG8(0xb271), 0x01},
+       {CCI_REG8(0xb272), 0x00},
+       {CCI_REG8(0xb273), 0x01},
+       {CCI_REG8(0xb274), 0x00},
+       {CCI_REG8(0xb275), 0x01},
+       {CCI_REG8(0xb276), 0x00},
+       {CCI_REG8(0xb277), 0x01},
+       {CCI_REG8(0xb278), 0x00},
+       {CCI_REG8(0xb279), 0x01},
+       {CCI_REG8(0xb27a), 0x00},
+       {CCI_REG8(0xb27b), 0x01},
+       {CCI_REG8(0xb27c), 0x00},
+       {CCI_REG8(0xb27d), 0x01},
+       {CCI_REG8(0xb27e), 0x00},
+       {CCI_REG8(0xb27f), 0x01},
+       {CCI_REG8(0xb280), 0x80},
+       {CCI_REG8(0xb281), 0x00},
+       {CCI_REG8(0xb282), 0x80},
+       {CCI_REG8(0xb283), 0x00},
+       {CCI_REG8(0xb284), 0x80},
+       {CCI_REG8(0xb285), 0x00},
+       {CCI_REG8(0xb286), 0x80},
+       {CCI_REG8(0xb287), 0x00},
+       {CCI_REG8(0xb288), 0x80},
+       {CCI_REG8(0xb289), 0x00},
+       {CCI_REG8(0xb28a), 0x80},
+       {CCI_REG8(0xb28b), 0x00},
+       {CCI_REG8(0xb28c), 0x80},
+       {CCI_REG8(0xb28d), 0x00},
+       {CCI_REG8(0xb28e), 0x80},
+       {CCI_REG8(0xb28f), 0x00},
+       {CCI_REG8(0xb290), 0x80},
+       {CCI_REG8(0xb291), 0x00},
+       {CCI_REG8(0xb292), 0x80},
+       {CCI_REG8(0xb293), 0x00},
+       {CCI_REG8(0xb294), 0x80},
+       {CCI_REG8(0xb295), 0x00},
+       {CCI_REG8(0xb296), 0x80},
+       {CCI_REG8(0xb297), 0x00},
+       {CCI_REG8(0xb298), 0x80},
+       {CCI_REG8(0xb299), 0x00},
+       {CCI_REG8(0xb29a), 0x80},
+       {CCI_REG8(0xb29b), 0x00},
+       {CCI_REG8(0xb29c), 0x80},
+       {CCI_REG8(0xb29d), 0x00},
+       {CCI_REG8(0xb29e), 0x80},
+       {CCI_REG8(0xb29f), 0x00},
+       {CCI_REG8(0xb2a0), 0x00},
+       {CCI_REG8(0xb2a1), 0x01},
+       {CCI_REG8(0xb2a2), 0x00},
+       {CCI_REG8(0xb2a3), 0x01},
+       {CCI_REG8(0xb2a4), 0x00},
+       {CCI_REG8(0xb2a5), 0x01},
+       {CCI_REG8(0xb2a6), 0x00},
+       {CCI_REG8(0xb2a7), 0x01},
+       {CCI_REG8(0xb2a8), 0x00},
+       {CCI_REG8(0xb2a9), 0x01},
+       {CCI_REG8(0xb2aa), 0x00},
+       {CCI_REG8(0xb2ab), 0x01},
+       {CCI_REG8(0xb2ac), 0x00},
+       {CCI_REG8(0xb2ad), 0x01},
+       {CCI_REG8(0xb2ae), 0x00},
+       {CCI_REG8(0xb2af), 0x01},
+       {CCI_REG8(0xb2b0), 0x00},
+       {CCI_REG8(0xb2b1), 0x01},
+       {CCI_REG8(0xb2b2), 0x00},
+       {CCI_REG8(0xb2b3), 0x01},
+       {CCI_REG8(0xb2b4), 0x00},
+       {CCI_REG8(0xb2b5), 0x01},
+       {CCI_REG8(0xb2b6), 0x00},
+       {CCI_REG8(0xb2b7), 0x01},
+       {CCI_REG8(0xb2b8), 0x00},
+       {CCI_REG8(0xb2b9), 0x01},
+       {CCI_REG8(0xb2ba), 0x00},
+       {CCI_REG8(0xb2bb), 0x01},
+       {CCI_REG8(0xb2bc), 0x00},
+       {CCI_REG8(0xb2bd), 0x01},
+       {CCI_REG8(0xb2be), 0x00},
+       {CCI_REG8(0xb2bf), 0x01},
+       {CCI_REG8(0xb2c0), 0x80},
+       {CCI_REG8(0xb2c1), 0x00},
+       {CCI_REG8(0xb2c2), 0x80},
+       {CCI_REG8(0xb2c3), 0x00},
+       {CCI_REG8(0xb2c4), 0x80},
+       {CCI_REG8(0xb2c5), 0x00},
+       {CCI_REG8(0xb2c6), 0x80},
+       {CCI_REG8(0xb2c7), 0x00},
+       {CCI_REG8(0xb2c8), 0x80},
+       {CCI_REG8(0xb2c9), 0x00},
+       {CCI_REG8(0xb2ca), 0x80},
+       {CCI_REG8(0xb2cb), 0x00},
+       {CCI_REG8(0xb2cc), 0x80},
+       {CCI_REG8(0xb2cd), 0x00},
+       {CCI_REG8(0xb2ce), 0x80},
+       {CCI_REG8(0xb2cf), 0x00},
+       {CCI_REG8(0xb2d0), 0x80},
+       {CCI_REG8(0xb2d1), 0x00},
+       {CCI_REG8(0xb2d2), 0x80},
+       {CCI_REG8(0xb2d3), 0x00},
+       {CCI_REG8(0xb2d4), 0x80},
+       {CCI_REG8(0xb2d5), 0x00},
+       {CCI_REG8(0xb2d6), 0x80},
+       {CCI_REG8(0xb2d7), 0x00},
+       {CCI_REG8(0xb2d8), 0x80},
+       {CCI_REG8(0xb2d9), 0x00},
+       {CCI_REG8(0xb2da), 0x80},
+       {CCI_REG8(0xb2db), 0x00},
+       {CCI_REG8(0xb2dc), 0x80},
+       {CCI_REG8(0xb2dd), 0x00},
+       {CCI_REG8(0xb2de), 0x80},
+       {CCI_REG8(0xb2df), 0x00},
+       {CCI_REG8(0xb2e0), 0x00},
+       {CCI_REG8(0xb2e1), 0x01},
+       {CCI_REG8(0xb2e2), 0x00},
+       {CCI_REG8(0xb2e3), 0x01},
+       {CCI_REG8(0xb2e4), 0x00},
+       {CCI_REG8(0xb2e5), 0x01},
+       {CCI_REG8(0xb2e6), 0x00},
+       {CCI_REG8(0xb2e7), 0x01},
+       {CCI_REG8(0xb2e8), 0x00},
+       {CCI_REG8(0xb2e9), 0x01},
+       {CCI_REG8(0xb2ea), 0x00},
+       {CCI_REG8(0xb2eb), 0x01},
+       {CCI_REG8(0xb2ec), 0x00},
+       {CCI_REG8(0xb2ed), 0x01},
+       {CCI_REG8(0xb2ee), 0x00},
+       {CCI_REG8(0xb2ef), 0x01},
+       {CCI_REG8(0xb2f0), 0x00},
+       {CCI_REG8(0xb2f1), 0x01},
+       {CCI_REG8(0xb2f2), 0x00},
+       {CCI_REG8(0xb2f3), 0x01},
+       {CCI_REG8(0xb2f4), 0x00},
+       {CCI_REG8(0xb2f5), 0x01},
+       {CCI_REG8(0xb2f6), 0x00},
+       {CCI_REG8(0xb2f7), 0x01},
+       {CCI_REG8(0xb2f8), 0x00},
+       {CCI_REG8(0xb2f9), 0x01},
+       {CCI_REG8(0xb2fa), 0x00},
+       {CCI_REG8(0xb2fb), 0x01},
+       {CCI_REG8(0xb2fc), 0x00},
+       {CCI_REG8(0xb2fd), 0x01},
+       {CCI_REG8(0xb2fe), 0x00},
+       {CCI_REG8(0xb2ff), 0x01},
+       {CCI_REG8(0xb300), 0x80},
+       {CCI_REG8(0xb301), 0x00},
+       {CCI_REG8(0xb302), 0x80},
+       {CCI_REG8(0xb303), 0x00},
+       {CCI_REG8(0xb304), 0x80},
+       {CCI_REG8(0xb305), 0x00},
+       {CCI_REG8(0xb306), 0x80},
+       {CCI_REG8(0xb307), 0x00},
+       {CCI_REG8(0xb308), 0x80},
+       {CCI_REG8(0xb309), 0x00},
+       {CCI_REG8(0xb30a), 0x80},
+       {CCI_REG8(0xb30b), 0x00},
+       {CCI_REG8(0xb30c), 0x80},
+       {CCI_REG8(0xb30d), 0x00},
+       {CCI_REG8(0xb30e), 0x80},
+       {CCI_REG8(0xb30f), 0x00},
+       {CCI_REG8(0xb310), 0x80},
+       {CCI_REG8(0xb311), 0x00},
+       {CCI_REG8(0xb312), 0x80},
+       {CCI_REG8(0xb313), 0x00},
+       {CCI_REG8(0xb314), 0x80},
+       {CCI_REG8(0xb315), 0x00},
+       {CCI_REG8(0xb316), 0x80},
+       {CCI_REG8(0xb317), 0x00},
+       {CCI_REG8(0xb318), 0x80},
+       {CCI_REG8(0xb319), 0x00},
+       {CCI_REG8(0xb31a), 0x80},
+       {CCI_REG8(0xb31b), 0x00},
+       {CCI_REG8(0xb31c), 0x80},
+       {CCI_REG8(0xb31d), 0x00},
+       {CCI_REG8(0xb31e), 0x80},
+       {CCI_REG8(0xb31f), 0x00},
+       {CCI_REG8(0xb320), 0x40},
+       {CCI_REG8(0xb321), 0x40},
+       {CCI_REG8(0xb322), 0x40},
+       {CCI_REG8(0xb323), 0x40},
+       {CCI_REG8(0xb324), 0x40},
+       {CCI_REG8(0xb325), 0x40},
+       {CCI_REG8(0xb326), 0x40},
+       {CCI_REG8(0xb327), 0x40},
+       {CCI_REG8(0xb328), 0x40},
+       {CCI_REG8(0xb329), 0x40},
+       {CCI_REG8(0xb32a), 0x40},
+       {CCI_REG8(0xb32b), 0x40},
+       {CCI_REG8(0xb32c), 0x40},
+       {CCI_REG8(0xb32d), 0x40},
+       {CCI_REG8(0xb32e), 0x40},
+       {CCI_REG8(0xb32f), 0x40},
+       {CCI_REG8(0xb34c), 0x40},
+       {CCI_REG8(0xb34d), 0x40},
+       {CCI_REG8(0xb34e), 0x40},
+       {CCI_REG8(0xb34f), 0x40},
+       {CCI_REG8(0xb350), 0x40},
+       {CCI_REG8(0xb351), 0x40},
+       {CCI_REG8(0xb352), 0x40},
+       {CCI_REG8(0xb353), 0x40},
+       {CCI_REG8(0xb354), 0x40},
+       {CCI_REG8(0xb355), 0x40},
+       {CCI_REG8(0xb356), 0x40},
+       {CCI_REG8(0xb357), 0x40},
+       {CCI_REG8(0xb358), 0x40},
+       {CCI_REG8(0xb359), 0x40},
+       {CCI_REG8(0xb35a), 0x40},
+       {CCI_REG8(0xb35b), 0x40},
+       {CCI_REG8(0xb378), 0x40},
+       {CCI_REG8(0xb379), 0x40},
+       {CCI_REG8(0xb37a), 0x40},
+       {CCI_REG8(0xb37b), 0x40},
+       {CCI_REG8(0xb37c), 0x40},
+       {CCI_REG8(0xb37d), 0x40},
+       {CCI_REG8(0xb37e), 0x40},
+       {CCI_REG8(0xb37f), 0x40},
+       {CCI_REG8(0xb380), 0x40},
+       {CCI_REG8(0xb381), 0x40},
+       {CCI_REG8(0xb382), 0x40},
+       {CCI_REG8(0xb383), 0x40},
+       {CCI_REG8(0xb384), 0x40},
+       {CCI_REG8(0xb385), 0x40},
+       {CCI_REG8(0xb386), 0x40},
+       {CCI_REG8(0xb387), 0x40},
+       {CCI_REG8(0xb3a4), 0x40},
+       {CCI_REG8(0xb3a5), 0x40},
+       {CCI_REG8(0xb3a6), 0x40},
+       {CCI_REG8(0xb3a7), 0x40},
+       {CCI_REG8(0xb3a8), 0x40},
+       {CCI_REG8(0xb3a9), 0x40},
+       {CCI_REG8(0xb3aa), 0x40},
+       {CCI_REG8(0xb3ab), 0x40},
+       {CCI_REG8(0xb3ac), 0x40},
+       {CCI_REG8(0xb3ad), 0x40},
+       {CCI_REG8(0xb3ae), 0x40},
+       {CCI_REG8(0xb3af), 0x40},
+       {CCI_REG8(0xb3b0), 0x40},
+       {CCI_REG8(0xb3b1), 0x40},
+       {CCI_REG8(0xb3b2), 0x40},
+       {CCI_REG8(0xb3b3), 0x40},
+       {CCI_REG8(0xb3d0), 0x40},
+       {CCI_REG8(0xb3d1), 0x40},
+       {CCI_REG8(0xb3d2), 0x40},
+       {CCI_REG8(0xb3d3), 0x40},
+       {CCI_REG8(0xb3d4), 0x40},
+       {CCI_REG8(0xb3d5), 0x40},
+       {CCI_REG8(0xb3d6), 0x40},
+       {CCI_REG8(0xb3d7), 0x40},
+       {CCI_REG8(0xb3d8), 0x40},
+       {CCI_REG8(0xb3d9), 0x40},
+       {CCI_REG8(0xb3da), 0x40},
+       {CCI_REG8(0xb3db), 0x40},
+       {CCI_REG8(0xb3dc), 0x40},
+       {CCI_REG8(0xb3dd), 0x40},
+       {CCI_REG8(0xb3de), 0x40},
+       {CCI_REG8(0xb3df), 0x40},
+       {CCI_REG8(0xa4dc), 0x02},
+       {CCI_REG8(0xa4dd), 0x12},
+       {CCI_REG8(0xa690), 0x02},
+       {CCI_REG8(0xa694), 0x01},
+       {CCI_REG8(0xa695), 0x01},
+       {CCI_REG8(0xa696), 0x01},
+       {CCI_REG8(0xa8c8), 0x19},
+       {CCI_REG8(0xa8c9), 0x00},
+       {CCI_REG8(0xa8ca), 0x17},
+       {CCI_REG8(0xa8cb), 0x00},
+       {CCI_REG8(0xa8cc), 0x14},
+       {CCI_REG8(0xa8cd), 0x00},
+       {CCI_REG8(0xa8ce), 0x11},
+       {CCI_REG8(0xa8cf), 0x00},
+       {CCI_REG8(0xa8d0), 0x23},
+       {CCI_REG8(0xa8d1), 0x00},
+       {CCI_REG8(0xa8d2), 0x20},
+       {CCI_REG8(0xa8d3), 0x00},
+       {CCI_REG8(0xa8d4), 0x1c},
+       {CCI_REG8(0xa8d5), 0x00},
+       {CCI_REG8(0xa8d6), 0x18},
+       {CCI_REG8(0xa8d7), 0x00},
+       {CCI_REG8(0xa8d8), 0x31},
+       {CCI_REG8(0xa8d9), 0x00},
+       {CCI_REG8(0xa8da), 0x2d},
+       {CCI_REG8(0xa8db), 0x00},
+       {CCI_REG8(0xa8dc), 0x28},
+       {CCI_REG8(0xa8dd), 0x00},
+       {CCI_REG8(0xa8de), 0x22},
+       {CCI_REG8(0xa8df), 0x00},
+       {CCI_REG8(0xa8e0), 0x46},
+       {CCI_REG8(0xa8e1), 0x00},
+       {CCI_REG8(0xa8e2), 0x40},
+       {CCI_REG8(0xa8e3), 0x00},
+       {CCI_REG8(0xa8e4), 0x39},
+       {CCI_REG8(0xa8e5), 0x00},
+       {CCI_REG8(0xa8e6), 0x31},
+       {CCI_REG8(0xa8e7), 0x00},
+       {CCI_REG8(0xa8e8), 0x63},
+       {CCI_REG8(0xa8e9), 0x00},
+       {CCI_REG8(0xa8ea), 0x5a},
+       {CCI_REG8(0xa8eb), 0x00},
+       {CCI_REG8(0xa8ec), 0x50},
+       {CCI_REG8(0xa8ed), 0x00},
+       {CCI_REG8(0xa8ee), 0x45},
+       {CCI_REG8(0xa8ef), 0x00},
+       {CCI_REG8(0xa8f0), 0x8c},
+       {CCI_REG8(0xa8f1), 0x00},
+       {CCI_REG8(0xa8f2), 0x7f},
+       {CCI_REG8(0xa8f3), 0x00},
+       {CCI_REG8(0xa8f4), 0x71},
+       {CCI_REG8(0xa8f5), 0x00},
+       {CCI_REG8(0xa8f6), 0x61},
+       {CCI_REG8(0xa8f7), 0x00},
+       {CCI_REG8(0xa8f8), 0xc6},
+       {CCI_REG8(0xa8f9), 0x00},
+       {CCI_REG8(0xa8fa), 0xb4},
+       {CCI_REG8(0xa8fb), 0x00},
+       {CCI_REG8(0xa8fc), 0xa0},
+       {CCI_REG8(0xa8fd), 0x00},
+       {CCI_REG8(0xa8fe), 0x89},
+       {CCI_REG8(0xa8ff), 0x00},
+       {CCI_REG8(0xa900), 0x18},
+       {CCI_REG8(0xa901), 0x01},
+       {CCI_REG8(0xa902), 0xff},
+       {CCI_REG8(0xa903), 0x00},
+       {CCI_REG8(0xa904), 0xe2},
+       {CCI_REG8(0xa905), 0x00},
+       {CCI_REG8(0xa906), 0xc2},
+       {CCI_REG8(0xa907), 0x00},
+       {CCI_REG8(0xa928), 0x02},
+       {CCI_REG8(0xa929), 0x00},
+       {CCI_REG8(0xa92a), 0x02},
+       {CCI_REG8(0xa92b), 0x00},
+       {CCI_REG8(0xa92c), 0x02},
+       {CCI_REG8(0xa92d), 0x00},
+       {CCI_REG8(0xa92e), 0x02},
+       {CCI_REG8(0xa92f), 0x00},
+       {CCI_REG8(0xa930), 0x02},
+       {CCI_REG8(0xa931), 0x00},
+       {CCI_REG8(0xa932), 0x02},
+       {CCI_REG8(0xa933), 0x00},
+       {CCI_REG8(0xa934), 0x02},
+       {CCI_REG8(0xa935), 0x00},
+       {CCI_REG8(0xa936), 0x02},
+       {CCI_REG8(0xa937), 0x00},
+       {CCI_REG8(0xa938), 0x02},
+       {CCI_REG8(0xa939), 0x00},
+       {CCI_REG8(0xa93a), 0x02},
+       {CCI_REG8(0xa93b), 0x00},
+       {CCI_REG8(0xa93c), 0x02},
+       {CCI_REG8(0xa93d), 0x00},
+       {CCI_REG8(0xa93e), 0x02},
+       {CCI_REG8(0xa93f), 0x00},
+       {CCI_REG8(0xa940), 0x02},
+       {CCI_REG8(0xa941), 0x00},
+       {CCI_REG8(0xa942), 0x02},
+       {CCI_REG8(0xa943), 0x00},
+       {CCI_REG8(0xa944), 0x02},
+       {CCI_REG8(0xa945), 0x00},
+       {CCI_REG8(0xa946), 0x02},
+       {CCI_REG8(0xa947), 0x00},
+       {CCI_REG8(0xa948), 0x40},
+       {CCI_REG8(0xa949), 0x40},
+       {CCI_REG8(0xa94a), 0x40},
+       {CCI_REG8(0xa94b), 0x40},
+       {CCI_REG8(0xa94c), 0x40},
+       {CCI_REG8(0xa94d), 0x40},
+       {CCI_REG8(0xa94e), 0x40},
+       {CCI_REG8(0xa94f), 0x40},
+       {CCI_REG8(0xa950), 0x40},
+       {CCI_REG8(0xa951), 0x40},
+       {CCI_REG8(0xa952), 0x40},
+       {CCI_REG8(0xa953), 0x40},
+       {CCI_REG8(0xa954), 0x40},
+       {CCI_REG8(0xa955), 0x40},
+       {CCI_REG8(0xa956), 0x40},
+       {CCI_REG8(0xa957), 0x40},
+       {CCI_REG8(0xa960), 0x03},
+       {CCI_REG8(0xa961), 0x00},
+       {CCI_REG8(0xa962), 0x03},
+       {CCI_REG8(0xa963), 0x00},
+       {CCI_REG8(0xa964), 0x03},
+       {CCI_REG8(0xa965), 0x00},
+       {CCI_REG8(0xa966), 0x03},
+       {CCI_REG8(0xa967), 0x00},
+       {CCI_REG8(0xa968), 0x05},
+       {CCI_REG8(0xa969), 0x00},
+       {CCI_REG8(0xa96a), 0x05},
+       {CCI_REG8(0xa96b), 0x00},
+       {CCI_REG8(0xa96c), 0x05},
+       {CCI_REG8(0xa96d), 0x00},
+       {CCI_REG8(0xa96e), 0x05},
+       {CCI_REG8(0xa96f), 0x00},
+       {CCI_REG8(0xa970), 0x07},
+       {CCI_REG8(0xa971), 0x00},
+       {CCI_REG8(0xa972), 0x07},
+       {CCI_REG8(0xa973), 0x00},
+       {CCI_REG8(0xa974), 0x07},
+       {CCI_REG8(0xa975), 0x00},
+       {CCI_REG8(0xa976), 0x07},
+       {CCI_REG8(0xa977), 0x00},
+       {CCI_REG8(0xa978), 0x09},
+       {CCI_REG8(0xa979), 0x00},
+       {CCI_REG8(0xa97a), 0x09},
+       {CCI_REG8(0xa97b), 0x00},
+       {CCI_REG8(0xa97c), 0x09},
+       {CCI_REG8(0xa97d), 0x00},
+       {CCI_REG8(0xa97e), 0x09},
+       {CCI_REG8(0xa97f), 0x00},
+       {CCI_REG8(0xa980), 0x0d},
+       {CCI_REG8(0xa981), 0x00},
+       {CCI_REG8(0xa982), 0x0d},
+       {CCI_REG8(0xa983), 0x00},
+       {CCI_REG8(0xa984), 0x0d},
+       {CCI_REG8(0xa985), 0x00},
+       {CCI_REG8(0xa986), 0x0d},
+       {CCI_REG8(0xa987), 0x00},
+       {CCI_REG8(0xa988), 0x13},
+       {CCI_REG8(0xa989), 0x00},
+       {CCI_REG8(0xa98a), 0x13},
+       {CCI_REG8(0xa98b), 0x00},
+       {CCI_REG8(0xa98c), 0x13},
+       {CCI_REG8(0xa98d), 0x00},
+       {CCI_REG8(0xa98e), 0x13},
+       {CCI_REG8(0xa98f), 0x00},
+       {CCI_REG8(0xa990), 0x1a},
+       {CCI_REG8(0xa991), 0x00},
+       {CCI_REG8(0xa992), 0x1a},
+       {CCI_REG8(0xa993), 0x00},
+       {CCI_REG8(0xa994), 0x1a},
+       {CCI_REG8(0xa995), 0x00},
+       {CCI_REG8(0xa996), 0x1a},
+       {CCI_REG8(0xa997), 0x00},
+       {CCI_REG8(0xa998), 0x25},
+       {CCI_REG8(0xa999), 0x00},
+       {CCI_REG8(0xa99a), 0x25},
+       {CCI_REG8(0xa99b), 0x00},
+       {CCI_REG8(0xa99c), 0x25},
+       {CCI_REG8(0xa99d), 0x00},
+       {CCI_REG8(0xa99e), 0x25},
+       {CCI_REG8(0xa99f), 0x00},
+       {CCI_REG8(0xa9c0), 0x02},
+       {CCI_REG8(0xa9c1), 0x00},
+       {CCI_REG8(0xa9c2), 0x02},
+       {CCI_REG8(0xa9c3), 0x00},
+       {CCI_REG8(0xa9c4), 0x02},
+       {CCI_REG8(0xa9c5), 0x00},
+       {CCI_REG8(0xa9c6), 0x02},
+       {CCI_REG8(0xa9c7), 0x00},
+       {CCI_REG8(0xa9c8), 0x02},
+       {CCI_REG8(0xa9c9), 0x00},
+       {CCI_REG8(0xa9ca), 0x02},
+       {CCI_REG8(0xa9cb), 0x00},
+       {CCI_REG8(0xa9cc), 0x02},
+       {CCI_REG8(0xa9cd), 0x00},
+       {CCI_REG8(0xa9ce), 0x02},
+       {CCI_REG8(0xa9cf), 0x00},
+       {CCI_REG8(0xa9d0), 0x02},
+       {CCI_REG8(0xa9d1), 0x00},
+       {CCI_REG8(0xa9d2), 0x02},
+       {CCI_REG8(0xa9d3), 0x00},
+       {CCI_REG8(0xa9d4), 0x02},
+       {CCI_REG8(0xa9d5), 0x00},
+       {CCI_REG8(0xa9d6), 0x02},
+       {CCI_REG8(0xa9d7), 0x00},
+       {CCI_REG8(0xa9d8), 0x02},
+       {CCI_REG8(0xa9d9), 0x00},
+       {CCI_REG8(0xa9da), 0x02},
+       {CCI_REG8(0xa9db), 0x00},
+       {CCI_REG8(0xa9dc), 0x02},
+       {CCI_REG8(0xa9dd), 0x00},
+       {CCI_REG8(0xa9de), 0x02},
+       {CCI_REG8(0xa9df), 0x00},
+       {CCI_REG8(0xa9e0), 0x40},
+       {CCI_REG8(0xa9e1), 0x40},
+       {CCI_REG8(0xa9e2), 0x40},
+       {CCI_REG8(0xa9e3), 0x40},
+       {CCI_REG8(0xa9e4), 0x40},
+       {CCI_REG8(0xa9e5), 0x40},
+       {CCI_REG8(0xa9e6), 0x40},
+       {CCI_REG8(0xa9e7), 0x40},
+       {CCI_REG8(0xa9e8), 0x40},
+       {CCI_REG8(0xa9e9), 0x40},
+       {CCI_REG8(0xa9ea), 0x40},
+       {CCI_REG8(0xa9eb), 0x40},
+       {CCI_REG8(0xa9ec), 0x40},
+       {CCI_REG8(0xa9ed), 0x40},
+       {CCI_REG8(0xa9ee), 0x40},
+       {CCI_REG8(0xa9ef), 0x40},
+       {CCI_REG8(0xa9f8), 0x02},
+       {CCI_REG8(0xa9f9), 0x00},
+       {CCI_REG8(0xa9fa), 0x02},
+       {CCI_REG8(0xa9fb), 0x00},
+       {CCI_REG8(0xa9fc), 0x02},
+       {CCI_REG8(0xa9fd), 0x00},
+       {CCI_REG8(0xa9fe), 0x02},
+       {CCI_REG8(0xa9ff), 0x00},
+       {CCI_REG8(0xaa00), 0x03},
+       {CCI_REG8(0xaa01), 0x00},
+       {CCI_REG8(0xaa02), 0x03},
+       {CCI_REG8(0xaa03), 0x00},
+       {CCI_REG8(0xaa04), 0x03},
+       {CCI_REG8(0xaa05), 0x00},
+       {CCI_REG8(0xaa06), 0x03},
+       {CCI_REG8(0xaa07), 0x00},
+       {CCI_REG8(0xaa08), 0x04},
+       {CCI_REG8(0xaa09), 0x00},
+       {CCI_REG8(0xaa0a), 0x04},
+       {CCI_REG8(0xaa0b), 0x00},
+       {CCI_REG8(0xaa0c), 0x04},
+       {CCI_REG8(0xaa0d), 0x00},
+       {CCI_REG8(0xaa0e), 0x04},
+       {CCI_REG8(0xaa0f), 0x00},
+       {CCI_REG8(0xaa10), 0x06},
+       {CCI_REG8(0xaa11), 0x00},
+       {CCI_REG8(0xaa12), 0x06},
+       {CCI_REG8(0xaa13), 0x00},
+       {CCI_REG8(0xaa14), 0x06},
+       {CCI_REG8(0xaa15), 0x00},
+       {CCI_REG8(0xaa16), 0x06},
+       {CCI_REG8(0xaa17), 0x00},
+       {CCI_REG8(0xaa18), 0x09},
+       {CCI_REG8(0xaa19), 0x00},
+       {CCI_REG8(0xaa1a), 0x09},
+       {CCI_REG8(0xaa1b), 0x00},
+       {CCI_REG8(0xaa1c), 0x09},
+       {CCI_REG8(0xaa1d), 0x00},
+       {CCI_REG8(0xaa1e), 0x09},
+       {CCI_REG8(0xaa1f), 0x00},
+       {CCI_REG8(0xaa20), 0x0c},
+       {CCI_REG8(0xaa21), 0x00},
+       {CCI_REG8(0xaa22), 0x0c},
+       {CCI_REG8(0xaa23), 0x00},
+       {CCI_REG8(0xaa24), 0x0c},
+       {CCI_REG8(0xaa25), 0x00},
+       {CCI_REG8(0xaa26), 0x0c},
+       {CCI_REG8(0xaa27), 0x00},
+       {CCI_REG8(0xaa28), 0x12},
+       {CCI_REG8(0xaa29), 0x00},
+       {CCI_REG8(0xaa2a), 0x12},
+       {CCI_REG8(0xaa2b), 0x00},
+       {CCI_REG8(0xaa2c), 0x12},
+       {CCI_REG8(0xaa2d), 0x00},
+       {CCI_REG8(0xaa2e), 0x12},
+       {CCI_REG8(0xaa2f), 0x00},
+       {CCI_REG8(0xaa30), 0x19},
+       {CCI_REG8(0xaa31), 0x00},
+       {CCI_REG8(0xaa32), 0x19},
+       {CCI_REG8(0xaa33), 0x00},
+       {CCI_REG8(0xaa34), 0x19},
+       {CCI_REG8(0xaa35), 0x00},
+       {CCI_REG8(0xaa36), 0x19},
+       {CCI_REG8(0xaa37), 0x00},
+       {CCI_REG8(0xaa58), 0x02},
+       {CCI_REG8(0xaa59), 0x00},
+       {CCI_REG8(0xaa5a), 0x02},
+       {CCI_REG8(0xaa5b), 0x00},
+       {CCI_REG8(0xaa5c), 0x02},
+       {CCI_REG8(0xaa5d), 0x00},
+       {CCI_REG8(0xaa5e), 0x02},
+       {CCI_REG8(0xaa5f), 0x00},
+       {CCI_REG8(0xaa60), 0x02},
+       {CCI_REG8(0xaa61), 0x00},
+       {CCI_REG8(0xaa62), 0x02},
+       {CCI_REG8(0xaa63), 0x00},
+       {CCI_REG8(0xaa64), 0x02},
+       {CCI_REG8(0xaa65), 0x00},
+       {CCI_REG8(0xaa66), 0x02},
+       {CCI_REG8(0xaa67), 0x00},
+       {CCI_REG8(0xaa68), 0x02},
+       {CCI_REG8(0xaa69), 0x00},
+       {CCI_REG8(0xaa6a), 0x02},
+       {CCI_REG8(0xaa6b), 0x00},
+       {CCI_REG8(0xaa6c), 0x02},
+       {CCI_REG8(0xaa6d), 0x00},
+       {CCI_REG8(0xaa6e), 0x02},
+       {CCI_REG8(0xaa6f), 0x00},
+       {CCI_REG8(0xaa70), 0x02},
+       {CCI_REG8(0xaa71), 0x00},
+       {CCI_REG8(0xaa72), 0x02},
+       {CCI_REG8(0xaa73), 0x00},
+       {CCI_REG8(0xaa74), 0x02},
+       {CCI_REG8(0xaa75), 0x00},
+       {CCI_REG8(0xaa76), 0x02},
+       {CCI_REG8(0xaa77), 0x00},
+       {CCI_REG8(0xaa78), 0x40},
+       {CCI_REG8(0xaa79), 0x40},
+       {CCI_REG8(0xaa7a), 0x40},
+       {CCI_REG8(0xaa7b), 0x40},
+       {CCI_REG8(0xaa7c), 0x40},
+       {CCI_REG8(0xaa7d), 0x40},
+       {CCI_REG8(0xaa7e), 0x40},
+       {CCI_REG8(0xaa7f), 0x40},
+       {CCI_REG8(0xaa80), 0x40},
+       {CCI_REG8(0xaa81), 0x40},
+       {CCI_REG8(0xaa82), 0x40},
+       {CCI_REG8(0xaa83), 0x40},
+       {CCI_REG8(0xaa84), 0x40},
+       {CCI_REG8(0xaa85), 0x40},
+       {CCI_REG8(0xaa86), 0x40},
+       {CCI_REG8(0xaa87), 0x40},
+       {CCI_REG8(0xaa90), 0x00},
+       {CCI_REG8(0xaa91), 0x00},
+       {CCI_REG8(0xaa92), 0x00},
+       {CCI_REG8(0xaa93), 0x00},
+       {CCI_REG8(0xaa94), 0x00},
+       {CCI_REG8(0xaa95), 0x00},
+       {CCI_REG8(0xaa96), 0x00},
+       {CCI_REG8(0xaa97), 0x00},
+       {CCI_REG8(0xaa98), 0x01},
+       {CCI_REG8(0xaa99), 0x00},
+       {CCI_REG8(0xaa9a), 0x01},
+       {CCI_REG8(0xaa9b), 0x00},
+       {CCI_REG8(0xaa9c), 0x01},
+       {CCI_REG8(0xaa9d), 0x00},
+       {CCI_REG8(0xaa9e), 0x01},
+       {CCI_REG8(0xaa9f), 0x00},
+       {CCI_REG8(0xaaa0), 0x01},
+       {CCI_REG8(0xaaa1), 0x00},
+       {CCI_REG8(0xaaa2), 0x01},
+       {CCI_REG8(0xaaa3), 0x00},
+       {CCI_REG8(0xaaa4), 0x01},
+       {CCI_REG8(0xaaa5), 0x00},
+       {CCI_REG8(0xaaa6), 0x01},
+       {CCI_REG8(0xaaa7), 0x00},
+       {CCI_REG8(0xaaa8), 0x03},
+       {CCI_REG8(0xaaa9), 0x00},
+       {CCI_REG8(0xaaaa), 0x03},
+       {CCI_REG8(0xaaab), 0x00},
+       {CCI_REG8(0xaaac), 0x03},
+       {CCI_REG8(0xaaad), 0x00},
+       {CCI_REG8(0xaaae), 0x03},
+       {CCI_REG8(0xaaaf), 0x00},
+       {CCI_REG8(0xaab0), 0x06},
+       {CCI_REG8(0xaab1), 0x00},
+       {CCI_REG8(0xaab2), 0x06},
+       {CCI_REG8(0xaab3), 0x00},
+       {CCI_REG8(0xaab4), 0x06},
+       {CCI_REG8(0xaab5), 0x00},
+       {CCI_REG8(0xaab6), 0x06},
+       {CCI_REG8(0xaab7), 0x00},
+       {CCI_REG8(0xaab8), 0x0b},
+       {CCI_REG8(0xaab9), 0x00},
+       {CCI_REG8(0xaaba), 0x0b},
+       {CCI_REG8(0xaabb), 0x00},
+       {CCI_REG8(0xaabc), 0x0b},
+       {CCI_REG8(0xaabd), 0x00},
+       {CCI_REG8(0xaabe), 0x0b},
+       {CCI_REG8(0xaabf), 0x00},
+       {CCI_REG8(0xaac0), 0x17},
+       {CCI_REG8(0xaac1), 0x00},
+       {CCI_REG8(0xaac2), 0x17},
+       {CCI_REG8(0xaac3), 0x00},
+       {CCI_REG8(0xaac4), 0x17},
+       {CCI_REG8(0xaac5), 0x00},
+       {CCI_REG8(0xaac6), 0x17},
+       {CCI_REG8(0xaac7), 0x00},
+       {CCI_REG8(0xaac8), 0x2e},
+       {CCI_REG8(0xaac9), 0x00},
+       {CCI_REG8(0xaaca), 0x2e},
+       {CCI_REG8(0xaacb), 0x00},
+       {CCI_REG8(0xaacc), 0x2e},
+       {CCI_REG8(0xaacd), 0x00},
+       {CCI_REG8(0xaace), 0x2e},
+       {CCI_REG8(0xaacf), 0x00},
+       {CCI_REG8(0xaaf0), 0x0a},
+       {CCI_REG8(0xaaf1), 0x00},
+       {CCI_REG8(0xaaf2), 0x0a},
+       {CCI_REG8(0xaaf3), 0x00},
+       {CCI_REG8(0xaaf4), 0x0a},
+       {CCI_REG8(0xaaf5), 0x00},
+       {CCI_REG8(0xaaf6), 0x0a},
+       {CCI_REG8(0xaaf7), 0x00},
+       {CCI_REG8(0xaaf8), 0x0a},
+       {CCI_REG8(0xaaf9), 0x00},
+       {CCI_REG8(0xaafa), 0x0a},
+       {CCI_REG8(0xaafb), 0x00},
+       {CCI_REG8(0xaafc), 0x0a},
+       {CCI_REG8(0xaafd), 0x00},
+       {CCI_REG8(0xaafe), 0x0a},
+       {CCI_REG8(0xaaff), 0x00},
+       {CCI_REG8(0xab00), 0x0a},
+       {CCI_REG8(0xab01), 0x00},
+       {CCI_REG8(0xab02), 0x0a},
+       {CCI_REG8(0xab03), 0x00},
+       {CCI_REG8(0xab04), 0x0a},
+       {CCI_REG8(0xab05), 0x00},
+       {CCI_REG8(0xab06), 0x0a},
+       {CCI_REG8(0xab07), 0x00},
+       {CCI_REG8(0xab08), 0x0a},
+       {CCI_REG8(0xab09), 0x00},
+       {CCI_REG8(0xab0a), 0x0a},
+       {CCI_REG8(0xab0b), 0x00},
+       {CCI_REG8(0xab0c), 0x0a},
+       {CCI_REG8(0xab0d), 0x00},
+       {CCI_REG8(0xab0e), 0x0a},
+       {CCI_REG8(0xab0f), 0x00},
+       {CCI_REG8(0xab10), 0x40},
+       {CCI_REG8(0xab11), 0x40},
+       {CCI_REG8(0xab12), 0x40},
+       {CCI_REG8(0xab13), 0x40},
+       {CCI_REG8(0xab14), 0x40},
+       {CCI_REG8(0xab15), 0x40},
+       {CCI_REG8(0xab16), 0x40},
+       {CCI_REG8(0xab17), 0x40},
+       {CCI_REG8(0xab18), 0x40},
+       {CCI_REG8(0xab19), 0x40},
+       {CCI_REG8(0xab1a), 0x40},
+       {CCI_REG8(0xab1b), 0x40},
+       {CCI_REG8(0xab1c), 0x40},
+       {CCI_REG8(0xab1d), 0x40},
+       {CCI_REG8(0xab1e), 0x40},
+       {CCI_REG8(0xab1f), 0x40},
+       {CCI_REG8(0xab28), 0x03},
+       {CCI_REG8(0xab29), 0x00},
+       {CCI_REG8(0xab2a), 0x03},
+       {CCI_REG8(0xab2b), 0x00},
+       {CCI_REG8(0xab2c), 0x03},
+       {CCI_REG8(0xab2d), 0x00},
+       {CCI_REG8(0xab2e), 0x03},
+       {CCI_REG8(0xab2f), 0x00},
+       {CCI_REG8(0xab30), 0x05},
+       {CCI_REG8(0xab31), 0x00},
+       {CCI_REG8(0xab32), 0x05},
+       {CCI_REG8(0xab33), 0x00},
+       {CCI_REG8(0xab34), 0x05},
+       {CCI_REG8(0xab35), 0x00},
+       {CCI_REG8(0xab36), 0x05},
+       {CCI_REG8(0xab37), 0x00},
+       {CCI_REG8(0xab38), 0x07},
+       {CCI_REG8(0xab39), 0x00},
+       {CCI_REG8(0xab3a), 0x07},
+       {CCI_REG8(0xab3b), 0x00},
+       {CCI_REG8(0xab3c), 0x07},
+       {CCI_REG8(0xab3d), 0x00},
+       {CCI_REG8(0xab3e), 0x07},
+       {CCI_REG8(0xab3f), 0x00},
+       {CCI_REG8(0xab40), 0x0a},
+       {CCI_REG8(0xab41), 0x00},
+       {CCI_REG8(0xab42), 0x0a},
+       {CCI_REG8(0xab43), 0x00},
+       {CCI_REG8(0xab44), 0x0a},
+       {CCI_REG8(0xab45), 0x00},
+       {CCI_REG8(0xab46), 0x0a},
+       {CCI_REG8(0xab47), 0x00},
+       {CCI_REG8(0xab48), 0x0e},
+       {CCI_REG8(0xab49), 0x00},
+       {CCI_REG8(0xab4a), 0x0e},
+       {CCI_REG8(0xab4b), 0x00},
+       {CCI_REG8(0xab4c), 0x0e},
+       {CCI_REG8(0xab4d), 0x00},
+       {CCI_REG8(0xab4e), 0x0e},
+       {CCI_REG8(0xab4f), 0x00},
+       {CCI_REG8(0xab50), 0x13},
+       {CCI_REG8(0xab51), 0x00},
+       {CCI_REG8(0xab52), 0x13},
+       {CCI_REG8(0xab53), 0x00},
+       {CCI_REG8(0xab54), 0x13},
+       {CCI_REG8(0xab55), 0x00},
+       {CCI_REG8(0xab56), 0x13},
+       {CCI_REG8(0xab57), 0x00},
+       {CCI_REG8(0xab58), 0x1b},
+       {CCI_REG8(0xab59), 0x00},
+       {CCI_REG8(0xab5a), 0x1b},
+       {CCI_REG8(0xab5b), 0x00},
+       {CCI_REG8(0xab5c), 0x1b},
+       {CCI_REG8(0xab5d), 0x00},
+       {CCI_REG8(0xab5e), 0x1b},
+       {CCI_REG8(0xab5f), 0x00},
+       {CCI_REG8(0xab60), 0x26},
+       {CCI_REG8(0xab61), 0x00},
+       {CCI_REG8(0xab62), 0x26},
+       {CCI_REG8(0xab63), 0x00},
+       {CCI_REG8(0xab64), 0x26},
+       {CCI_REG8(0xab65), 0x00},
+       {CCI_REG8(0xab66), 0x26},
+       {CCI_REG8(0xab67), 0x00},
+       {CCI_REG8(0xab88), 0x02},
+       {CCI_REG8(0xab89), 0x00},
+       {CCI_REG8(0xab8a), 0x02},
+       {CCI_REG8(0xab8b), 0x00},
+       {CCI_REG8(0xab8c), 0x02},
+       {CCI_REG8(0xab8d), 0x00},
+       {CCI_REG8(0xab8e), 0x02},
+       {CCI_REG8(0xab8f), 0x00},
+       {CCI_REG8(0xab90), 0x02},
+       {CCI_REG8(0xab91), 0x00},
+       {CCI_REG8(0xab92), 0x02},
+       {CCI_REG8(0xab93), 0x00},
+       {CCI_REG8(0xab94), 0x02},
+       {CCI_REG8(0xab95), 0x00},
+       {CCI_REG8(0xab96), 0x02},
+       {CCI_REG8(0xab97), 0x00},
+       {CCI_REG8(0xab98), 0x02},
+       {CCI_REG8(0xab99), 0x00},
+       {CCI_REG8(0xab9a), 0x02},
+       {CCI_REG8(0xab9b), 0x00},
+       {CCI_REG8(0xab9c), 0x02},
+       {CCI_REG8(0xab9d), 0x00},
+       {CCI_REG8(0xab9e), 0x02},
+       {CCI_REG8(0xab9f), 0x00},
+       {CCI_REG8(0xaba0), 0x02},
+       {CCI_REG8(0xaba1), 0x00},
+       {CCI_REG8(0xaba2), 0x02},
+       {CCI_REG8(0xaba3), 0x00},
+       {CCI_REG8(0xaba4), 0x02},
+       {CCI_REG8(0xaba5), 0x00},
+       {CCI_REG8(0xaba6), 0x02},
+       {CCI_REG8(0xaba7), 0x00},
+       {CCI_REG8(0xaba8), 0x40},
+       {CCI_REG8(0xaba9), 0x40},
+       {CCI_REG8(0xabaa), 0x40},
+       {CCI_REG8(0xabab), 0x40},
+       {CCI_REG8(0xabac), 0x40},
+       {CCI_REG8(0xabad), 0x40},
+       {CCI_REG8(0xabae), 0x40},
+       {CCI_REG8(0xabaf), 0x40},
+       {CCI_REG8(0xabb0), 0x40},
+       {CCI_REG8(0xabb1), 0x40},
+       {CCI_REG8(0xabb2), 0x40},
+       {CCI_REG8(0xabb3), 0x40},
+       {CCI_REG8(0xabb4), 0x40},
+       {CCI_REG8(0xabb5), 0x40},
+       {CCI_REG8(0xabb6), 0x40},
+       {CCI_REG8(0xabb7), 0x40},
+       {CCI_REG8(0xa69c), 0x01},
+       {CCI_REG8(0xa69d), 0x01},
+       {CCI_REG8(0xa69e), 0x01},
+       {CCI_REG8(0xa69f), 0x01},
+       {CCI_REG8(0xa6a0), 0x01},
+       {CCI_REG8(0xa6a1), 0x01},
+       {CCI_REG8(0xb1b0), 0x00},
+       {CCI_REG8(0xb1b1), 0xf0},
+       {CCI_REG8(0xa198), 0x64},
+       {CCI_REG8(0xa199), 0x00},
+       {CCI_REG8(0xa19a), 0x00},
+       {CCI_REG8(0xa19c), 0x64},
+       {CCI_REG8(0xa19d), 0x00},
+       {CCI_REG8(0xa19e), 0x00},
+       {CCI_REG8(0xa1a0), 0xd4},
+       {CCI_REG8(0xa1a1), 0x00},
+       {CCI_REG8(0xa1a2), 0x00},
+       {CCI_REG8(0xa1a4), 0xaf},
+       {CCI_REG8(0xa1a5), 0x00},
+       {CCI_REG8(0xa1a6), 0x00},
+       {CCI_REG8(0xa1a8), 0xc2},
+       {CCI_REG8(0xa1a9), 0x01},
+       {CCI_REG8(0xa1aa), 0x00},
+       {CCI_REG8(0xa1ac), 0x34},
+       {CCI_REG8(0xa1ad), 0x01},
+       {CCI_REG8(0xa1ae), 0x00},
+       {CCI_REG8(0xa1b0), 0xba},
+       {CCI_REG8(0xa1b1), 0x03},
+       {CCI_REG8(0xa1b2), 0x00},
+       {CCI_REG8(0xa1b4), 0xa7},
+       {CCI_REG8(0xa1b5), 0x01},
+       {CCI_REG8(0xa1b6), 0x00},
+       {CCI_REG8(0xa1b8), 0xe8},
+       {CCI_REG8(0xa1b9), 0x07},
+       {CCI_REG8(0xa1ba), 0x00},
+       {CCI_REG8(0xa1bc), 0x70},
+       {CCI_REG8(0xa1bd), 0x02},
+       {CCI_REG8(0xa1be), 0x00},
+       {CCI_REG8(0xa1c0), 0xc5},
+       {CCI_REG8(0xa1c1), 0x10},
+       {CCI_REG8(0xa1c2), 0x00},
+       {CCI_REG8(0xa1c4), 0xfa},
+       {CCI_REG8(0xa1c5), 0x02},
+       {CCI_REG8(0xa1c6), 0x00},
+       {CCI_REG8(0xa1c8), 0x92},
+       {CCI_REG8(0xa1c9), 0x23},
+       {CCI_REG8(0xa1ca), 0x00},
+       {CCI_REG8(0xa1cc), 0xeb},
+       {CCI_REG8(0xa1cd), 0x03},
+       {CCI_REG8(0xa1ce), 0x00},
+       {CCI_REG8(0xa1d0), 0x71},
+       {CCI_REG8(0xa1d1), 0x4b},
+       {CCI_REG8(0xa1d2), 0x00},
+       {CCI_REG8(0xa1d4), 0x8f},
+       {CCI_REG8(0xa1d5), 0x04},
+       {CCI_REG8(0xa1d6), 0x00},
+       {CCI_REG8(0xa1d8), 0x03},
+       {CCI_REG8(0xa1d9), 0xa0},
+       {CCI_REG8(0xa1da), 0x00},
+       {CCI_REG8(0xa1dc), 0xb0},
+       {CCI_REG8(0xa1dd), 0x05},
+       {CCI_REG8(0xa1de), 0x00},
+       {CCI_REG8(0xa1e0), 0x63},
+       {CCI_REG8(0xa1e1), 0x53},
+       {CCI_REG8(0xa1e2), 0x01},
+       {CCI_REG8(0xa1e4), 0x74},
+       {CCI_REG8(0xa1e5), 0x06},
+       {CCI_REG8(0xa1e6), 0x00},
+       {CCI_REG8(0xa1e8), 0xd7},
+       {CCI_REG8(0xa1e9), 0xcf},
+       {CCI_REG8(0xa1ea), 0x02},
+       {CCI_REG8(0xa1ec), 0xce},
+       {CCI_REG8(0xa1ed), 0x07},
+       {CCI_REG8(0xa1ee), 0x00},
+       {CCI_REG8(0xa1f0), 0xc8},
+       {CCI_REG8(0xa1f1), 0xf6},
+       {CCI_REG8(0xa1f2), 0x05},
+       {CCI_REG8(0xa1f4), 0xb9},
+       {CCI_REG8(0xa1f5), 0x08},
+       {CCI_REG8(0xa1f6), 0x00},
+       {CCI_REG8(0xa1f8), 0x4d},
+       {CCI_REG8(0xa1f9), 0xa6},
+       {CCI_REG8(0xa1fa), 0x0c},
+       {CCI_REG8(0xa1fc), 0x56},
+       {CCI_REG8(0xa1fd), 0x0a},
+       {CCI_REG8(0xa1fe), 0x00},
+       {CCI_REG8(0xa200), 0x70},
+       {CCI_REG8(0xa201), 0xd4},
+       {CCI_REG8(0xa202), 0x1a},
+       {CCI_REG8(0xa204), 0x70},
+       {CCI_REG8(0xa205), 0x0b},
+       {CCI_REG8(0xa206), 0x00},
+       {CCI_REG8(0xa208), 0xf4},
+       {CCI_REG8(0xa209), 0xe7},
+       {CCI_REG8(0xa20a), 0x38},
+       {CCI_REG8(0xa20c), 0x5f},
+       {CCI_REG8(0xa20d), 0x0d},
+       {CCI_REG8(0xa20e), 0x00},
+       {CCI_REG8(0xa210), 0xa2},
+       {CCI_REG8(0xa211), 0xb2},
+       {CCI_REG8(0xa212), 0x78},
+       {CCI_REG8(0xa214), 0xaf},
+       {CCI_REG8(0xa215), 0x0e},
+       {CCI_REG8(0xa216), 0x00},
+       {CCI_REG8(0xa21c), 0xff},
+       {CCI_REG8(0xa21d), 0x0f},
+       {CCI_REG8(0xa21e), 0x00},
+       {CCI_REG8(0x179c), 0x02},
+       {CCI_REG8(0x179d), 0x03},
+       {CCI_REG8(0x179e), 0x01},
+       {CCI_REG8(0x179f), 0x03},
+       {CCI_REG8(0x17a0), 0x03},
+       {CCI_REG8(0x17a1), 0x01},
+       {CCI_REG8(0x17a2), 0x03},
+       {CCI_REG8(0x17a3), 0x03},
+       {CCI_REG8(0x17a4), 0x01},
+       {CCI_REG8(0x17a5), 0x03},
+       {CCI_REG8(0x17a6), 0x03},
+       {CCI_REG8(0x17a7), 0x01},
+       {CCI_REG8(0x17a8), 0x03},
+       {CCI_REG8(0x17a9), 0x03},
+       {CCI_REG8(0x17aa), 0x01},
+       {CCI_REG8(0x17ab), 0x03},
+       {CCI_REG8(0x17f2), 0x01},
+       {CCI_REG8(0x17f4), 0x01},
+       {CCI_REG8(0x17f6), 0xff},
+       {CCI_REG8(0x17f7), 0x0f},
+       {CCI_REG8(0x1792), 0x01},
+       {CCI_REG8(0x1794), 0x01},
+       {CCI_REG8(0x1796), 0x01},
+       {CCI_REG8(0x1798), 0x01},
+       {CCI_REG8(0x179a), 0x01},
+       {CCI_REG8(0x1808), 0x00},
+       {CCI_REG8(0x16dd), 0x01},
+       {CCI_REG8(0xa198), 0x80},
+       {CCI_REG8(0xa199), 0x01},
+       {CCI_REG8(0xa19a), 0x00},
+       {CCI_REG8(0xa1a0), 0x5a},
+       {CCI_REG8(0xa1a1), 0x03},
+       {CCI_REG8(0xa1a2), 0x00},
+       {CCI_REG8(0xa1a8), 0xb2},
+       {CCI_REG8(0xa1a9), 0x0c},
+       {CCI_REG8(0xa1aa), 0x00},
+       {CCI_REG8(0xa1b0), 0x6d},
+       {CCI_REG8(0xa1b1), 0x38},
+       {CCI_REG8(0xa1b2), 0x00},
+       {CCI_REG8(0xa1b8), 0x71},
+       {CCI_REG8(0xa1b9), 0x88},
+       {CCI_REG8(0xa1ba), 0x00},
+       {CCI_REG8(0xa1c0), 0x77},
+       {CCI_REG8(0xa1c1), 0xe7},
+       {CCI_REG8(0xa1c2), 0x00},
+       {CCI_REG8(0xa1c8), 0x7b},
+       {CCI_REG8(0xa1c9), 0xb5},
+       {CCI_REG8(0xa1ca), 0x03},
+       {CCI_REG8(0xa1d0), 0xa4},
+       {CCI_REG8(0xa1d1), 0x7d},
+       {CCI_REG8(0xa1d2), 0x07},
+       {CCI_REG8(0xa1d8), 0xcb},
+       {CCI_REG8(0xa1d9), 0x36},
+       {CCI_REG8(0xa1da), 0x0f},
+       {CCI_REG8(0xa1e0), 0x86},
+       {CCI_REG8(0xa1e1), 0x68},
+       {CCI_REG8(0xa1e2), 0x3e},
+       {CCI_REG8(0xa1e8), 0xff},
+       {CCI_REG8(0xa1e9), 0xff},
+       {CCI_REG8(0xa1ea), 0xff},
+       {CCI_REG8(0xa1f0), 0xff},
+       {CCI_REG8(0xa1f1), 0xff},
+       {CCI_REG8(0xa1f2), 0xff},
+       {CCI_REG8(0xa1f8), 0xff},
+       {CCI_REG8(0xa1f9), 0xff},
+       {CCI_REG8(0xa1fa), 0xff},
+       {CCI_REG8(0xa200), 0xff},
+       {CCI_REG8(0xa201), 0xff},
+       {CCI_REG8(0xa202), 0xff},
+       {CCI_REG8(0xa208), 0xff},
+       {CCI_REG8(0xa209), 0xff},
+       {CCI_REG8(0xa20a), 0xff},
+       {CCI_REG8(0xa210), 0xff},
+       {CCI_REG8(0xa211), 0xff},
+       {CCI_REG8(0xa212), 0xff},
+       {CCI_REG8(0xa218), 0xff},
+       {CCI_REG8(0xa219), 0xff},
+       {CCI_REG8(0xa21a), 0xff},
+       {CCI_REG8(0xa19c), 0x80},
+       {CCI_REG8(0xa19d), 0x01},
+       {CCI_REG8(0xa19e), 0x00},
+       {CCI_REG8(0xa1a4), 0x00},
+       {CCI_REG8(0xa1a5), 0x02},
+       {CCI_REG8(0xa1a6), 0x00},
+       {CCI_REG8(0xa1ac), 0x40},
+       {CCI_REG8(0xa1ad), 0x04},
+       {CCI_REG8(0xa1ae), 0x00},
+       {CCI_REG8(0xa1b4), 0x80},
+       {CCI_REG8(0xa1b5), 0x05},
+       {CCI_REG8(0xa1b6), 0x00},
+       {CCI_REG8(0xa1bc), 0xa0},
+       {CCI_REG8(0xa1bd), 0x07},
+       {CCI_REG8(0xa1be), 0x00},
+       {CCI_REG8(0xa1c4), 0xe0},
+       {CCI_REG8(0xa1c5), 0x07},
+       {CCI_REG8(0xa1c6), 0x00},
+       {CCI_REG8(0xa1cc), 0x00},
+       {CCI_REG8(0xa1cd), 0x0a},
+       {CCI_REG8(0xa1ce), 0x00},
+       {CCI_REG8(0xa1d4), 0xa0},
+       {CCI_REG8(0xa1d5), 0x0b},
+       {CCI_REG8(0xa1d6), 0x00},
+       {CCI_REG8(0xa1dc), 0xe0},
+       {CCI_REG8(0xa1dd), 0x0b},
+       {CCI_REG8(0xa1de), 0x00},
+       {CCI_REG8(0xa1e4), 0xc0},
+       {CCI_REG8(0xa1e5), 0x0c},
+       {CCI_REG8(0xa1e6), 0x00},
+       {CCI_REG8(0xa1ec), 0xff},
+       {CCI_REG8(0xa1ed), 0x0f},
+       {CCI_REG8(0xa1ee), 0x00},
+       {CCI_REG8(0xa1f4), 0xff},
+       {CCI_REG8(0xa1f5), 0x0f},
+       {CCI_REG8(0xa1f6), 0x00},
+       {CCI_REG8(0xa1fc), 0xff},
+       {CCI_REG8(0xa1fd), 0x0f},
+       {CCI_REG8(0xa1fe), 0x00},
+       {CCI_REG8(0xa204), 0xff},
+       {CCI_REG8(0xa205), 0x0f},
+       {CCI_REG8(0xa206), 0x00},
+       {CCI_REG8(0xa20c), 0xff},
+       {CCI_REG8(0xa20d), 0x0f},
+       {CCI_REG8(0xa20e), 0x00},
+       {CCI_REG8(0xa214), 0xff},
+       {CCI_REG8(0xa215), 0x0f},
+       {CCI_REG8(0xa216), 0x00},
+       {CCI_REG8(0xa21c), 0xff},
+       {CCI_REG8(0xa21d), 0x0f},
+       {CCI_REG8(0xa21e), 0x00},
+       {CCI_REG8(0xffff), 0x00},
+       {CCI_REG8(0xac4d), 0x02},
+       {CCI_REG8(0xffff), 0x01},
+       {CCI_REG8(0x0070), 0x61},
+       {CCI_REG8(0x0071), 0x40},
+       {CCI_REG8(0x0072), 0xb4},
+       {CCI_REG8(0x0073), 0x40},
+       {CCI_REG8(0x0074), 0xf6},
+       {CCI_REG8(0x0075), 0x40},
+       {CCI_REG8(0x0076), 0x45},
+       {CCI_REG8(0x0077), 0x40},
+       {CCI_REG8(0x0078), 0x07},
+       {CCI_REG8(0x0079), 0x40},
+       {CCI_REG8(0x007a), 0x04},
+       {CCI_REG8(0x007b), 0x00},
+       {CCI_REG8(0x007c), 0x1c},
+       {CCI_REG8(0x007d), 0x40},
+       {CCI_REG8(0x007e), 0x32},
+       {CCI_REG8(0x007f), 0x40},
+       {CCI_REG8(0x0080), 0x05},
+       {CCI_REG8(0x0081), 0x40},
+       {CCI_REG8(0x0082), 0x4c},
+       {CCI_REG8(0x0083), 0x40},
+       {CCI_REG8(0x0084), 0x64},
+       {CCI_REG8(0x0085), 0x40},
+       {CCI_REG8(0x0086), 0x40},
+       {CCI_REG8(0x0087), 0x40},
+       {CCI_REG8(0x0088), 0x10},
+       {CCI_REG8(0x0089), 0x40},
+       {CCI_REG8(0x008a), 0x2d},
+       {CCI_REG8(0x008b), 0x40},
+       {CCI_REG8(0x008c), 0x39},
+       {CCI_REG8(0x008d), 0x40},
+       {CCI_REG8(0x008e), 0x47},
+       {CCI_REG8(0x008f), 0x40},
+       {CCI_REG8(0x0090), 0x30},
+       {CCI_REG8(0x0091), 0x40},
+       {CCI_REG8(0x0092), 0x45},
+       {CCI_REG8(0x0093), 0x40},
+       {CCI_REG8(0x0094), 0x7f},
+       {CCI_REG8(0x0095), 0x40},
+       {CCI_REG8(0x0096), 0x63},
+       {CCI_REG8(0x0097), 0x40},
+       {CCI_REG8(0x0098), 0x1b},
+       {CCI_REG8(0x0099), 0x40},
+       {CCI_REG8(0x009a), 0x4e},
+       {CCI_REG8(0x009b), 0x40},
+       {CCI_REG8(0x009c), 0x4f},
+       {CCI_REG8(0x009d), 0x40},
+       {CCI_REG8(0x009e), 0x45},
+       {CCI_REG8(0x009f), 0x40},
+       {CCI_REG8(0x00a0), 0x2c},
+       {CCI_REG8(0x00a1), 0x00},
+       {CCI_REG8(0x00a2), 0x0d},
+       {CCI_REG8(0x00a3), 0x00},
+       {CCI_REG8(0x00a4), 0x35},
+       {CCI_REG8(0x00a5), 0x40},
+       {CCI_REG8(0x00a6), 0x01},
+       {CCI_REG8(0x00a7), 0x00},
+       {CCI_REG8(0x00a8), 0x23},
+       {CCI_REG8(0x00a9), 0x00},
+       {CCI_REG8(0x00aa), 0x10},
+       {CCI_REG8(0x00ab), 0x40},
+       {CCI_REG8(0x00ac), 0x1a},
+       {CCI_REG8(0x00ad), 0x40},
+       {CCI_REG8(0x00ae), 0x15},
+       {CCI_REG8(0x00af), 0x40},
+       {CCI_REG8(0x00b0), 0x28},
+       {CCI_REG8(0x00b1), 0x00},
+       {CCI_REG8(0x00b2), 0x01},
+       {CCI_REG8(0x00b3), 0x40},
+       {CCI_REG8(0x00b4), 0x1b},
+       {CCI_REG8(0x00b5), 0x40},
+       {CCI_REG8(0x00b6), 0x0e},
+       {CCI_REG8(0x00b7), 0x00},
+       {CCI_REG8(0x00b8), 0x1d},
+       {CCI_REG8(0x00b9), 0x00},
+       {CCI_REG8(0x00ba), 0x2d},
+       {CCI_REG8(0x00bb), 0x00},
+       {CCI_REG8(0x00bc), 0x10},
+       {CCI_REG8(0x00bd), 0x40},
+       {CCI_REG8(0x00be), 0x3a},
+       {CCI_REG8(0x00bf), 0x40},
+       {CCI_REG8(0x00c0), 0x3e},
+       {CCI_REG8(0x00c1), 0x00},
+       {CCI_REG8(0x00c2), 0x4f},
+       {CCI_REG8(0x00c3), 0x00},
+       {CCI_REG8(0x00c4), 0x48},
+       {CCI_REG8(0x00c5), 0x00},
+       {CCI_REG8(0x00c6), 0x1b},
+       {CCI_REG8(0x00c7), 0x00},
+       {CCI_REG8(0x00c8), 0x1b},
+       {CCI_REG8(0x00c9), 0x40},
+       {CCI_REG8(0x00ca), 0x51},
+       {CCI_REG8(0x00cb), 0x40},
+       {CCI_REG8(0x00cc), 0x4a},
+       {CCI_REG8(0x00cd), 0x40},
+       {CCI_REG8(0x00ce), 0x27},
+       {CCI_REG8(0x00cf), 0x40},
+       {CCI_REG8(0x00d0), 0x7a},
+       {CCI_REG8(0x00d1), 0x40},
+       {CCI_REG8(0x00d2), 0x8c},
+       {CCI_REG8(0x00d3), 0x40},
+       {CCI_REG8(0x00d4), 0x91},
+       {CCI_REG8(0x00d5), 0x40},
+       {CCI_REG8(0x00d6), 0x7c},
+       {CCI_REG8(0x00d7), 0x40},
+       {CCI_REG8(0x00d8), 0xab},
+       {CCI_REG8(0x00d9), 0x40},
+       {CCI_REG8(0x00da), 0xc7},
+       {CCI_REG8(0x00db), 0x40},
+       {CCI_REG8(0x00dc), 0xce},
+       {CCI_REG8(0x00dd), 0x40},
+       {CCI_REG8(0x00de), 0xb9},
+       {CCI_REG8(0x00df), 0x40},
+       {CCI_REG8(0x00e0), 0xe0},
+       {CCI_REG8(0x00e1), 0x40},
+       {CCI_REG8(0x00e2), 0xfd},
+       {CCI_REG8(0x00e3), 0x40},
+       {CCI_REG8(0x00e4), 0xfe},
+       {CCI_REG8(0x00e5), 0x40},
+       {CCI_REG8(0x00e6), 0xea},
+       {CCI_REG8(0x00e7), 0x40},
+       {CCI_REG8(0x00e8), 0xbf},
+       {CCI_REG8(0x00e9), 0x40},
+       {CCI_REG8(0x00ea), 0xe1},
+       {CCI_REG8(0x00eb), 0x40},
+       {CCI_REG8(0x00ec), 0xea},
+       {CCI_REG8(0x00ed), 0x40},
+       {CCI_REG8(0x00ee), 0xce},
+       {CCI_REG8(0x00ef), 0x40},
+       {CCI_REG8(0x00f0), 0x8d},
+       {CCI_REG8(0x00f1), 0x40},
+       {CCI_REG8(0x00f2), 0xae},
+       {CCI_REG8(0x00f3), 0x40},
+       {CCI_REG8(0x00f4), 0xae},
+       {CCI_REG8(0x00f5), 0x40},
+       {CCI_REG8(0x00f6), 0xa7},
+       {CCI_REG8(0x00f7), 0x40},
+       {CCI_REG8(0x00f8), 0x58},
+       {CCI_REG8(0x00f9), 0x40},
+       {CCI_REG8(0x00fa), 0x81},
+       {CCI_REG8(0x00fb), 0x40},
+       {CCI_REG8(0x00fc), 0x8c},
+       {CCI_REG8(0x00fd), 0x40},
+       {CCI_REG8(0x00fe), 0x69},
+       {CCI_REG8(0x00ff), 0x40},
+       {CCI_REG8(0x0100), 0x25},
+       {CCI_REG8(0x0101), 0x00},
+       {CCI_REG8(0x0102), 0x12},
+       {CCI_REG8(0x0103), 0x00},
+       {CCI_REG8(0x0104), 0x0a},
+       {CCI_REG8(0x0105), 0x00},
+       {CCI_REG8(0x0106), 0x06},
+       {CCI_REG8(0x0107), 0x00},
+       {CCI_REG8(0x0108), 0x5c},
+       {CCI_REG8(0x0109), 0x40},
+       {CCI_REG8(0x010a), 0x80},
+       {CCI_REG8(0x010b), 0x40},
+       {CCI_REG8(0x010c), 0x86},
+       {CCI_REG8(0x010d), 0x40},
+       {CCI_REG8(0x010e), 0x5f},
+       {CCI_REG8(0x010f), 0x40},
+       {CCI_REG8(0x0110), 0x84},
+       {CCI_REG8(0x0111), 0x00},
+       {CCI_REG8(0x0112), 0x7c},
+       {CCI_REG8(0x0113), 0x00},
+       {CCI_REG8(0x0114), 0x73},
+       {CCI_REG8(0x0115), 0x00},
+       {CCI_REG8(0x0116), 0x80},
+       {CCI_REG8(0x0117), 0x00},
+       {CCI_REG8(0x0118), 0x23},
+       {CCI_REG8(0x0119), 0x00},
+       {CCI_REG8(0x011a), 0x0e},
+       {CCI_REG8(0x011b), 0x00},
+       {CCI_REG8(0x011c), 0x14},
+       {CCI_REG8(0x011d), 0x00},
+       {CCI_REG8(0x011e), 0x1d},
+       {CCI_REG8(0x011f), 0x00},
+       {CCI_REG8(0x0120), 0x32},
+       {CCI_REG8(0x0121), 0x40},
+       {CCI_REG8(0x0122), 0x5a},
+       {CCI_REG8(0x0123), 0x40},
+       {CCI_REG8(0x0124), 0x67},
+       {CCI_REG8(0x0125), 0x40},
+       {CCI_REG8(0x0126), 0x4f},
+       {CCI_REG8(0x0127), 0x40},
+       {CCI_REG8(0x0128), 0x9e},
+       {CCI_REG8(0x0129), 0x40},
+       {CCI_REG8(0x012a), 0xb3},
+       {CCI_REG8(0x012b), 0x40},
+       {CCI_REG8(0x012c), 0xb7},
+       {CCI_REG8(0x012d), 0x40},
+       {CCI_REG8(0x012e), 0xb4},
+       {CCI_REG8(0x012f), 0x40},
+       {CCI_REG8(0x0130), 0xd1},
+       {CCI_REG8(0x0131), 0x40},
+       {CCI_REG8(0x0132), 0xe7},
+       {CCI_REG8(0x0133), 0x40},
+       {CCI_REG8(0x0134), 0xef},
+       {CCI_REG8(0x0135), 0x40},
+       {CCI_REG8(0x0136), 0xe2},
+       {CCI_REG8(0x0137), 0x40},
+       {CCI_REG8(0x0138), 0xc2},
+       {CCI_REG8(0x0139), 0x40},
+       {CCI_REG8(0x013a), 0xe6},
+       {CCI_REG8(0x013b), 0x40},
+       {CCI_REG8(0x013c), 0xec},
+       {CCI_REG8(0x013d), 0x40},
+       {CCI_REG8(0x013e), 0xdb},
+       {CCI_REG8(0x013f), 0x40},
+       {CCI_REG8(0x0140), 0x84},
+       {CCI_REG8(0x0141), 0x40},
+       {CCI_REG8(0x0142), 0x9e},
+       {CCI_REG8(0x0143), 0x40},
+       {CCI_REG8(0x0144), 0xad},
+       {CCI_REG8(0x0145), 0x40},
+       {CCI_REG8(0x0146), 0x95},
+       {CCI_REG8(0x0147), 0x40},
+       {CCI_REG8(0x0148), 0x3c},
+       {CCI_REG8(0x0149), 0x40},
+       {CCI_REG8(0x014a), 0x5f},
+       {CCI_REG8(0x014b), 0x40},
+       {CCI_REG8(0x014c), 0x64},
+       {CCI_REG8(0x014d), 0x40},
+       {CCI_REG8(0x014e), 0x55},
+       {CCI_REG8(0x014f), 0x40},
+       {CCI_REG8(0x0150), 0x8e},
+       {CCI_REG8(0x0151), 0x00},
+       {CCI_REG8(0x0152), 0x75},
+       {CCI_REG8(0x0153), 0x00},
+       {CCI_REG8(0x0154), 0x6f},
+       {CCI_REG8(0x0155), 0x00},
+       {CCI_REG8(0x0156), 0x7b},
+       {CCI_REG8(0x0157), 0x00},
+       {CCI_REG8(0x0158), 0x3c},
+       {CCI_REG8(0x0159), 0x40},
+       {CCI_REG8(0x015a), 0x49},
+       {CCI_REG8(0x015b), 0x40},
+       {CCI_REG8(0x015c), 0x4c},
+       {CCI_REG8(0x015d), 0x40},
+       {CCI_REG8(0x015e), 0x5b},
+       {CCI_REG8(0x015f), 0x40},
+       {CCI_REG8(0x0160), 0xca},
+       {CCI_REG8(0x0161), 0x00},
+       {CCI_REG8(0x0162), 0xca},
+       {CCI_REG8(0x0163), 0x00},
+       {CCI_REG8(0x0164), 0xdc},
+       {CCI_REG8(0x0165), 0x00},
+       {CCI_REG8(0x0166), 0xb8},
+       {CCI_REG8(0x0167), 0x00},
+       {CCI_REG8(0x0168), 0x50},
+       {CCI_REG8(0x0169), 0x00},
+       {CCI_REG8(0x016a), 0x29},
+       {CCI_REG8(0x016b), 0x00},
+       {CCI_REG8(0x016c), 0x19},
+       {CCI_REG8(0x016d), 0x00},
+       {CCI_REG8(0x016e), 0x3d},
+       {CCI_REG8(0x016f), 0x00},
+       {CCI_REG8(0x0170), 0x2f},
+       {CCI_REG8(0x0171), 0x40},
+       {CCI_REG8(0x0172), 0x4e},
+       {CCI_REG8(0x0173), 0x40},
+       {CCI_REG8(0x0174), 0x51},
+       {CCI_REG8(0x0175), 0x40},
+       {CCI_REG8(0x0176), 0x3d},
+       {CCI_REG8(0x0177), 0x40},
+       {CCI_REG8(0x0178), 0x99},
+       {CCI_REG8(0x0179), 0x40},
+       {CCI_REG8(0x017a), 0xb0},
+       {CCI_REG8(0x017b), 0x40},
+       {CCI_REG8(0x017c), 0xb9},
+       {CCI_REG8(0x017d), 0x40},
+       {CCI_REG8(0x017e), 0xaf},
+       {CCI_REG8(0x017f), 0x40},
+       {CCI_REG8(0x0180), 0xec},
+       {CCI_REG8(0x0181), 0x40},
+       {CCI_REG8(0x0182), 0xfe},
+       {CCI_REG8(0x0183), 0x40},
+       {CCI_REG8(0x0184), 0x02},
+       {CCI_REG8(0x0185), 0x41},
+       {CCI_REG8(0x0186), 0xff},
+       {CCI_REG8(0x0187), 0x40},
+       {CCI_REG8(0x0188), 0xd8},
+       {CCI_REG8(0x0189), 0x40},
+       {CCI_REG8(0x018a), 0xf8},
+       {CCI_REG8(0x018b), 0x40},
+       {CCI_REG8(0x018c), 0x02},
+       {CCI_REG8(0x018d), 0x41},
+       {CCI_REG8(0x018e), 0xed},
+       {CCI_REG8(0x018f), 0x40},
+       {CCI_REG8(0x0190), 0x93},
+       {CCI_REG8(0x0191), 0x40},
+       {CCI_REG8(0x0192), 0xb1},
+       {CCI_REG8(0x0193), 0x40},
+       {CCI_REG8(0x0194), 0xbf},
+       {CCI_REG8(0x0195), 0x40},
+       {CCI_REG8(0x0196), 0xae},
+       {CCI_REG8(0x0197), 0x40},
+       {CCI_REG8(0x0198), 0x4d},
+       {CCI_REG8(0x0199), 0x40},
+       {CCI_REG8(0x019a), 0x6d},
+       {CCI_REG8(0x019b), 0x40},
+       {CCI_REG8(0x019c), 0x80},
+       {CCI_REG8(0x019d), 0x40},
+       {CCI_REG8(0x019e), 0x65},
+       {CCI_REG8(0x019f), 0x40},
+       {CCI_REG8(0x01a0), 0x98},
+       {CCI_REG8(0x01a1), 0x00},
+       {CCI_REG8(0x01a2), 0x7e},
+       {CCI_REG8(0x01a3), 0x00},
+       {CCI_REG8(0x01a4), 0x77},
+       {CCI_REG8(0x01a5), 0x00},
+       {CCI_REG8(0x01a6), 0x7d},
+       {CCI_REG8(0x01a7), 0x00},
+       {CCI_REG8(0x01a8), 0x46},
+       {CCI_REG8(0x01a9), 0x40},
+       {CCI_REG8(0x01aa), 0x5c},
+       {CCI_REG8(0x01ab), 0x40},
+       {CCI_REG8(0x01ac), 0x6e},
+       {CCI_REG8(0x01ad), 0x40},
+       {CCI_REG8(0x01ae), 0x6e},
+       {CCI_REG8(0x01af), 0x40},
+       {CCI_REG8(0x01b0), 0xd3},
+       {CCI_REG8(0x01b1), 0x00},
+       {CCI_REG8(0x01b2), 0xd3},
+       {CCI_REG8(0x01b3), 0x00},
+       {CCI_REG8(0x01b4), 0xec},
+       {CCI_REG8(0x01b5), 0x00},
+       {CCI_REG8(0x01b6), 0xbf},
+       {CCI_REG8(0x01b7), 0x00},
+       {CCI_REG8(0x01b8), 0x54},
+       {CCI_REG8(0x01b9), 0x00},
+       {CCI_REG8(0x01ba), 0x37},
+       {CCI_REG8(0x01bb), 0x00},
+       {CCI_REG8(0x01bc), 0x34},
+       {CCI_REG8(0x01bd), 0x00},
+       {CCI_REG8(0x01be), 0x50},
+       {CCI_REG8(0x01bf), 0x00},
+       {CCI_REG8(0x01c0), 0x2d},
+       {CCI_REG8(0x01c1), 0x40},
+       {CCI_REG8(0x01c2), 0x57},
+       {CCI_REG8(0x01c3), 0x40},
+       {CCI_REG8(0x01c4), 0x53},
+       {CCI_REG8(0x01c5), 0x40},
+       {CCI_REG8(0x01c6), 0x3c},
+       {CCI_REG8(0x01c7), 0x40},
+       {CCI_REG8(0x01c8), 0xb1},
+       {CCI_REG8(0x01c9), 0x40},
+       {CCI_REG8(0x01ca), 0xbd},
+       {CCI_REG8(0x01cb), 0x40},
+       {CCI_REG8(0x01cc), 0xc0},
+       {CCI_REG8(0x01cd), 0x40},
+       {CCI_REG8(0x01ce), 0xbf},
+       {CCI_REG8(0x01cf), 0x40},
+       {CCI_REG8(0x01d0), 0xfc},
+       {CCI_REG8(0x01d1), 0x40},
+       {CCI_REG8(0x01d2), 0x16},
+       {CCI_REG8(0x01d3), 0x41},
+       {CCI_REG8(0x01d4), 0x11},
+       {CCI_REG8(0x01d5), 0x41},
+       {CCI_REG8(0x01d6), 0x0a},
+       {CCI_REG8(0x01d7), 0x41},
+       {CCI_REG8(0x01d8), 0xf8},
+       {CCI_REG8(0x01d9), 0x40},
+       {CCI_REG8(0x01da), 0x1e},
+       {CCI_REG8(0x01db), 0x41},
+       {CCI_REG8(0x01dc), 0x20},
+       {CCI_REG8(0x01dd), 0x41},
+       {CCI_REG8(0x01de), 0x0f},
+       {CCI_REG8(0x01df), 0x41},
+       {CCI_REG8(0x01e0), 0xbe},
+       {CCI_REG8(0x01e1), 0x40},
+       {CCI_REG8(0x01e2), 0xd3},
+       {CCI_REG8(0x01e3), 0x40},
+       {CCI_REG8(0x01e4), 0xd9},
+       {CCI_REG8(0x01e5), 0x40},
+       {CCI_REG8(0x01e6), 0xcb},
+       {CCI_REG8(0x01e7), 0x40},
+       {CCI_REG8(0x01e8), 0x68},
+       {CCI_REG8(0x01e9), 0x40},
+       {CCI_REG8(0x01ea), 0x97},
+       {CCI_REG8(0x01eb), 0x40},
+       {CCI_REG8(0x01ec), 0x9b},
+       {CCI_REG8(0x01ed), 0x40},
+       {CCI_REG8(0x01ee), 0x85},
+       {CCI_REG8(0x01ef), 0x40},
+       {CCI_REG8(0x01f0), 0x75},
+       {CCI_REG8(0x01f1), 0x00},
+       {CCI_REG8(0x01f2), 0x63},
+       {CCI_REG8(0x01f3), 0x00},
+       {CCI_REG8(0x01f4), 0x55},
+       {CCI_REG8(0x01f5), 0x00},
+       {CCI_REG8(0x01f6), 0x58},
+       {CCI_REG8(0x01f7), 0x00},
+       {CCI_REG8(0x01f8), 0x60},
+       {CCI_REG8(0x01f9), 0x40},
+       {CCI_REG8(0x01fa), 0x91},
+       {CCI_REG8(0x01fb), 0x40},
+       {CCI_REG8(0x01fc), 0x94},
+       {CCI_REG8(0x01fd), 0x40},
+       {CCI_REG8(0x01fe), 0x80},
+       {CCI_REG8(0x01ff), 0x40},
+       {CCI_REG8(0x0200), 0x2c},
+       {CCI_REG8(0x0201), 0x00},
+       {CCI_REG8(0x0202), 0x75},
+       {CCI_REG8(0x0203), 0x00},
+       {CCI_REG8(0x0204), 0x5f},
+       {CCI_REG8(0x0205), 0x00},
+       {CCI_REG8(0x0206), 0x59},
+       {CCI_REG8(0x0207), 0x00},
+       {CCI_REG8(0x0208), 0x21},
+       {CCI_REG8(0x0209), 0x00},
+       {CCI_REG8(0x020a), 0x0e},
+       {CCI_REG8(0x020b), 0x40},
+       {CCI_REG8(0x020c), 0x12},
+       {CCI_REG8(0x020d), 0x40},
+       {CCI_REG8(0x020e), 0x03},
+       {CCI_REG8(0x020f), 0x00},
+       {CCI_REG8(0x0210), 0x56},
+       {CCI_REG8(0x0211), 0x40},
+       {CCI_REG8(0x0212), 0x76},
+       {CCI_REG8(0x0213), 0x40},
+       {CCI_REG8(0x0214), 0x7c},
+       {CCI_REG8(0x0215), 0x40},
+       {CCI_REG8(0x0216), 0x66},
+       {CCI_REG8(0x0217), 0x40},
+       {CCI_REG8(0x0218), 0xdc},
+       {CCI_REG8(0x0219), 0x40},
+       {CCI_REG8(0x021a), 0xeb},
+       {CCI_REG8(0x021b), 0x40},
+       {CCI_REG8(0x021c), 0xf2},
+       {CCI_REG8(0x021d), 0x40},
+       {CCI_REG8(0x021e), 0xed},
+       {CCI_REG8(0x021f), 0x40},
+       {CCI_REG8(0x0220), 0x39},
+       {CCI_REG8(0x0221), 0x41},
+       {CCI_REG8(0x0222), 0x41},
+       {CCI_REG8(0x0223), 0x41},
+       {CCI_REG8(0x0224), 0x46},
+       {CCI_REG8(0x0225), 0x41},
+       {CCI_REG8(0x0226), 0x45},
+       {CCI_REG8(0x0227), 0x41},
+       {CCI_REG8(0x0228), 0x3d},
+       {CCI_REG8(0x0229), 0x41},
+       {CCI_REG8(0x022a), 0x51},
+       {CCI_REG8(0x022b), 0x41},
+       {CCI_REG8(0x022c), 0x5d},
+       {CCI_REG8(0x022d), 0x41},
+       {CCI_REG8(0x022e), 0x51},
+       {CCI_REG8(0x022f), 0x41},
+       {CCI_REG8(0x0230), 0xdf},
+       {CCI_REG8(0x0231), 0x40},
+       {CCI_REG8(0x0232), 0xfb},
+       {CCI_REG8(0x0233), 0x40},
+       {CCI_REG8(0x0234), 0xff},
+       {CCI_REG8(0x0235), 0x40},
+       {CCI_REG8(0x0236), 0xeb},
+       {CCI_REG8(0x0237), 0x40},
+       {CCI_REG8(0x0238), 0xa0},
+       {CCI_REG8(0x0239), 0x40},
+       {CCI_REG8(0x023a), 0xc0},
+       {CCI_REG8(0x023b), 0x40},
+       {CCI_REG8(0x023c), 0xd9},
+       {CCI_REG8(0x023d), 0x40},
+       {CCI_REG8(0x023e), 0xbc},
+       {CCI_REG8(0x023f), 0x40},
+       {CCI_REG8(0x0240), 0x1e},
+       {CCI_REG8(0x0241), 0x00},
+       {CCI_REG8(0x0242), 0x07},
+       {CCI_REG8(0x0243), 0x00},
+       {CCI_REG8(0x0244), 0x04},
+       {CCI_REG8(0x0245), 0x40},
+       {CCI_REG8(0x0246), 0x10},
+       {CCI_REG8(0x0247), 0x00},
+       {CCI_REG8(0x0248), 0xa6},
+       {CCI_REG8(0x0249), 0x40},
+       {CCI_REG8(0x024a), 0xa5},
+       {CCI_REG8(0x024b), 0x40},
+       {CCI_REG8(0x024c), 0xd4},
+       {CCI_REG8(0x024d), 0x40},
+       {CCI_REG8(0x024e), 0xd1},
+       {CCI_REG8(0x024f), 0x40},
+       {CCI_REG8(0x0250), 0xe4},
+       {CCI_REG8(0x0251), 0x01},
+       {CCI_REG8(0x0252), 0x3b},
+       {CCI_REG8(0x0253), 0x01},
+       {CCI_REG8(0x0254), 0xa2},
+       {CCI_REG8(0x0255), 0x01},
+       {CCI_REG8(0x0256), 0x43},
+       {CCI_REG8(0x0257), 0x01},
+       {CCI_REG8(0x0258), 0x72},
+       {CCI_REG8(0x0259), 0x00},
+       {CCI_REG8(0x025a), 0x85},
+       {CCI_REG8(0x025b), 0x00},
+       {CCI_REG8(0x025c), 0x73},
+       {CCI_REG8(0x025d), 0x00},
+       {CCI_REG8(0x025e), 0xa9},
+       {CCI_REG8(0x025f), 0x00},
+       {CCI_REG8(0x0260), 0x16},
+       {CCI_REG8(0x0261), 0x00},
+       {CCI_REG8(0x0262), 0x31},
+       {CCI_REG8(0x0263), 0x40},
+       {CCI_REG8(0x0264), 0x1d},
+       {CCI_REG8(0x0265), 0x40},
+       {CCI_REG8(0x0266), 0x1c},
+       {CCI_REG8(0x0267), 0x40},
+       {CCI_REG8(0x0268), 0x87},
+       {CCI_REG8(0x0269), 0x40},
+       {CCI_REG8(0x026a), 0x80},
+       {CCI_REG8(0x026b), 0x40},
+       {CCI_REG8(0x026c), 0x88},
+       {CCI_REG8(0x026d), 0x40},
+       {CCI_REG8(0x026e), 0x8d},
+       {CCI_REG8(0x026f), 0x40},
+       {CCI_REG8(0x0270), 0xaa},
+       {CCI_REG8(0x0271), 0x40},
+       {CCI_REG8(0x0272), 0xde},
+       {CCI_REG8(0x0273), 0x40},
+       {CCI_REG8(0x0274), 0xd1},
+       {CCI_REG8(0x0275), 0x40},
+       {CCI_REG8(0x0276), 0xc3},
+       {CCI_REG8(0x0277), 0x40},
+       {CCI_REG8(0x0278), 0xad},
+       {CCI_REG8(0x0279), 0x40},
+       {CCI_REG8(0x027a), 0xdc},
+       {CCI_REG8(0x027b), 0x40},
+       {CCI_REG8(0x027c), 0xce},
+       {CCI_REG8(0x027d), 0x40},
+       {CCI_REG8(0x027e), 0xc4},
+       {CCI_REG8(0x027f), 0x40},
+       {CCI_REG8(0x0280), 0x87},
+       {CCI_REG8(0x0281), 0x40},
+       {CCI_REG8(0x0282), 0xae},
+       {CCI_REG8(0x0283), 0x40},
+       {CCI_REG8(0x0284), 0xbc},
+       {CCI_REG8(0x0285), 0x40},
+       {CCI_REG8(0x0286), 0xa9},
+       {CCI_REG8(0x0287), 0x40},
+       {CCI_REG8(0x0288), 0x33},
+       {CCI_REG8(0x0289), 0x40},
+       {CCI_REG8(0x028a), 0x69},
+       {CCI_REG8(0x028b), 0x40},
+       {CCI_REG8(0x028c), 0x4f},
+       {CCI_REG8(0x028d), 0x40},
+       {CCI_REG8(0x028e), 0x47},
+       {CCI_REG8(0x028f), 0x40},
+       {CCI_REG8(0x0290), 0xeb},
+       {CCI_REG8(0x0291), 0x00},
+       {CCI_REG8(0x0292), 0xda},
+       {CCI_REG8(0x0293), 0x00},
+       {CCI_REG8(0x0294), 0xc8},
+       {CCI_REG8(0x0295), 0x00},
+       {CCI_REG8(0x0296), 0xb9},
+       {CCI_REG8(0x0297), 0x00},
+       {CCI_REG8(0x0298), 0x1a},
+       {CCI_REG8(0x0299), 0x40},
+       {CCI_REG8(0x029a), 0x7e},
+       {CCI_REG8(0x029b), 0x40},
+       {CCI_REG8(0x029c), 0x43},
+       {CCI_REG8(0x029d), 0x40},
+       {CCI_REG8(0x029e), 0x2a},
+       {CCI_REG8(0x029f), 0x40},
+       {CCI_REG8(0x02f0), 0x11},
+       {CCI_REG8(0x02f1), 0x00},
+       {CCI_REG8(0x02f2), 0x06},
+       {CCI_REG8(0x02f3), 0x00},
+       {CCI_REG8(0x02f4), 0x0e},
+       {CCI_REG8(0x02f5), 0x00},
+       {CCI_REG8(0x02f6), 0x1c},
+       {CCI_REG8(0x02f7), 0x00},
+       {CCI_REG8(0x02f8), 0x0a},
+       {CCI_REG8(0x02f9), 0x00},
+       {CCI_REG8(0x02fa), 0x1b},
+       {CCI_REG8(0x02fb), 0x00},
+       {CCI_REG8(0x02fc), 0x20},
+       {CCI_REG8(0x02fd), 0x00},
+       {CCI_REG8(0x02fe), 0x15},
+       {CCI_REG8(0x02ff), 0x00},
+       {CCI_REG8(0x0300), 0x0d},
+       {CCI_REG8(0x0301), 0x00},
+       {CCI_REG8(0x0302), 0x1e},
+       {CCI_REG8(0x0303), 0x00},
+       {CCI_REG8(0x0304), 0x27},
+       {CCI_REG8(0x0305), 0x00},
+       {CCI_REG8(0x0306), 0x16},
+       {CCI_REG8(0x0307), 0x00},
+       {CCI_REG8(0x0308), 0x10},
+       {CCI_REG8(0x0309), 0x00},
+       {CCI_REG8(0x030a), 0x21},
+       {CCI_REG8(0x030b), 0x00},
+       {CCI_REG8(0x030c), 0x28},
+       {CCI_REG8(0x030d), 0x00},
+       {CCI_REG8(0x030e), 0x20},
+       {CCI_REG8(0x030f), 0x00},
+       {CCI_REG8(0x0310), 0x15},
+       {CCI_REG8(0x0311), 0x00},
+       {CCI_REG8(0x0312), 0x23},
+       {CCI_REG8(0x0313), 0x00},
+       {CCI_REG8(0x0314), 0x2b},
+       {CCI_REG8(0x0315), 0x00},
+       {CCI_REG8(0x0316), 0x21},
+       {CCI_REG8(0x0317), 0x00},
+       {CCI_REG8(0x0318), 0x14},
+       {CCI_REG8(0x0319), 0x00},
+       {CCI_REG8(0x031a), 0x24},
+       {CCI_REG8(0x031b), 0x00},
+       {CCI_REG8(0x031c), 0x29},
+       {CCI_REG8(0x031d), 0x00},
+       {CCI_REG8(0x031e), 0x23},
+       {CCI_REG8(0x031f), 0x00},
+       {CCI_REG8(0x0320), 0x15},
+       {CCI_REG8(0x0321), 0x00},
+       {CCI_REG8(0x0322), 0x21},
+       {CCI_REG8(0x0323), 0x00},
+       {CCI_REG8(0x0324), 0x29},
+       {CCI_REG8(0x0325), 0x00},
+       {CCI_REG8(0x0326), 0x23},
+       {CCI_REG8(0x0327), 0x00},
+       {CCI_REG8(0x0328), 0x0e},
+       {CCI_REG8(0x0329), 0x00},
+       {CCI_REG8(0x032a), 0x1b},
+       {CCI_REG8(0x032b), 0x00},
+       {CCI_REG8(0x032c), 0x20},
+       {CCI_REG8(0x032d), 0x00},
+       {CCI_REG8(0x032e), 0x1d},
+       {CCI_REG8(0x032f), 0x00},
+       {CCI_REG8(0x0330), 0x0f},
+       {CCI_REG8(0x0331), 0x00},
+       {CCI_REG8(0x0332), 0x15},
+       {CCI_REG8(0x0333), 0x00},
+       {CCI_REG8(0x0334), 0x1e},
+       {CCI_REG8(0x0335), 0x00},
+       {CCI_REG8(0x0336), 0x20},
+       {CCI_REG8(0x0337), 0x00},
+       {CCI_REG8(0x0338), 0x0d},
+       {CCI_REG8(0x0339), 0x00},
+       {CCI_REG8(0x033a), 0x1d},
+       {CCI_REG8(0x033b), 0x00},
+       {CCI_REG8(0x033c), 0x21},
+       {CCI_REG8(0x033d), 0x00},
+       {CCI_REG8(0x033e), 0x1e},
+       {CCI_REG8(0x033f), 0x00},
+       {CCI_REG8(0x0340), 0x09},
+       {CCI_REG8(0x0341), 0x00},
+       {CCI_REG8(0x0342), 0x05},
+       {CCI_REG8(0x0343), 0x00},
+       {CCI_REG8(0x0344), 0x03},
+       {CCI_REG8(0x0345), 0x00},
+       {CCI_REG8(0x0346), 0x0f},
+       {CCI_REG8(0x0347), 0x00},
+       {CCI_REG8(0x0348), 0x06},
+       {CCI_REG8(0x0349), 0x00},
+       {CCI_REG8(0x034a), 0x0b},
+       {CCI_REG8(0x034b), 0x00},
+       {CCI_REG8(0x034c), 0x0c},
+       {CCI_REG8(0x034d), 0x00},
+       {CCI_REG8(0x034e), 0x10},
+       {CCI_REG8(0x034f), 0x00},
+       {CCI_REG8(0x0350), 0x0b},
+       {CCI_REG8(0x0351), 0x00},
+       {CCI_REG8(0x0352), 0x11},
+       {CCI_REG8(0x0353), 0x00},
+       {CCI_REG8(0x0354), 0x10},
+       {CCI_REG8(0x0355), 0x00},
+       {CCI_REG8(0x0356), 0x14},
+       {CCI_REG8(0x0357), 0x00},
+       {CCI_REG8(0x0358), 0x0f},
+       {CCI_REG8(0x0359), 0x00},
+       {CCI_REG8(0x035a), 0x12},
+       {CCI_REG8(0x035b), 0x00},
+       {CCI_REG8(0x035c), 0x13},
+       {CCI_REG8(0x035d), 0x00},
+       {CCI_REG8(0x035e), 0x17},
+       {CCI_REG8(0x035f), 0x00},
+       {CCI_REG8(0x0360), 0x0e},
+       {CCI_REG8(0x0361), 0x00},
+       {CCI_REG8(0x0362), 0x14},
+       {CCI_REG8(0x0363), 0x00},
+       {CCI_REG8(0x0364), 0x13},
+       {CCI_REG8(0x0365), 0x00},
+       {CCI_REG8(0x0366), 0x18},
+       {CCI_REG8(0x0367), 0x00},
+       {CCI_REG8(0x0368), 0x11},
+       {CCI_REG8(0x0369), 0x00},
+       {CCI_REG8(0x036a), 0x11},
+       {CCI_REG8(0x036b), 0x00},
+       {CCI_REG8(0x036c), 0x12},
+       {CCI_REG8(0x036d), 0x00},
+       {CCI_REG8(0x036e), 0x19},
+       {CCI_REG8(0x036f), 0x00},
+       {CCI_REG8(0x0370), 0x0e},
+       {CCI_REG8(0x0371), 0x00},
+       {CCI_REG8(0x0372), 0x10},
+       {CCI_REG8(0x0373), 0x00},
+       {CCI_REG8(0x0374), 0x0f},
+       {CCI_REG8(0x0375), 0x00},
+       {CCI_REG8(0x0376), 0x18},
+       {CCI_REG8(0x0377), 0x00},
+       {CCI_REG8(0x0378), 0x10},
+       {CCI_REG8(0x0379), 0x00},
+       {CCI_REG8(0x037a), 0x0d},
+       {CCI_REG8(0x037b), 0x00},
+       {CCI_REG8(0x037c), 0x0f},
+       {CCI_REG8(0x037d), 0x00},
+       {CCI_REG8(0x037e), 0x19},
+       {CCI_REG8(0x037f), 0x00},
+       {CCI_REG8(0x0380), 0x0a},
+       {CCI_REG8(0x0381), 0x00},
+       {CCI_REG8(0x0382), 0x03},
+       {CCI_REG8(0x0383), 0x00},
+       {CCI_REG8(0x0384), 0x01},
+       {CCI_REG8(0x0385), 0x00},
+       {CCI_REG8(0x0386), 0x11},
+       {CCI_REG8(0x0387), 0x00},
+       {CCI_REG8(0x0388), 0x12},
+       {CCI_REG8(0x0389), 0x00},
+       {CCI_REG8(0x038a), 0x0e},
+       {CCI_REG8(0x038b), 0x00},
+       {CCI_REG8(0x038c), 0x0d},
+       {CCI_REG8(0x038d), 0x00},
+       {CCI_REG8(0x038e), 0x1b},
+       {CCI_REG8(0x038f), 0x00},
+       {CCI_REG8(0x0390), 0x02},
+       {CCI_REG8(0x0391), 0x40},
+       {CCI_REG8(0x0392), 0x02},
+       {CCI_REG8(0x0393), 0x40},
+       {CCI_REG8(0x0394), 0x01},
+       {CCI_REG8(0x0395), 0x00},
+       {CCI_REG8(0x0396), 0x0b},
+       {CCI_REG8(0x0397), 0x00},
+       {CCI_REG8(0x0398), 0x01},
+       {CCI_REG8(0x0399), 0x40},
+       {CCI_REG8(0x039a), 0x04},
+       {CCI_REG8(0x039b), 0x00},
+       {CCI_REG8(0x039c), 0x0a},
+       {CCI_REG8(0x039d), 0x00},
+       {CCI_REG8(0x039e), 0x07},
+       {CCI_REG8(0x039f), 0x00},
+       {CCI_REG8(0x03a0), 0x02},
+       {CCI_REG8(0x03a1), 0x00},
+       {CCI_REG8(0x03a2), 0x09},
+       {CCI_REG8(0x03a3), 0x00},
+       {CCI_REG8(0x03a4), 0x0e},
+       {CCI_REG8(0x03a5), 0x00},
+       {CCI_REG8(0x03a6), 0x0d},
+       {CCI_REG8(0x03a7), 0x00},
+       {CCI_REG8(0x03a8), 0x04},
+       {CCI_REG8(0x03a9), 0x00},
+       {CCI_REG8(0x03aa), 0x0b},
+       {CCI_REG8(0x03ab), 0x00},
+       {CCI_REG8(0x03ac), 0x0f},
+       {CCI_REG8(0x03ad), 0x00},
+       {CCI_REG8(0x03ae), 0x0f},
+       {CCI_REG8(0x03af), 0x00},
+       {CCI_REG8(0x03b0), 0x05},
+       {CCI_REG8(0x03b1), 0x00},
+       {CCI_REG8(0x03b2), 0x0b},
+       {CCI_REG8(0x03b3), 0x00},
+       {CCI_REG8(0x03b4), 0x10},
+       {CCI_REG8(0x03b5), 0x00},
+       {CCI_REG8(0x03b6), 0x10},
+       {CCI_REG8(0x03b7), 0x00},
+       {CCI_REG8(0x03b8), 0x05},
+       {CCI_REG8(0x03b9), 0x00},
+       {CCI_REG8(0x03ba), 0x0b},
+       {CCI_REG8(0x03bb), 0x00},
+       {CCI_REG8(0x03bc), 0x0d},
+       {CCI_REG8(0x03bd), 0x00},
+       {CCI_REG8(0x03be), 0x11},
+       {CCI_REG8(0x03bf), 0x00},
+       {CCI_REG8(0x03c0), 0x04},
+       {CCI_REG8(0x03c1), 0x00},
+       {CCI_REG8(0x03c2), 0x08},
+       {CCI_REG8(0x03c3), 0x00},
+       {CCI_REG8(0x03c4), 0x0c},
+       {CCI_REG8(0x03c5), 0x00},
+       {CCI_REG8(0x03c6), 0x10},
+       {CCI_REG8(0x03c7), 0x00},
+       {CCI_REG8(0x03c8), 0x04},
+       {CCI_REG8(0x03c9), 0x00},
+       {CCI_REG8(0x03ca), 0x06},
+       {CCI_REG8(0x03cb), 0x00},
+       {CCI_REG8(0x03cc), 0x09},
+       {CCI_REG8(0x03cd), 0x00},
+       {CCI_REG8(0x03ce), 0x0f},
+       {CCI_REG8(0x03cf), 0x00},
+       {CCI_REG8(0x03d0), 0x01},
+       {CCI_REG8(0x03d1), 0x00},
+       {CCI_REG8(0x03d2), 0x04},
+       {CCI_REG8(0x03d3), 0x40},
+       {CCI_REG8(0x03d4), 0x01},
+       {CCI_REG8(0x03d5), 0x40},
+       {CCI_REG8(0x03d6), 0x0d},
+       {CCI_REG8(0x03d7), 0x00},
+       {CCI_REG8(0x03d8), 0x05},
+       {CCI_REG8(0x03d9), 0x00},
+       {CCI_REG8(0x03da), 0x08},
+       {CCI_REG8(0x03db), 0x00},
+       {CCI_REG8(0x03dc), 0x0a},
+       {CCI_REG8(0x03dd), 0x00},
+       {CCI_REG8(0x03de), 0x11},
+       {CCI_REG8(0x03df), 0x00},
+       {CCI_REG8(0x03e0), 0x07},
+       {CCI_REG8(0x03e1), 0x40},
+       {CCI_REG8(0x03e2), 0x06},
+       {CCI_REG8(0x03e3), 0x40},
+       {CCI_REG8(0x03e4), 0x06},
+       {CCI_REG8(0x03e5), 0x40},
+       {CCI_REG8(0x03e6), 0x01},
+       {CCI_REG8(0x03e7), 0x40},
+       {CCI_REG8(0x03e8), 0x07},
+       {CCI_REG8(0x03e9), 0x40},
+       {CCI_REG8(0x03ec), 0x01},
+       {CCI_REG8(0x03ed), 0x40},
+       {CCI_REG8(0x03ee), 0x04},
+       {CCI_REG8(0x03ef), 0x00},
+       {CCI_REG8(0x03f0), 0x06},
+       {CCI_REG8(0x03f1), 0x40},
+       {CCI_REG8(0x03f2), 0x01},
+       {CCI_REG8(0x03f3), 0x00},
+       {CCI_REG8(0x03f4), 0x01},
+       {CCI_REG8(0x03f5), 0x00},
+       {CCI_REG8(0x03f6), 0x04},
+       {CCI_REG8(0x03f7), 0x00},
+       {CCI_REG8(0x03f8), 0x04},
+       {CCI_REG8(0x03f9), 0x40},
+       {CCI_REG8(0x03fa), 0x02},
+       {CCI_REG8(0x03fb), 0x00},
+       {CCI_REG8(0x03fc), 0x02},
+       {CCI_REG8(0x03fd), 0x00},
+       {CCI_REG8(0x03fe), 0x06},
+       {CCI_REG8(0x03ff), 0x00},
+       {CCI_REG8(0x0400), 0x04},
+       {CCI_REG8(0x0401), 0x40},
+       {CCI_REG8(0x0402), 0x02},
+       {CCI_REG8(0x0403), 0x00},
+       {CCI_REG8(0x0404), 0x02},
+       {CCI_REG8(0x0405), 0x00},
+       {CCI_REG8(0x0406), 0x05},
+       {CCI_REG8(0x0407), 0x00},
+       {CCI_REG8(0x0408), 0x03},
+       {CCI_REG8(0x0409), 0x40},
+       {CCI_REG8(0x040a), 0x01},
+       {CCI_REG8(0x040b), 0x40},
+       {CCI_REG8(0x040c), 0x01},
+       {CCI_REG8(0x040d), 0x00},
+       {CCI_REG8(0x040e), 0x07},
+       {CCI_REG8(0x040f), 0x00},
+       {CCI_REG8(0x0410), 0x05},
+       {CCI_REG8(0x0411), 0x40},
+       {CCI_REG8(0x0412), 0x02},
+       {CCI_REG8(0x0413), 0x40},
+       {CCI_REG8(0x0414), 0x02},
+       {CCI_REG8(0x0415), 0x40},
+       {CCI_REG8(0x0416), 0x05},
+       {CCI_REG8(0x0417), 0x00},
+       {CCI_REG8(0x0418), 0x02},
+       {CCI_REG8(0x0419), 0x40},
+       {CCI_REG8(0x041a), 0x04},
+       {CCI_REG8(0x041b), 0x40},
+       {CCI_REG8(0x041c), 0x03},
+       {CCI_REG8(0x041d), 0x40},
+       {CCI_REG8(0x041e), 0x07},
+       {CCI_REG8(0x041f), 0x00},
+       {CCI_REG8(0x0420), 0x05},
+       {CCI_REG8(0x0421), 0x40},
+       {CCI_REG8(0x0422), 0x0c},
+       {CCI_REG8(0x0423), 0x40},
+       {CCI_REG8(0x0424), 0x0c},
+       {CCI_REG8(0x0425), 0x40},
+       {CCI_REG8(0x0426), 0x03},
+       {CCI_REG8(0x0427), 0x00},
+       {CCI_REG8(0x0428), 0x02},
+       {CCI_REG8(0x0429), 0x40},
+       {CCI_REG8(0x042a), 0x05},
+       {CCI_REG8(0x042b), 0x40},
+       {CCI_REG8(0x042c), 0x04},
+       {CCI_REG8(0x042d), 0x40},
+       {CCI_REG8(0x042e), 0x0a},
+       {CCI_REG8(0x042f), 0x00},
+       {CCI_REG8(0x0430), 0x0d},
+       {CCI_REG8(0x0431), 0x40},
+       {CCI_REG8(0x0432), 0x15},
+       {CCI_REG8(0x0433), 0x40},
+       {CCI_REG8(0x0434), 0x14},
+       {CCI_REG8(0x0435), 0x40},
+       {CCI_REG8(0x0436), 0x02},
+       {CCI_REG8(0x0437), 0x00},
+       {CCI_REG8(0x0438), 0x0f},
+       {CCI_REG8(0x0439), 0x40},
+       {CCI_REG8(0x043a), 0x0b},
+       {CCI_REG8(0x043b), 0x40},
+       {CCI_REG8(0x043c), 0x06},
+       {CCI_REG8(0x043d), 0x40},
+       {CCI_REG8(0x043e), 0x08},
+       {CCI_REG8(0x043f), 0x40},
+       {CCI_REG8(0x0440), 0x11},
+       {CCI_REG8(0x0441), 0x40},
+       {CCI_REG8(0x0442), 0x0a},
+       {CCI_REG8(0x0443), 0x40},
+       {CCI_REG8(0x0444), 0x07},
+       {CCI_REG8(0x0445), 0x40},
+       {CCI_REG8(0x0446), 0x05},
+       {CCI_REG8(0x0447), 0x40},
+       {CCI_REG8(0x0448), 0x11},
+       {CCI_REG8(0x0449), 0x40},
+       {CCI_REG8(0x044a), 0x0d},
+       {CCI_REG8(0x044b), 0x40},
+       {CCI_REG8(0x044c), 0x09},
+       {CCI_REG8(0x044d), 0x40},
+       {CCI_REG8(0x044e), 0x07},
+       {CCI_REG8(0x044f), 0x40},
+       {CCI_REG8(0x0450), 0x12},
+       {CCI_REG8(0x0451), 0x40},
+       {CCI_REG8(0x0452), 0x0c},
+       {CCI_REG8(0x0453), 0x40},
+       {CCI_REG8(0x0454), 0x09},
+       {CCI_REG8(0x0455), 0x40},
+       {CCI_REG8(0x0456), 0x07},
+       {CCI_REG8(0x0457), 0x40},
+       {CCI_REG8(0x0458), 0x12},
+       {CCI_REG8(0x0459), 0x40},
+       {CCI_REG8(0x045a), 0x0f},
+       {CCI_REG8(0x045b), 0x40},
+       {CCI_REG8(0x045c), 0x0d},
+       {CCI_REG8(0x045d), 0x40},
+       {CCI_REG8(0x045e), 0x07},
+       {CCI_REG8(0x045f), 0x40},
+       {CCI_REG8(0x0460), 0x13},
+       {CCI_REG8(0x0461), 0x40},
+       {CCI_REG8(0x0462), 0x10},
+       {CCI_REG8(0x0463), 0x40},
+       {CCI_REG8(0x0464), 0x0e},
+       {CCI_REG8(0x0465), 0x40},
+       {CCI_REG8(0x0466), 0x09},
+       {CCI_REG8(0x0467), 0x40},
+       {CCI_REG8(0x0468), 0x11},
+       {CCI_REG8(0x0469), 0x40},
+       {CCI_REG8(0x046a), 0x11},
+       {CCI_REG8(0x046b), 0x40},
+       {CCI_REG8(0x046c), 0x0e},
+       {CCI_REG8(0x046d), 0x40},
+       {CCI_REG8(0x046e), 0x06},
+       {CCI_REG8(0x046f), 0x40},
+       {CCI_REG8(0x0470), 0x13},
+       {CCI_REG8(0x0471), 0x40},
+       {CCI_REG8(0x0472), 0x1a},
+       {CCI_REG8(0x0473), 0x40},
+       {CCI_REG8(0x0474), 0x17},
+       {CCI_REG8(0x0475), 0x40},
+       {CCI_REG8(0x0476), 0x09},
+       {CCI_REG8(0x0477), 0x40},
+       {CCI_REG8(0x0478), 0x0e},
+       {CCI_REG8(0x0479), 0x40},
+       {CCI_REG8(0x047a), 0x10},
+       {CCI_REG8(0x047b), 0x40},
+       {CCI_REG8(0x047c), 0x0d},
+       {CCI_REG8(0x047d), 0x40},
+       {CCI_REG8(0x047e), 0x03},
+       {CCI_REG8(0x047f), 0x40},
+       {CCI_REG8(0x0480), 0x17},
+       {CCI_REG8(0x0481), 0x40},
+       {CCI_REG8(0x0482), 0x23},
+       {CCI_REG8(0x0483), 0x40},
+       {CCI_REG8(0x0484), 0x1a},
+       {CCI_REG8(0x0485), 0x40},
+       {CCI_REG8(0x0486), 0x0b},
+       {CCI_REG8(0x0487), 0x40},
+       {CCI_REG8(0x0488), 0x19},
+       {CCI_REG8(0x0489), 0x40},
+       {CCI_REG8(0x048a), 0x18},
+       {CCI_REG8(0x048b), 0x40},
+       {CCI_REG8(0x048c), 0x14},
+       {CCI_REG8(0x048d), 0x40},
+       {CCI_REG8(0x048e), 0x0e},
+       {CCI_REG8(0x048f), 0x40},
+       {CCI_REG8(0x0490), 0x1c},
+       {CCI_REG8(0x0491), 0x40},
+       {CCI_REG8(0x0492), 0x19},
+       {CCI_REG8(0x0493), 0x40},
+       {CCI_REG8(0x0494), 0x13},
+       {CCI_REG8(0x0495), 0x40},
+       {CCI_REG8(0x0496), 0x13},
+       {CCI_REG8(0x0497), 0x40},
+       {CCI_REG8(0x0498), 0x1f},
+       {CCI_REG8(0x0499), 0x40},
+       {CCI_REG8(0x049a), 0x1b},
+       {CCI_REG8(0x049b), 0x40},
+       {CCI_REG8(0x049c), 0x19},
+       {CCI_REG8(0x049d), 0x40},
+       {CCI_REG8(0x049e), 0x13},
+       {CCI_REG8(0x049f), 0x40},
+       {CCI_REG8(0x04a0), 0x20},
+       {CCI_REG8(0x04a1), 0x40},
+       {CCI_REG8(0x04a2), 0x1d},
+       {CCI_REG8(0x04a3), 0x40},
+       {CCI_REG8(0x04a4), 0x17},
+       {CCI_REG8(0x04a5), 0x40},
+       {CCI_REG8(0x04a6), 0x15},
+       {CCI_REG8(0x04a7), 0x40},
+       {CCI_REG8(0x04a8), 0x1d},
+       {CCI_REG8(0x04a9), 0x40},
+       {CCI_REG8(0x04aa), 0x1d},
+       {CCI_REG8(0x04ab), 0x40},
+       {CCI_REG8(0x04ac), 0x1b},
+       {CCI_REG8(0x04ad), 0x40},
+       {CCI_REG8(0x04ae), 0x13},
+       {CCI_REG8(0x04af), 0x40},
+       {CCI_REG8(0x04b0), 0x20},
+       {CCI_REG8(0x04b1), 0x40},
+       {CCI_REG8(0x04b2), 0x1f},
+       {CCI_REG8(0x04b3), 0x40},
+       {CCI_REG8(0x04b4), 0x1b},
+       {CCI_REG8(0x04b5), 0x40},
+       {CCI_REG8(0x04b6), 0x13},
+       {CCI_REG8(0x04b7), 0x40},
+       {CCI_REG8(0x04b8), 0x1d},
+       {CCI_REG8(0x04b9), 0x40},
+       {CCI_REG8(0x04ba), 0x20},
+       {CCI_REG8(0x04bb), 0x40},
+       {CCI_REG8(0x04bc), 0x1e},
+       {CCI_REG8(0x04bd), 0x40},
+       {CCI_REG8(0x04be), 0x14},
+       {CCI_REG8(0x04bf), 0x40},
+       {CCI_REG8(0x04c0), 0x1d},
+       {CCI_REG8(0x04c1), 0x40},
+       {CCI_REG8(0x04c2), 0x25},
+       {CCI_REG8(0x04c3), 0x40},
+       {CCI_REG8(0x04c4), 0x20},
+       {CCI_REG8(0x04c5), 0x40},
+       {CCI_REG8(0x04c6), 0x0f},
+       {CCI_REG8(0x04c7), 0x40},
+       {CCI_REG8(0x04c8), 0x19},
+       {CCI_REG8(0x04c9), 0x40},
+       {CCI_REG8(0x04ca), 0x20},
+       {CCI_REG8(0x04cb), 0x40},
+       {CCI_REG8(0x04cc), 0x20},
+       {CCI_REG8(0x04cd), 0x40},
+       {CCI_REG8(0x04ce), 0x10},
+       {CCI_REG8(0x04cf), 0x40},
+       {CCI_REG8(0x04d0), 0x01},
+       {CCI_REG8(0x04d1), 0x00},
+       {CCI_REG8(0x04d2), 0x03},
+       {CCI_REG8(0x04d3), 0x00},
+       {CCI_REG8(0x04d4), 0x0b},
+       {CCI_REG8(0x04d5), 0x40},
+       {CCI_REG8(0x04d6), 0x12},
+       {CCI_REG8(0x04d7), 0x00},
+       {CCI_REG8(0x04d8), 0x07},
+       {CCI_REG8(0x04d9), 0x40},
+       {CCI_REG8(0x04da), 0x06},
+       {CCI_REG8(0x04db), 0x00},
+       {CCI_REG8(0x04dc), 0x0b},
+       {CCI_REG8(0x04dd), 0x00},
+       {CCI_REG8(0x04de), 0x07},
+       {CCI_REG8(0x04df), 0x00},
+       {CCI_REG8(0x04e0), 0x04},
+       {CCI_REG8(0x04e1), 0x40},
+       {CCI_REG8(0x04e2), 0x0a},
+       {CCI_REG8(0x04e3), 0x00},
+       {CCI_REG8(0x04e4), 0x0b},
+       {CCI_REG8(0x04e5), 0x00},
+       {CCI_REG8(0x04e6), 0x0c},
+       {CCI_REG8(0x04e7), 0x00},
+       {CCI_REG8(0x04e8), 0x02},
+       {CCI_REG8(0x04e9), 0x40},
+       {CCI_REG8(0x04ea), 0x05},
+       {CCI_REG8(0x04eb), 0x00},
+       {CCI_REG8(0x04ec), 0x0d},
+       {CCI_REG8(0x04ed), 0x00},
+       {CCI_REG8(0x04ee), 0x0b},
+       {CCI_REG8(0x04ef), 0x00},
+       {CCI_REG8(0x04f2), 0x09},
+       {CCI_REG8(0x04f3), 0x00},
+       {CCI_REG8(0x04f4), 0x0a},
+       {CCI_REG8(0x04f5), 0x00},
+       {CCI_REG8(0x04f6), 0x0d},
+       {CCI_REG8(0x04f7), 0x00},
+       {CCI_REG8(0x04f8), 0x08},
+       {CCI_REG8(0x04f9), 0x40},
+       {CCI_REG8(0x04fa), 0x04},
+       {CCI_REG8(0x04fb), 0x00},
+       {CCI_REG8(0x04fc), 0x08},
+       {CCI_REG8(0x04fd), 0x00},
+       {CCI_REG8(0x04fe), 0x0a},
+       {CCI_REG8(0x04ff), 0x00},
+       {CCI_REG8(0x0500), 0x04},
+       {CCI_REG8(0x0501), 0x40},
+       {CCI_REG8(0x0504), 0x04},
+       {CCI_REG8(0x0505), 0x00},
+       {CCI_REG8(0x0506), 0x06},
+       {CCI_REG8(0x0507), 0x00},
+       {CCI_REG8(0x0508), 0x03},
+       {CCI_REG8(0x0509), 0x40},
+       {CCI_REG8(0x050a), 0x03},
+       {CCI_REG8(0x050b), 0x00},
+       {CCI_REG8(0x050c), 0x09},
+       {CCI_REG8(0x050d), 0x00},
+       {CCI_REG8(0x050e), 0x0f},
+       {CCI_REG8(0x050f), 0x00},
+       {CCI_REG8(0x0510), 0x08},
+       {CCI_REG8(0x0511), 0x40},
+       {CCI_REG8(0x0512), 0x0d},
+       {CCI_REG8(0x0513), 0x40},
+       {CCI_REG8(0x0514), 0x0b},
+       {CCI_REG8(0x0515), 0x40},
+       {CCI_REG8(0x0516), 0x01},
+       {CCI_REG8(0x0517), 0x00},
+       {CCI_REG8(0x051a), 0x01},
+       {CCI_REG8(0x051b), 0x00},
+       {CCI_REG8(0x051c), 0x0f},
+       {CCI_REG8(0x051d), 0x00},
+       {CCI_REG8(0x051e), 0x10},
+       {CCI_REG8(0x051f), 0x00},
+       {CCI_REG8(0x0570), 0x13},
+       {CCI_REG8(0x0571), 0x40},
+       {CCI_REG8(0x0572), 0x2f},
+       {CCI_REG8(0x0573), 0x00},
+       {CCI_REG8(0x0574), 0x04},
+       {CCI_REG8(0x0575), 0x00},
+       {CCI_REG8(0x0576), 0x11},
+       {CCI_REG8(0x0577), 0x00},
+       {CCI_REG8(0x0578), 0x1d},
+       {CCI_REG8(0x0579), 0x00},
+       {CCI_REG8(0x057a), 0x0a},
+       {CCI_REG8(0x057b), 0x00},
+       {CCI_REG8(0x057c), 0x18},
+       {CCI_REG8(0x057d), 0x00},
+       {CCI_REG8(0x057e), 0x21},
+       {CCI_REG8(0x057f), 0x00},
+       {CCI_REG8(0x0580), 0x69},
+       {CCI_REG8(0x0581), 0x00},
+       {CCI_REG8(0x0582), 0x6d},
+       {CCI_REG8(0x0583), 0x00},
+       {CCI_REG8(0x0584), 0x72},
+       {CCI_REG8(0x0585), 0x00},
+       {CCI_REG8(0x0586), 0x79},
+       {CCI_REG8(0x0587), 0x00},
+       {CCI_REG8(0x0588), 0x6f},
+       {CCI_REG8(0x0589), 0x00},
+       {CCI_REG8(0x058a), 0x6a},
+       {CCI_REG8(0x058b), 0x00},
+       {CCI_REG8(0x058c), 0x79},
+       {CCI_REG8(0x058d), 0x00},
+       {CCI_REG8(0x058e), 0x60},
+       {CCI_REG8(0x058f), 0x00},
+       {CCI_REG8(0x0590), 0x72},
+       {CCI_REG8(0x0591), 0x00},
+       {CCI_REG8(0x0592), 0x72},
+       {CCI_REG8(0x0593), 0x00},
+       {CCI_REG8(0x0594), 0x6f},
+       {CCI_REG8(0x0595), 0x00},
+       {CCI_REG8(0x0596), 0x7b},
+       {CCI_REG8(0x0597), 0x00},
+       {CCI_REG8(0x0598), 0x7b},
+       {CCI_REG8(0x0599), 0x00},
+       {CCI_REG8(0x059a), 0x69},
+       {CCI_REG8(0x059b), 0x00},
+       {CCI_REG8(0x059c), 0x7b},
+       {CCI_REG8(0x059d), 0x00},
+       {CCI_REG8(0x059e), 0x65},
+       {CCI_REG8(0x059f), 0x00},
+       {CCI_REG8(0x05a0), 0x79},
+       {CCI_REG8(0x05a1), 0x00},
+       {CCI_REG8(0x05a2), 0x7c},
+       {CCI_REG8(0x05a3), 0x00},
+       {CCI_REG8(0x05a4), 0x72},
+       {CCI_REG8(0x05a5), 0x00},
+       {CCI_REG8(0x05a6), 0x74},
+       {CCI_REG8(0x05a7), 0x00},
+       {CCI_REG8(0x05a8), 0x3e},
+       {CCI_REG8(0x05a9), 0x00},
+       {CCI_REG8(0x05aa), 0x39},
+       {CCI_REG8(0x05ab), 0x00},
+       {CCI_REG8(0x05ac), 0x48},
+       {CCI_REG8(0x05ad), 0x00},
+       {CCI_REG8(0x05ae), 0x50},
+       {CCI_REG8(0x05af), 0x00},
+       {CCI_REG8(0x05b0), 0x10},
+       {CCI_REG8(0x05b1), 0x40},
+       {CCI_REG8(0x05b2), 0x26},
+       {CCI_REG8(0x05b3), 0x40},
+       {CCI_REG8(0x05b4), 0x2c},
+       {CCI_REG8(0x05b5), 0x40},
+       {CCI_REG8(0x05b6), 0x24},
+       {CCI_REG8(0x05b7), 0x40},
+       {CCI_REG8(0x05b8), 0x2f},
+       {CCI_REG8(0x05b9), 0x00},
+       {CCI_REG8(0x05ba), 0x1c},
+       {CCI_REG8(0x05bb), 0x00},
+       {CCI_REG8(0x05bc), 0x33},
+       {CCI_REG8(0x05bd), 0x00},
+       {CCI_REG8(0x05be), 0x65},
+       {CCI_REG8(0x05bf), 0x00},
+       {CCI_REG8(0x05c0), 0x1b},
+       {CCI_REG8(0x05c1), 0x40},
+       {CCI_REG8(0x05c2), 0x3f},
+       {CCI_REG8(0x05c3), 0x40},
+       {CCI_REG8(0x05c4), 0x2f},
+       {CCI_REG8(0x05c5), 0x40},
+       {CCI_REG8(0x05c6), 0x33},
+       {CCI_REG8(0x05c7), 0x40},
+       {CCI_REG8(0x05c8), 0xc0},
+       {CCI_REG8(0x05c9), 0x40},
+       {CCI_REG8(0x05ca), 0xcb},
+       {CCI_REG8(0x05cb), 0x40},
+       {CCI_REG8(0x05cc), 0xcf},
+       {CCI_REG8(0x05cd), 0x40},
+       {CCI_REG8(0x05ce), 0xc1},
+       {CCI_REG8(0x05cf), 0x40},
+       {CCI_REG8(0x05d0), 0xe5},
+       {CCI_REG8(0x05d1), 0x40},
+       {CCI_REG8(0x05d2), 0xfa},
+       {CCI_REG8(0x05d3), 0x40},
+       {CCI_REG8(0x05d4), 0xfa},
+       {CCI_REG8(0x05d5), 0x40},
+       {CCI_REG8(0x05d6), 0xee},
+       {CCI_REG8(0x05d7), 0x40},
+       {CCI_REG8(0x05d8), 0xee},
+       {CCI_REG8(0x05d9), 0x40},
+       {CCI_REG8(0x05da), 0xfd},
+       {CCI_REG8(0x05db), 0x40},
+       {CCI_REG8(0x05dc), 0x02},
+       {CCI_REG8(0x05dd), 0x41},
+       {CCI_REG8(0x05de), 0xed},
+       {CCI_REG8(0x05df), 0x40},
+       {CCI_REG8(0x05e0), 0xef},
+       {CCI_REG8(0x05e1), 0x40},
+       {CCI_REG8(0x05e2), 0xfe},
+       {CCI_REG8(0x05e3), 0x40},
+       {CCI_REG8(0x05e4), 0xfc},
+       {CCI_REG8(0x05e5), 0x40},
+       {CCI_REG8(0x05e6), 0xf9},
+       {CCI_REG8(0x05e7), 0x40},
+       {CCI_REG8(0x05e8), 0xfa},
+       {CCI_REG8(0x05e9), 0x40},
+       {CCI_REG8(0x05ea), 0x02},
+       {CCI_REG8(0x05eb), 0x41},
+       {CCI_REG8(0x05ec), 0x06},
+       {CCI_REG8(0x05ed), 0x41},
+       {CCI_REG8(0x05ee), 0xf6},
+       {CCI_REG8(0x05ef), 0x40},
+       {CCI_REG8(0x05f0), 0xec},
+       {CCI_REG8(0x05f1), 0x40},
+       {CCI_REG8(0x05f2), 0xfe},
+       {CCI_REG8(0x05f3), 0x40},
+       {CCI_REG8(0x05f4), 0xfe},
+       {CCI_REG8(0x05f5), 0x40},
+       {CCI_REG8(0x05f6), 0xf5},
+       {CCI_REG8(0x05f7), 0x40},
+       {CCI_REG8(0x05f8), 0xd4},
+       {CCI_REG8(0x05f9), 0x40},
+       {CCI_REG8(0x05fa), 0xe3},
+       {CCI_REG8(0x05fb), 0x40},
+       {CCI_REG8(0x05fc), 0xe1},
+       {CCI_REG8(0x05fd), 0x40},
+       {CCI_REG8(0x05fe), 0xd9},
+       {CCI_REG8(0x05ff), 0x40},
+       {CCI_REG8(0x0600), 0x19},
+       {CCI_REG8(0x0601), 0x40},
+       {CCI_REG8(0x0602), 0x24},
+       {CCI_REG8(0x0603), 0x40},
+       {CCI_REG8(0x0604), 0x2a},
+       {CCI_REG8(0x0605), 0x40},
+       {CCI_REG8(0x0606), 0x1d},
+       {CCI_REG8(0x0607), 0x40},
+       {CCI_REG8(0x0608), 0xcd},
+       {CCI_REG8(0x0609), 0x40},
+       {CCI_REG8(0x060a), 0xd7},
+       {CCI_REG8(0x060b), 0x40},
+       {CCI_REG8(0x060c), 0xd1},
+       {CCI_REG8(0x060d), 0x40},
+       {CCI_REG8(0x060e), 0xdf},
+       {CCI_REG8(0x060f), 0x40},
+       {CCI_REG8(0x0610), 0x66},
+       {CCI_REG8(0x0611), 0x40},
+       {CCI_REG8(0x0612), 0x65},
+       {CCI_REG8(0x0613), 0x40},
+       {CCI_REG8(0x0614), 0x63},
+       {CCI_REG8(0x0615), 0x40},
+       {CCI_REG8(0x0616), 0x57},
+       {CCI_REG8(0x0617), 0x40},
+       {CCI_REG8(0x0618), 0xca},
+       {CCI_REG8(0x0619), 0x40},
+       {CCI_REG8(0x061a), 0xdc},
+       {CCI_REG8(0x061b), 0x40},
+       {CCI_REG8(0x061c), 0xdc},
+       {CCI_REG8(0x061d), 0x40},
+       {CCI_REG8(0x061e), 0xd2},
+       {CCI_REG8(0x061f), 0x40},
+       {CCI_REG8(0x0620), 0xf0},
+       {CCI_REG8(0x0621), 0x40},
+       {CCI_REG8(0x0622), 0x02},
+       {CCI_REG8(0x0623), 0x41},
+       {CCI_REG8(0x0624), 0xfe},
+       {CCI_REG8(0x0625), 0x40},
+       {CCI_REG8(0x0626), 0xef},
+       {CCI_REG8(0x0627), 0x40},
+       {CCI_REG8(0x0628), 0xfc},
+       {CCI_REG8(0x0629), 0x40},
+       {CCI_REG8(0x062a), 0x09},
+       {CCI_REG8(0x062b), 0x41},
+       {CCI_REG8(0x062c), 0x0a},
+       {CCI_REG8(0x062d), 0x41},
+       {CCI_REG8(0x062e), 0x06},
+       {CCI_REG8(0x062f), 0x41},
+       {CCI_REG8(0x0630), 0x0b},
+       {CCI_REG8(0x0631), 0x41},
+       {CCI_REG8(0x0632), 0x15},
+       {CCI_REG8(0x0633), 0x41},
+       {CCI_REG8(0x0634), 0x12},
+       {CCI_REG8(0x0635), 0x41},
+       {CCI_REG8(0x0636), 0x0c},
+       {CCI_REG8(0x0637), 0x41},
+       {CCI_REG8(0x0638), 0x08},
+       {CCI_REG8(0x0639), 0x41},
+       {CCI_REG8(0x063a), 0x19},
+       {CCI_REG8(0x063b), 0x41},
+       {CCI_REG8(0x063c), 0x15},
+       {CCI_REG8(0x063d), 0x41},
+       {CCI_REG8(0x063e), 0x14},
+       {CCI_REG8(0x063f), 0x41},
+       {CCI_REG8(0x0640), 0x00},
+       {CCI_REG8(0x0641), 0x41},
+       {CCI_REG8(0x0642), 0x09},
+       {CCI_REG8(0x0643), 0x41},
+       {CCI_REG8(0x0644), 0x09},
+       {CCI_REG8(0x0645), 0x41},
+       {CCI_REG8(0x0646), 0x01},
+       {CCI_REG8(0x0647), 0x41},
+       {CCI_REG8(0x0648), 0xe3},
+       {CCI_REG8(0x0649), 0x40},
+       {CCI_REG8(0x064a), 0xf7},
+       {CCI_REG8(0x064b), 0x40},
+       {CCI_REG8(0x064c), 0xf9},
+       {CCI_REG8(0x064d), 0x40},
+       {CCI_REG8(0x064e), 0xec},
+       {CCI_REG8(0x064f), 0x40},
+       {CCI_REG8(0x0650), 0x1f},
+       {CCI_REG8(0x0651), 0x40},
+       {CCI_REG8(0x0652), 0x2b},
+       {CCI_REG8(0x0653), 0x40},
+       {CCI_REG8(0x0654), 0x2e},
+       {CCI_REG8(0x0655), 0x40},
+       {CCI_REG8(0x0656), 0x23},
+       {CCI_REG8(0x0657), 0x40},
+       {CCI_REG8(0x0658), 0xda},
+       {CCI_REG8(0x0659), 0x40},
+       {CCI_REG8(0x065a), 0xee},
+       {CCI_REG8(0x065b), 0x40},
+       {CCI_REG8(0x065c), 0xf3},
+       {CCI_REG8(0x065d), 0x40},
+       {CCI_REG8(0x065e), 0xe4},
+       {CCI_REG8(0x065f), 0x40},
+       {CCI_REG8(0x0660), 0x34},
+       {CCI_REG8(0x0661), 0x40},
+       {CCI_REG8(0x0662), 0x34},
+       {CCI_REG8(0x0663), 0x40},
+       {CCI_REG8(0x0664), 0x39},
+       {CCI_REG8(0x0665), 0x40},
+       {CCI_REG8(0x0666), 0x33},
+       {CCI_REG8(0x0667), 0x40},
+       {CCI_REG8(0x0668), 0xa5},
+       {CCI_REG8(0x0669), 0x40},
+       {CCI_REG8(0x066a), 0xb7},
+       {CCI_REG8(0x066b), 0x40},
+       {CCI_REG8(0x066c), 0xb6},
+       {CCI_REG8(0x066d), 0x40},
+       {CCI_REG8(0x066e), 0xa7},
+       {CCI_REG8(0x066f), 0x40},
+       {CCI_REG8(0x0670), 0xc8},
+       {CCI_REG8(0x0671), 0x40},
+       {CCI_REG8(0x0672), 0xd6},
+       {CCI_REG8(0x0673), 0x40},
+       {CCI_REG8(0x0674), 0xdc},
+       {CCI_REG8(0x0675), 0x40},
+       {CCI_REG8(0x0676), 0xca},
+       {CCI_REG8(0x0677), 0x40},
+       {CCI_REG8(0x0678), 0xd9},
+       {CCI_REG8(0x0679), 0x40},
+       {CCI_REG8(0x067a), 0xe9},
+       {CCI_REG8(0x067b), 0x40},
+       {CCI_REG8(0x067c), 0xe6},
+       {CCI_REG8(0x067d), 0x40},
+       {CCI_REG8(0x067e), 0xda},
+       {CCI_REG8(0x067f), 0x40},
+       {CCI_REG8(0x0680), 0xe4},
+       {CCI_REG8(0x0681), 0x40},
+       {CCI_REG8(0x0682), 0xf1},
+       {CCI_REG8(0x0683), 0x40},
+       {CCI_REG8(0x0684), 0xf2},
+       {CCI_REG8(0x0685), 0x40},
+       {CCI_REG8(0x0686), 0xec},
+       {CCI_REG8(0x0687), 0x40},
+       {CCI_REG8(0x0688), 0xe3},
+       {CCI_REG8(0x0689), 0x40},
+       {CCI_REG8(0x068a), 0xf0},
+       {CCI_REG8(0x068b), 0x40},
+       {CCI_REG8(0x068c), 0xf2},
+       {CCI_REG8(0x068d), 0x40},
+       {CCI_REG8(0x068e), 0xe6},
+       {CCI_REG8(0x068f), 0x40},
+       {CCI_REG8(0x0690), 0xe5},
+       {CCI_REG8(0x0691), 0x40},
+       {CCI_REG8(0x0692), 0xed},
+       {CCI_REG8(0x0693), 0x40},
+       {CCI_REG8(0x0694), 0xf1},
+       {CCI_REG8(0x0695), 0x40},
+       {CCI_REG8(0x0696), 0xe7},
+       {CCI_REG8(0x0697), 0x40},
+       {CCI_REG8(0x0698), 0xc4},
+       {CCI_REG8(0x0699), 0x40},
+       {CCI_REG8(0x069a), 0xd3},
+       {CCI_REG8(0x069b), 0x40},
+       {CCI_REG8(0x069c), 0xd2},
+       {CCI_REG8(0x069d), 0x40},
+       {CCI_REG8(0x069e), 0xca},
+       {CCI_REG8(0x069f), 0x40},
+       {CCI_REG8(0x06a0), 0x08},
+       {CCI_REG8(0x06a1), 0x00},
+       {CCI_REG8(0x06a2), 0x08},
+       {CCI_REG8(0x06a3), 0x40},
+       {CCI_REG8(0x06a4), 0x09},
+       {CCI_REG8(0x06a5), 0x40},
+       {CCI_REG8(0x06a6), 0x05},
+       {CCI_REG8(0x06a7), 0x00},
+       {CCI_REG8(0x06a8), 0xb6},
+       {CCI_REG8(0x06a9), 0x40},
+       {CCI_REG8(0x06aa), 0xc9},
+       {CCI_REG8(0x06ab), 0x40},
+       {CCI_REG8(0x06ac), 0xc7},
+       {CCI_REG8(0x06ad), 0x40},
+       {CCI_REG8(0x06ae), 0xc1},
+       {CCI_REG8(0x06af), 0x40},
+       {CCI_REG8(0x06b0), 0x03},
+       {CCI_REG8(0x06b1), 0x00},
+       {CCI_REG8(0x06b2), 0x0c},
+       {CCI_REG8(0x06b3), 0x40},
+       {CCI_REG8(0x06b4), 0x0e},
+       {CCI_REG8(0x06b5), 0x40},
+       {CCI_REG8(0x06b6), 0x03},
+       {CCI_REG8(0x06b7), 0x40},
+       {CCI_REG8(0x06b8), 0x93},
+       {CCI_REG8(0x06b9), 0x40},
+       {CCI_REG8(0x06ba), 0xa5},
+       {CCI_REG8(0x06bb), 0x40},
+       {CCI_REG8(0x06bc), 0xa3},
+       {CCI_REG8(0x06bd), 0x40},
+       {CCI_REG8(0x06be), 0x9b},
+       {CCI_REG8(0x06bf), 0x40},
+       {CCI_REG8(0x06c0), 0xd0},
+       {CCI_REG8(0x06c1), 0x40},
+       {CCI_REG8(0x06c2), 0xe1},
+       {CCI_REG8(0x06c3), 0x40},
+       {CCI_REG8(0x06c4), 0xe3},
+       {CCI_REG8(0x06c5), 0x40},
+       {CCI_REG8(0x06c6), 0xd6},
+       {CCI_REG8(0x06c7), 0x40},
+       {CCI_REG8(0x06c8), 0xe3},
+       {CCI_REG8(0x06c9), 0x40},
+       {CCI_REG8(0x06ca), 0xf2},
+       {CCI_REG8(0x06cb), 0x40},
+       {CCI_REG8(0x06cc), 0xef},
+       {CCI_REG8(0x06cd), 0x40},
+       {CCI_REG8(0x06ce), 0xe1},
+       {CCI_REG8(0x06cf), 0x40},
+       {CCI_REG8(0x06d0), 0xe5},
+       {CCI_REG8(0x06d1), 0x40},
+       {CCI_REG8(0x06d2), 0xed},
+       {CCI_REG8(0x06d3), 0x40},
+       {CCI_REG8(0x06d4), 0xf2},
+       {CCI_REG8(0x06d5), 0x40},
+       {CCI_REG8(0x06d6), 0xec},
+       {CCI_REG8(0x06d7), 0x40},
+       {CCI_REG8(0x06d8), 0xef},
+       {CCI_REG8(0x06d9), 0x40},
+       {CCI_REG8(0x06da), 0x02},
+       {CCI_REG8(0x06db), 0x41},
+       {CCI_REG8(0x06dc), 0xfd},
+       {CCI_REG8(0x06dd), 0x40},
+       {CCI_REG8(0x06de), 0xf9},
+       {CCI_REG8(0x06df), 0x40},
+       {CCI_REG8(0x06e0), 0xf8},
+       {CCI_REG8(0x06e1), 0x40},
+       {CCI_REG8(0x06e2), 0x04},
+       {CCI_REG8(0x06e3), 0x41},
+       {CCI_REG8(0x06e4), 0x07},
+       {CCI_REG8(0x06e5), 0x41},
+       {CCI_REG8(0x06e6), 0xf6},
+       {CCI_REG8(0x06e7), 0x40},
+       {CCI_REG8(0x06e8), 0xd2},
+       {CCI_REG8(0x06e9), 0x40},
+       {CCI_REG8(0x06ea), 0xe2},
+       {CCI_REG8(0x06eb), 0x40},
+       {CCI_REG8(0x06ec), 0xe5},
+       {CCI_REG8(0x06ed), 0x40},
+       {CCI_REG8(0x06ee), 0xd7},
+       {CCI_REG8(0x06ef), 0x40},
+       {CCI_REG8(0x06f0), 0x0c},
+       {CCI_REG8(0x06f1), 0x00},
+       {CCI_REG8(0x06f2), 0x03},
+       {CCI_REG8(0x06f3), 0x00},
+       {CCI_REG8(0x06f4), 0x03},
+       {CCI_REG8(0x06f5), 0x40},
+       {CCI_REG8(0x06f6), 0x0b},
+       {CCI_REG8(0x06f7), 0x00},
+       {CCI_REG8(0x06f8), 0xc4},
+       {CCI_REG8(0x06f9), 0x40},
+       {CCI_REG8(0x06fa), 0xd5},
+       {CCI_REG8(0x06fb), 0x40},
+       {CCI_REG8(0x06fc), 0xdc},
+       {CCI_REG8(0x06fd), 0x40},
+       {CCI_REG8(0x06fe), 0xcb},
+       {CCI_REG8(0x06ff), 0x40},
+       {CCI_REG8(0x0700), 0x72},
+       {CCI_REG8(0x0701), 0x00},
+       {CCI_REG8(0x0702), 0x5e},
+       {CCI_REG8(0x0703), 0x00},
+       {CCI_REG8(0x0704), 0x7a},
+       {CCI_REG8(0x0705), 0x00},
+       {CCI_REG8(0x0706), 0x63},
+       {CCI_REG8(0x0707), 0x00},
+       {CCI_REG8(0x0708), 0x32},
+       {CCI_REG8(0x0709), 0x40},
+       {CCI_REG8(0x070a), 0x30},
+       {CCI_REG8(0x070b), 0x40},
+       {CCI_REG8(0x070c), 0x3c},
+       {CCI_REG8(0x070d), 0x40},
+       {CCI_REG8(0x070e), 0x28},
+       {CCI_REG8(0x070f), 0x40},
+       {CCI_REG8(0x0710), 0x53},
+       {CCI_REG8(0x0711), 0x40},
+       {CCI_REG8(0x0712), 0x6d},
+       {CCI_REG8(0x0713), 0x40},
+       {CCI_REG8(0x0714), 0x66},
+       {CCI_REG8(0x0715), 0x40},
+       {CCI_REG8(0x0716), 0x57},
+       {CCI_REG8(0x0717), 0x40},
+       {CCI_REG8(0x0718), 0x5d},
+       {CCI_REG8(0x0719), 0x40},
+       {CCI_REG8(0x071a), 0x6f},
+       {CCI_REG8(0x071b), 0x40},
+       {CCI_REG8(0x071c), 0x71},
+       {CCI_REG8(0x071d), 0x40},
+       {CCI_REG8(0x071e), 0x69},
+       {CCI_REG8(0x071f), 0x40},
+       {CCI_REG8(0x0720), 0x6f},
+       {CCI_REG8(0x0721), 0x40},
+       {CCI_REG8(0x0722), 0x7a},
+       {CCI_REG8(0x0723), 0x40},
+       {CCI_REG8(0x0724), 0x71},
+       {CCI_REG8(0x0725), 0x40},
+       {CCI_REG8(0x0726), 0x70},
+       {CCI_REG8(0x0727), 0x40},
+       {CCI_REG8(0x0728), 0x7d},
+       {CCI_REG8(0x0729), 0x40},
+       {CCI_REG8(0x072a), 0x82},
+       {CCI_REG8(0x072b), 0x40},
+       {CCI_REG8(0x072c), 0x8a},
+       {CCI_REG8(0x072d), 0x40},
+       {CCI_REG8(0x072e), 0x7f},
+       {CCI_REG8(0x072f), 0x40},
+       {CCI_REG8(0x0730), 0x71},
+       {CCI_REG8(0x0731), 0x40},
+       {CCI_REG8(0x0732), 0x86},
+       {CCI_REG8(0x0733), 0x40},
+       {CCI_REG8(0x0734), 0x85},
+       {CCI_REG8(0x0735), 0x40},
+       {CCI_REG8(0x0736), 0x7b},
+       {CCI_REG8(0x0737), 0x40},
+       {CCI_REG8(0x0738), 0x42},
+       {CCI_REG8(0x0739), 0x40},
+       {CCI_REG8(0x073a), 0x49},
+       {CCI_REG8(0x073b), 0x40},
+       {CCI_REG8(0x073c), 0x48},
+       {CCI_REG8(0x073d), 0x40},
+       {CCI_REG8(0x073e), 0x47},
+       {CCI_REG8(0x073f), 0x40},
+       {CCI_REG8(0x0740), 0x2c},
+       {CCI_REG8(0x0741), 0x00},
+       {CCI_REG8(0x0742), 0x17},
+       {CCI_REG8(0x0743), 0x00},
+       {CCI_REG8(0x0744), 0x13},
+       {CCI_REG8(0x0745), 0x00},
+       {CCI_REG8(0x0746), 0x22},
+       {CCI_REG8(0x0747), 0x00},
+       {CCI_REG8(0x0748), 0x42},
+       {CCI_REG8(0x0749), 0x40},
+       {CCI_REG8(0x074a), 0x41},
+       {CCI_REG8(0x074b), 0x40},
+       {CCI_REG8(0x074c), 0x36},
+       {CCI_REG8(0x074d), 0x40},
+       {CCI_REG8(0x074e), 0x4c},
+       {CCI_REG8(0x074f), 0x40},
+       {CCI_REG8(0x0750), 0x65},
+       {CCI_REG8(0x0751), 0x40},
+       {CCI_REG8(0x0752), 0x80},
+       {CCI_REG8(0x0753), 0x40},
+       {CCI_REG8(0x0754), 0xaa},
+       {CCI_REG8(0x0755), 0x40},
+       {CCI_REG8(0x0756), 0x6c},
+       {CCI_REG8(0x0757), 0x40},
+       {CCI_REG8(0x0758), 0x16},
+       {CCI_REG8(0x0759), 0x41},
+       {CCI_REG8(0x075a), 0x3b},
+       {CCI_REG8(0x075b), 0x41},
+       {CCI_REG8(0x075c), 0x2c},
+       {CCI_REG8(0x075d), 0x41},
+       {CCI_REG8(0x075e), 0x2e},
+       {CCI_REG8(0x075f), 0x41},
+       {CCI_REG8(0x0760), 0x67},
+       {CCI_REG8(0x0761), 0x41},
+       {CCI_REG8(0x0762), 0x6c},
+       {CCI_REG8(0x0763), 0x41},
+       {CCI_REG8(0x0764), 0x81},
+       {CCI_REG8(0x0765), 0x41},
+       {CCI_REG8(0x0766), 0x7b},
+       {CCI_REG8(0x0767), 0x41},
+       {CCI_REG8(0x0768), 0x90},
+       {CCI_REG8(0x0769), 0x41},
+       {CCI_REG8(0x076a), 0x9d},
+       {CCI_REG8(0x076b), 0x41},
+       {CCI_REG8(0x076c), 0x8d},
+       {CCI_REG8(0x076d), 0x41},
+       {CCI_REG8(0x076e), 0x76},
+       {CCI_REG8(0x076f), 0x41},
+       {CCI_REG8(0x0770), 0x6f},
+       {CCI_REG8(0x0771), 0x41},
+       {CCI_REG8(0x0772), 0x7e},
+       {CCI_REG8(0x0773), 0x41},
+       {CCI_REG8(0x0774), 0x94},
+       {CCI_REG8(0x0775), 0x41},
+       {CCI_REG8(0x0776), 0x92},
+       {CCI_REG8(0x0777), 0x41},
+       {CCI_REG8(0x0778), 0x98},
+       {CCI_REG8(0x0779), 0x41},
+       {CCI_REG8(0x077a), 0xab},
+       {CCI_REG8(0x077b), 0x41},
+       {CCI_REG8(0x077c), 0x9b},
+       {CCI_REG8(0x077d), 0x41},
+       {CCI_REG8(0x077e), 0x9b},
+       {CCI_REG8(0x077f), 0x41},
+       {CCI_REG8(0x0780), 0x96},
+       {CCI_REG8(0x0781), 0x41},
+       {CCI_REG8(0x0782), 0xa4},
+       {CCI_REG8(0x0783), 0x41},
+       {CCI_REG8(0x0784), 0xab},
+       {CCI_REG8(0x0785), 0x41},
+       {CCI_REG8(0x0786), 0x96},
+       {CCI_REG8(0x0787), 0x41},
+       {CCI_REG8(0x0788), 0x85},
+       {CCI_REG8(0x0789), 0x41},
+       {CCI_REG8(0x078a), 0x94},
+       {CCI_REG8(0x078b), 0x41},
+       {CCI_REG8(0x078c), 0x9e},
+       {CCI_REG8(0x078d), 0x41},
+       {CCI_REG8(0x078e), 0x84},
+       {CCI_REG8(0x078f), 0x41},
+       {CCI_REG8(0x0790), 0x07},
+       {CCI_REG8(0x0791), 0x40},
+       {CCI_REG8(0x0792), 0x15},
+       {CCI_REG8(0x0793), 0x40},
+       {CCI_REG8(0x0794), 0x17},
+       {CCI_REG8(0x0795), 0x40},
+       {CCI_REG8(0x0798), 0x58},
+       {CCI_REG8(0x0799), 0x41},
+       {CCI_REG8(0x079a), 0x86},
+       {CCI_REG8(0x079b), 0x41},
+       {CCI_REG8(0x079c), 0xa1},
+       {CCI_REG8(0x079d), 0x41},
+       {CCI_REG8(0x079e), 0x6b},
+       {CCI_REG8(0x079f), 0x41},
+       {CCI_REG8(0x07f0), 0x12},
+       {CCI_REG8(0x07f1), 0x40},
+       {CCI_REG8(0x07f2), 0x44},
+       {CCI_REG8(0x07f3), 0x40},
+       {CCI_REG8(0x07f4), 0x55},
+       {CCI_REG8(0x07f5), 0x40},
+       {CCI_REG8(0x07f6), 0x16},
+       {CCI_REG8(0x07f7), 0x40},
+       {CCI_REG8(0x07f8), 0x42},
+       {CCI_REG8(0x07f9), 0x40},
+       {CCI_REG8(0x07fa), 0x4e},
+       {CCI_REG8(0x07fb), 0x40},
+       {CCI_REG8(0x07fc), 0x4d},
+       {CCI_REG8(0x07fd), 0x40},
+       {CCI_REG8(0x07fe), 0x42},
+       {CCI_REG8(0x07ff), 0x40},
+       {CCI_REG8(0x0800), 0x31},
+       {CCI_REG8(0x0801), 0x40},
+       {CCI_REG8(0x0802), 0x4b},
+       {CCI_REG8(0x0803), 0x40},
+       {CCI_REG8(0x0804), 0x48},
+       {CCI_REG8(0x0805), 0x40},
+       {CCI_REG8(0x0806), 0x30},
+       {CCI_REG8(0x0807), 0x40},
+       {CCI_REG8(0x0808), 0x3c},
+       {CCI_REG8(0x0809), 0x40},
+       {CCI_REG8(0x080a), 0x4e},
+       {CCI_REG8(0x080b), 0x40},
+       {CCI_REG8(0x080c), 0x46},
+       {CCI_REG8(0x080d), 0x40},
+       {CCI_REG8(0x080e), 0x3b},
+       {CCI_REG8(0x080f), 0x40},
+       {CCI_REG8(0x0810), 0x32},
+       {CCI_REG8(0x0811), 0x40},
+       {CCI_REG8(0x0812), 0x43},
+       {CCI_REG8(0x0813), 0x40},
+       {CCI_REG8(0x0814), 0x44},
+       {CCI_REG8(0x0815), 0x40},
+       {CCI_REG8(0x0816), 0x30},
+       {CCI_REG8(0x0817), 0x40},
+       {CCI_REG8(0x0818), 0x33},
+       {CCI_REG8(0x0819), 0x40},
+       {CCI_REG8(0x081a), 0x48},
+       {CCI_REG8(0x081b), 0x40},
+       {CCI_REG8(0x081c), 0x43},
+       {CCI_REG8(0x081d), 0x40},
+       {CCI_REG8(0x081e), 0x39},
+       {CCI_REG8(0x081f), 0x40},
+       {CCI_REG8(0x0820), 0x28},
+       {CCI_REG8(0x0821), 0x40},
+       {CCI_REG8(0x0822), 0x39},
+       {CCI_REG8(0x0823), 0x40},
+       {CCI_REG8(0x0824), 0x38},
+       {CCI_REG8(0x0825), 0x40},
+       {CCI_REG8(0x0826), 0x28},
+       {CCI_REG8(0x0827), 0x40},
+       {CCI_REG8(0x0828), 0x26},
+       {CCI_REG8(0x0829), 0x40},
+       {CCI_REG8(0x082a), 0x3c},
+       {CCI_REG8(0x082b), 0x40},
+       {CCI_REG8(0x082c), 0x3b},
+       {CCI_REG8(0x082d), 0x40},
+       {CCI_REG8(0x082e), 0x21},
+       {CCI_REG8(0x082f), 0x40},
+       {CCI_REG8(0x0830), 0x18},
+       {CCI_REG8(0x0831), 0x40},
+       {CCI_REG8(0x0832), 0x26},
+       {CCI_REG8(0x0833), 0x40},
+       {CCI_REG8(0x0834), 0x27},
+       {CCI_REG8(0x0835), 0x40},
+       {CCI_REG8(0x0836), 0x13},
+       {CCI_REG8(0x0837), 0x40},
+       {CCI_REG8(0x0838), 0x18},
+       {CCI_REG8(0x0839), 0x40},
+       {CCI_REG8(0x083a), 0x3d},
+       {CCI_REG8(0x083b), 0x40},
+       {CCI_REG8(0x083c), 0x42},
+       {CCI_REG8(0x083d), 0x40},
+       {CCI_REG8(0x083e), 0x2a},
+       {CCI_REG8(0x083f), 0x40},
+       {CCI_REG8(0x0840), 0x34},
+       {CCI_REG8(0x0841), 0x40},
+       {CCI_REG8(0x0842), 0x47},
+       {CCI_REG8(0x0843), 0x40},
+       {CCI_REG8(0x0844), 0x3e},
+       {CCI_REG8(0x0845), 0x40},
+       {CCI_REG8(0x0846), 0x33},
+       {CCI_REG8(0x0847), 0x40},
+       {CCI_REG8(0x0848), 0x4f},
+       {CCI_REG8(0x0849), 0x40},
+       {CCI_REG8(0x084a), 0x68},
+       {CCI_REG8(0x084b), 0x40},
+       {CCI_REG8(0x084c), 0x65},
+       {CCI_REG8(0x084d), 0x40},
+       {CCI_REG8(0x084e), 0x4a},
+       {CCI_REG8(0x084f), 0x40},
+       {CCI_REG8(0x0850), 0x62},
+       {CCI_REG8(0x0851), 0x40},
+       {CCI_REG8(0x0852), 0x73},
+       {CCI_REG8(0x0853), 0x40},
+       {CCI_REG8(0x0854), 0x71},
+       {CCI_REG8(0x0855), 0x40},
+       {CCI_REG8(0x0856), 0x5f},
+       {CCI_REG8(0x0857), 0x40},
+       {CCI_REG8(0x0858), 0x63},
+       {CCI_REG8(0x0859), 0x40},
+       {CCI_REG8(0x085a), 0x74},
+       {CCI_REG8(0x085b), 0x40},
+       {CCI_REG8(0x085c), 0x71},
+       {CCI_REG8(0x085d), 0x40},
+       {CCI_REG8(0x085e), 0x62},
+       {CCI_REG8(0x085f), 0x40},
+       {CCI_REG8(0x0860), 0x61},
+       {CCI_REG8(0x0861), 0x40},
+       {CCI_REG8(0x0862), 0x70},
+       {CCI_REG8(0x0863), 0x40},
+       {CCI_REG8(0x0864), 0x6d},
+       {CCI_REG8(0x0865), 0x40},
+       {CCI_REG8(0x0866), 0x5f},
+       {CCI_REG8(0x0867), 0x40},
+       {CCI_REG8(0x0868), 0x59},
+       {CCI_REG8(0x0869), 0x40},
+       {CCI_REG8(0x086a), 0x66},
+       {CCI_REG8(0x086b), 0x40},
+       {CCI_REG8(0x086c), 0x61},
+       {CCI_REG8(0x086d), 0x40},
+       {CCI_REG8(0x086e), 0x55},
+       {CCI_REG8(0x086f), 0x40},
+       {CCI_REG8(0x0870), 0x3e},
+       {CCI_REG8(0x0871), 0x40},
+       {CCI_REG8(0x0872), 0x51},
+       {CCI_REG8(0x0873), 0x40},
+       {CCI_REG8(0x0874), 0x4f},
+       {CCI_REG8(0x0875), 0x40},
+       {CCI_REG8(0x0876), 0x3d},
+       {CCI_REG8(0x0877), 0x40},
+       {CCI_REG8(0x0878), 0x27},
+       {CCI_REG8(0x0879), 0x40},
+       {CCI_REG8(0x087a), 0x37},
+       {CCI_REG8(0x087b), 0x40},
+       {CCI_REG8(0x087c), 0x34},
+       {CCI_REG8(0x087d), 0x40},
+       {CCI_REG8(0x087e), 0x26},
+       {CCI_REG8(0x087f), 0x40},
+       {CCI_REG8(0x0880), 0x1b},
+       {CCI_REG8(0x0881), 0x00},
+       {CCI_REG8(0x0882), 0x05},
+       {CCI_REG8(0x0883), 0x00},
+       {CCI_REG8(0x0884), 0x07},
+       {CCI_REG8(0x0885), 0x00},
+       {CCI_REG8(0x0886), 0x19},
+       {CCI_REG8(0x0887), 0x00},
+       {CCI_REG8(0x0888), 0x29},
+       {CCI_REG8(0x0889), 0x40},
+       {CCI_REG8(0x088a), 0x33},
+       {CCI_REG8(0x088b), 0x40},
+       {CCI_REG8(0x088c), 0x2e},
+       {CCI_REG8(0x088d), 0x40},
+       {CCI_REG8(0x088e), 0x21},
+       {CCI_REG8(0x088f), 0x40},
+       {CCI_REG8(0x0890), 0x33},
+       {CCI_REG8(0x0891), 0x40},
+       {CCI_REG8(0x0892), 0x4e},
+       {CCI_REG8(0x0893), 0x40},
+       {CCI_REG8(0x0894), 0x4f},
+       {CCI_REG8(0x0895), 0x40},
+       {CCI_REG8(0x0896), 0x30},
+       {CCI_REG8(0x0897), 0x40},
+       {CCI_REG8(0x0898), 0x4f},
+       {CCI_REG8(0x0899), 0x40},
+       {CCI_REG8(0x089a), 0x64},
+       {CCI_REG8(0x089b), 0x40},
+       {CCI_REG8(0x089c), 0x61},
+       {CCI_REG8(0x089d), 0x40},
+       {CCI_REG8(0x089e), 0x4b},
+       {CCI_REG8(0x089f), 0x40},
+       {CCI_REG8(0x08a0), 0x5a},
+       {CCI_REG8(0x08a1), 0x40},
+       {CCI_REG8(0x08a2), 0x6f},
+       {CCI_REG8(0x08a3), 0x40},
+       {CCI_REG8(0x08a4), 0x6b},
+       {CCI_REG8(0x08a5), 0x40},
+       {CCI_REG8(0x08a6), 0x58},
+       {CCI_REG8(0x08a7), 0x40},
+       {CCI_REG8(0x08a8), 0x60},
+       {CCI_REG8(0x08a9), 0x40},
+       {CCI_REG8(0x08aa), 0x71},
+       {CCI_REG8(0x08ab), 0x40},
+       {CCI_REG8(0x08ac), 0x6e},
+       {CCI_REG8(0x08ad), 0x40},
+       {CCI_REG8(0x08ae), 0x5e},
+       {CCI_REG8(0x08af), 0x40},
+       {CCI_REG8(0x08b0), 0x5d},
+       {CCI_REG8(0x08b1), 0x40},
+       {CCI_REG8(0x08b2), 0x6d},
+       {CCI_REG8(0x08b3), 0x40},
+       {CCI_REG8(0x08b4), 0x6a},
+       {CCI_REG8(0x08b5), 0x40},
+       {CCI_REG8(0x08b6), 0x5c},
+       {CCI_REG8(0x08b7), 0x40},
+       {CCI_REG8(0x08b8), 0x5b},
+       {CCI_REG8(0x08b9), 0x40},
+       {CCI_REG8(0x08ba), 0x6a},
+       {CCI_REG8(0x08bb), 0x40},
+       {CCI_REG8(0x08bc), 0x68},
+       {CCI_REG8(0x08bd), 0x40},
+       {CCI_REG8(0x08be), 0x59},
+       {CCI_REG8(0x08bf), 0x40},
+       {CCI_REG8(0x08c0), 0x4b},
+       {CCI_REG8(0x08c1), 0x40},
+       {CCI_REG8(0x08c2), 0x5a},
+       {CCI_REG8(0x08c3), 0x40},
+       {CCI_REG8(0x08c4), 0x57},
+       {CCI_REG8(0x08c5), 0x40},
+       {CCI_REG8(0x08c6), 0x46},
+       {CCI_REG8(0x08c7), 0x40},
+       {CCI_REG8(0x08c8), 0x35},
+       {CCI_REG8(0x08c9), 0x40},
+       {CCI_REG8(0x08ca), 0x47},
+       {CCI_REG8(0x08cb), 0x40},
+       {CCI_REG8(0x08cc), 0x45},
+       {CCI_REG8(0x08cd), 0x40},
+       {CCI_REG8(0x08ce), 0x35},
+       {CCI_REG8(0x08cf), 0x40},
+       {CCI_REG8(0x08d0), 0x14},
+       {CCI_REG8(0x08d1), 0x00},
+       {CCI_REG8(0x08d2), 0x01},
+       {CCI_REG8(0x08d3), 0x00},
+       {CCI_REG8(0x08d4), 0x04},
+       {CCI_REG8(0x08d5), 0x00},
+       {CCI_REG8(0x08d6), 0x19},
+       {CCI_REG8(0x08d7), 0x00},
+       {CCI_REG8(0x08d8), 0x2f},
+       {CCI_REG8(0x08d9), 0x40},
+       {CCI_REG8(0x08da), 0x43},
+       {CCI_REG8(0x08db), 0x40},
+       {CCI_REG8(0x08dc), 0x40},
+       {CCI_REG8(0x08dd), 0x40},
+       {CCI_REG8(0x08de), 0x35},
+       {CCI_REG8(0x08df), 0x40},
+       {CCI_REG8(0x08e0), 0x1f},
+       {CCI_REG8(0x08e1), 0x40},
+       {CCI_REG8(0x08e2), 0x34},
+       {CCI_REG8(0x08e3), 0x40},
+       {CCI_REG8(0x08e4), 0x2e},
+       {CCI_REG8(0x08e5), 0x40},
+       {CCI_REG8(0x08e6), 0x1b},
+       {CCI_REG8(0x08e7), 0x40},
+       {CCI_REG8(0x08e8), 0x32},
+       {CCI_REG8(0x08e9), 0x40},
+       {CCI_REG8(0x08ea), 0x46},
+       {CCI_REG8(0x08eb), 0x40},
+       {CCI_REG8(0x08ec), 0x45},
+       {CCI_REG8(0x08ed), 0x40},
+       {CCI_REG8(0x08ee), 0x2f},
+       {CCI_REG8(0x08ef), 0x40},
+       {CCI_REG8(0x08f0), 0x42},
+       {CCI_REG8(0x08f1), 0x40},
+       {CCI_REG8(0x08f2), 0x54},
+       {CCI_REG8(0x08f3), 0x40},
+       {CCI_REG8(0x08f4), 0x50},
+       {CCI_REG8(0x08f5), 0x40},
+       {CCI_REG8(0x08f6), 0x3e},
+       {CCI_REG8(0x08f7), 0x40},
+       {CCI_REG8(0x08f8), 0x48},
+       {CCI_REG8(0x08f9), 0x40},
+       {CCI_REG8(0x08fa), 0x57},
+       {CCI_REG8(0x08fb), 0x40},
+       {CCI_REG8(0x08fc), 0x54},
+       {CCI_REG8(0x08fd), 0x40},
+       {CCI_REG8(0x08fe), 0x46},
+       {CCI_REG8(0x08ff), 0x40},
+       {CCI_REG8(0x0900), 0x4d},
+       {CCI_REG8(0x0901), 0x40},
+       {CCI_REG8(0x0902), 0x59},
+       {CCI_REG8(0x0903), 0x40},
+       {CCI_REG8(0x0904), 0x55},
+       {CCI_REG8(0x0905), 0x40},
+       {CCI_REG8(0x0906), 0x49},
+       {CCI_REG8(0x0907), 0x40},
+       {CCI_REG8(0x0908), 0x45},
+       {CCI_REG8(0x0909), 0x40},
+       {CCI_REG8(0x090a), 0x51},
+       {CCI_REG8(0x090b), 0x40},
+       {CCI_REG8(0x090c), 0x4f},
+       {CCI_REG8(0x090d), 0x40},
+       {CCI_REG8(0x090e), 0x43},
+       {CCI_REG8(0x090f), 0x40},
+       {CCI_REG8(0x0910), 0x32},
+       {CCI_REG8(0x0911), 0x40},
+       {CCI_REG8(0x0912), 0x45},
+       {CCI_REG8(0x0913), 0x40},
+       {CCI_REG8(0x0914), 0x3f},
+       {CCI_REG8(0x0915), 0x40},
+       {CCI_REG8(0x0916), 0x30},
+       {CCI_REG8(0x0917), 0x40},
+       {CCI_REG8(0x0918), 0x23},
+       {CCI_REG8(0x0919), 0x40},
+       {CCI_REG8(0x091a), 0x32},
+       {CCI_REG8(0x091b), 0x40},
+       {CCI_REG8(0x091c), 0x31},
+       {CCI_REG8(0x091d), 0x40},
+       {CCI_REG8(0x091e), 0x1e},
+       {CCI_REG8(0x091f), 0x40},
+       {CCI_REG8(0x0920), 0x28},
+       {CCI_REG8(0x0921), 0x00},
+       {CCI_REG8(0x0922), 0x13},
+       {CCI_REG8(0x0923), 0x00},
+       {CCI_REG8(0x0924), 0x15},
+       {CCI_REG8(0x0925), 0x00},
+       {CCI_REG8(0x0926), 0x24},
+       {CCI_REG8(0x0927), 0x00},
+       {CCI_REG8(0x0928), 0x22},
+       {CCI_REG8(0x0929), 0x40},
+       {CCI_REG8(0x092a), 0x2e},
+       {CCI_REG8(0x092b), 0x40},
+       {CCI_REG8(0x092c), 0x2e},
+       {CCI_REG8(0x092d), 0x40},
+       {CCI_REG8(0x092e), 0x1e},
+       {CCI_REG8(0x092f), 0x40},
+       {CCI_REG8(0x0930), 0x05},
+       {CCI_REG8(0x0931), 0x00},
+       {CCI_REG8(0x0932), 0x10},
+       {CCI_REG8(0x0933), 0x40},
+       {CCI_REG8(0x0934), 0x13},
+       {CCI_REG8(0x0935), 0x40},
+       {CCI_REG8(0x0936), 0x07},
+       {CCI_REG8(0x0937), 0x00},
+       {CCI_REG8(0x0938), 0x2e},
+       {CCI_REG8(0x0939), 0x40},
+       {CCI_REG8(0x093a), 0x40},
+       {CCI_REG8(0x093b), 0x40},
+       {CCI_REG8(0x093c), 0x3c},
+       {CCI_REG8(0x093d), 0x40},
+       {CCI_REG8(0x093e), 0x2a},
+       {CCI_REG8(0x093f), 0x40},
+       {CCI_REG8(0x0940), 0x41},
+       {CCI_REG8(0x0941), 0x40},
+       {CCI_REG8(0x0942), 0x4f},
+       {CCI_REG8(0x0943), 0x40},
+       {CCI_REG8(0x0944), 0x4d},
+       {CCI_REG8(0x0945), 0x40},
+       {CCI_REG8(0x0946), 0x40},
+       {CCI_REG8(0x0947), 0x40},
+       {CCI_REG8(0x0948), 0x48},
+       {CCI_REG8(0x0949), 0x40},
+       {CCI_REG8(0x094a), 0x55},
+       {CCI_REG8(0x094b), 0x40},
+       {CCI_REG8(0x094c), 0x52},
+       {CCI_REG8(0x094d), 0x40},
+       {CCI_REG8(0x094e), 0x45},
+       {CCI_REG8(0x094f), 0x40},
+       {CCI_REG8(0x0950), 0x42},
+       {CCI_REG8(0x0951), 0x40},
+       {CCI_REG8(0x0952), 0x4f},
+       {CCI_REG8(0x0953), 0x40},
+       {CCI_REG8(0x0954), 0x4c},
+       {CCI_REG8(0x0955), 0x40},
+       {CCI_REG8(0x0956), 0x41},
+       {CCI_REG8(0x0957), 0x40},
+       {CCI_REG8(0x0958), 0x44},
+       {CCI_REG8(0x0959), 0x40},
+       {CCI_REG8(0x095a), 0x4d},
+       {CCI_REG8(0x095b), 0x40},
+       {CCI_REG8(0x095c), 0x49},
+       {CCI_REG8(0x095d), 0x40},
+       {CCI_REG8(0x095e), 0x40},
+       {CCI_REG8(0x095f), 0x40},
+       {CCI_REG8(0x0960), 0x31},
+       {CCI_REG8(0x0961), 0x40},
+       {CCI_REG8(0x0962), 0x3e},
+       {CCI_REG8(0x0963), 0x40},
+       {CCI_REG8(0x0964), 0x3c},
+       {CCI_REG8(0x0965), 0x40},
+       {CCI_REG8(0x0966), 0x30},
+       {CCI_REG8(0x0967), 0x40},
+       {CCI_REG8(0x0968), 0x23},
+       {CCI_REG8(0x0969), 0x40},
+       {CCI_REG8(0x096a), 0x32},
+       {CCI_REG8(0x096b), 0x40},
+       {CCI_REG8(0x096c), 0x2f},
+       {CCI_REG8(0x096d), 0x40},
+       {CCI_REG8(0x096e), 0x24},
+       {CCI_REG8(0x096f), 0x40},
+       {CCI_REG8(0x0970), 0x26},
+       {CCI_REG8(0x0971), 0x00},
+       {CCI_REG8(0x0972), 0x17},
+       {CCI_REG8(0x0973), 0x00},
+       {CCI_REG8(0x0974), 0x18},
+       {CCI_REG8(0x0975), 0x00},
+       {CCI_REG8(0x0976), 0x29},
+       {CCI_REG8(0x0977), 0x00},
+       {CCI_REG8(0x0978), 0x23},
+       {CCI_REG8(0x0979), 0x40},
+       {CCI_REG8(0x097a), 0x30},
+       {CCI_REG8(0x097b), 0x40},
+       {CCI_REG8(0x097c), 0x2e},
+       {CCI_REG8(0x097d), 0x40},
+       {CCI_REG8(0x097e), 0x22},
+       {CCI_REG8(0x097f), 0x40},
+       {CCI_REG8(0x0980), 0x19},
+       {CCI_REG8(0x0981), 0x00},
+       {CCI_REG8(0x0982), 0x0e},
+       {CCI_REG8(0x0983), 0x00},
+       {CCI_REG8(0x0984), 0x16},
+       {CCI_REG8(0x0985), 0x00},
+       {CCI_REG8(0x0986), 0x29},
+       {CCI_REG8(0x0987), 0x00},
+       {CCI_REG8(0x0988), 0x15},
+       {CCI_REG8(0x0989), 0x40},
+       {CCI_REG8(0x098a), 0x2c},
+       {CCI_REG8(0x098b), 0x40},
+       {CCI_REG8(0x098c), 0x27},
+       {CCI_REG8(0x098d), 0x40},
+       {CCI_REG8(0x098e), 0x17},
+       {CCI_REG8(0x098f), 0x40},
+       {CCI_REG8(0x0990), 0x33},
+       {CCI_REG8(0x0991), 0x40},
+       {CCI_REG8(0x0992), 0x40},
+       {CCI_REG8(0x0993), 0x40},
+       {CCI_REG8(0x0994), 0x3c},
+       {CCI_REG8(0x0995), 0x40},
+       {CCI_REG8(0x0996), 0x2e},
+       {CCI_REG8(0x0997), 0x40},
+       {CCI_REG8(0x0998), 0x3a},
+       {CCI_REG8(0x0999), 0x40},
+       {CCI_REG8(0x099a), 0x46},
+       {CCI_REG8(0x099b), 0x40},
+       {CCI_REG8(0x099c), 0x41},
+       {CCI_REG8(0x099d), 0x40},
+       {CCI_REG8(0x099e), 0x38},
+       {CCI_REG8(0x099f), 0x40},
+       {CCI_REG8(0x09a0), 0x3c},
+       {CCI_REG8(0x09a1), 0x40},
+       {CCI_REG8(0x09a2), 0x44},
+       {CCI_REG8(0x09a3), 0x40},
+       {CCI_REG8(0x09a4), 0x41},
+       {CCI_REG8(0x09a5), 0x40},
+       {CCI_REG8(0x09a6), 0x37},
+       {CCI_REG8(0x09a7), 0x40},
+       {CCI_REG8(0x09a8), 0x39},
+       {CCI_REG8(0x09a9), 0x40},
+       {CCI_REG8(0x09aa), 0x42},
+       {CCI_REG8(0x09ab), 0x40},
+       {CCI_REG8(0x09ac), 0x3f},
+       {CCI_REG8(0x09ad), 0x40},
+       {CCI_REG8(0x09ae), 0x35},
+       {CCI_REG8(0x09af), 0x40},
+       {CCI_REG8(0x09b0), 0x29},
+       {CCI_REG8(0x09b1), 0x40},
+       {CCI_REG8(0x09b2), 0x35},
+       {CCI_REG8(0x09b3), 0x40},
+       {CCI_REG8(0x09b4), 0x30},
+       {CCI_REG8(0x09b5), 0x40},
+       {CCI_REG8(0x09b6), 0x27},
+       {CCI_REG8(0x09b7), 0x40},
+       {CCI_REG8(0x09b8), 0x15},
+       {CCI_REG8(0x09b9), 0x40},
+       {CCI_REG8(0x09ba), 0x21},
+       {CCI_REG8(0x09bb), 0x40},
+       {CCI_REG8(0x09bc), 0x1d},
+       {CCI_REG8(0x09bd), 0x40},
+       {CCI_REG8(0x09be), 0x10},
+       {CCI_REG8(0x09bf), 0x40},
+       {CCI_REG8(0x09c0), 0x30},
+       {CCI_REG8(0x09c1), 0x00},
+       {CCI_REG8(0x09c2), 0x22},
+       {CCI_REG8(0x09c3), 0x00},
+       {CCI_REG8(0x09c4), 0x25},
+       {CCI_REG8(0x09c5), 0x00},
+       {CCI_REG8(0x09c6), 0x2d},
+       {CCI_REG8(0x09c7), 0x00},
+       {CCI_REG8(0x09c8), 0x16},
+       {CCI_REG8(0x09c9), 0x40},
+       {CCI_REG8(0x09ca), 0x23},
+       {CCI_REG8(0x09cb), 0x40},
+       {CCI_REG8(0x09cc), 0x17},
+       {CCI_REG8(0x09cd), 0x40},
+       {CCI_REG8(0x09ce), 0x0e},
+       {CCI_REG8(0x09cf), 0x40},
+       {CCI_REG8(0x09d0), 0x10},
+       {CCI_REG8(0x09d1), 0x40},
+       {CCI_REG8(0x09d2), 0x43},
+       {CCI_REG8(0x09d3), 0x40},
+       {CCI_REG8(0x09d4), 0x41},
+       {CCI_REG8(0x09d5), 0x40},
+       {CCI_REG8(0x09d6), 0x34},
+       {CCI_REG8(0x09d7), 0x40},
+       {CCI_REG8(0x09d8), 0x4e},
+       {CCI_REG8(0x09d9), 0x40},
+       {CCI_REG8(0x09da), 0x55},
+       {CCI_REG8(0x09db), 0x40},
+       {CCI_REG8(0x09dc), 0x58},
+       {CCI_REG8(0x09dd), 0x40},
+       {CCI_REG8(0x09de), 0x3c},
+       {CCI_REG8(0x09df), 0x40},
+       {CCI_REG8(0x09e0), 0x51},
+       {CCI_REG8(0x09e1), 0x40},
+       {CCI_REG8(0x09e2), 0x66},
+       {CCI_REG8(0x09e3), 0x40},
+       {CCI_REG8(0x09e4), 0x64},
+       {CCI_REG8(0x09e5), 0x40},
+       {CCI_REG8(0x09e6), 0x59},
+       {CCI_REG8(0x09e7), 0x40},
+       {CCI_REG8(0x09e8), 0x5d},
+       {CCI_REG8(0x09e9), 0x40},
+       {CCI_REG8(0x09ea), 0x68},
+       {CCI_REG8(0x09eb), 0x40},
+       {CCI_REG8(0x09ec), 0x6c},
+       {CCI_REG8(0x09ed), 0x40},
+       {CCI_REG8(0x09ee), 0x56},
+       {CCI_REG8(0x09ef), 0x40},
+       {CCI_REG8(0x09f0), 0x4a},
+       {CCI_REG8(0x09f1), 0x40},
+       {CCI_REG8(0x09f2), 0x62},
+       {CCI_REG8(0x09f3), 0x40},
+       {CCI_REG8(0x09f4), 0x59},
+       {CCI_REG8(0x09f5), 0x40},
+       {CCI_REG8(0x09f6), 0x4f},
+       {CCI_REG8(0x09f7), 0x40},
+       {CCI_REG8(0x09f8), 0x56},
+       {CCI_REG8(0x09f9), 0x40},
+       {CCI_REG8(0x09fa), 0x60},
+       {CCI_REG8(0x09fb), 0x40},
+       {CCI_REG8(0x09fc), 0x61},
+       {CCI_REG8(0x09fd), 0x40},
+       {CCI_REG8(0x09fe), 0x53},
+       {CCI_REG8(0x09ff), 0x40},
+       {CCI_REG8(0x0a00), 0x3e},
+       {CCI_REG8(0x0a01), 0x40},
+       {CCI_REG8(0x0a02), 0x4d},
+       {CCI_REG8(0x0a03), 0x40},
+       {CCI_REG8(0x0a04), 0x4b},
+       {CCI_REG8(0x0a05), 0x40},
+       {CCI_REG8(0x0a06), 0x44},
+       {CCI_REG8(0x0a07), 0x40},
+       {CCI_REG8(0x0a08), 0x34},
+       {CCI_REG8(0x0a09), 0x40},
+       {CCI_REG8(0x0a0a), 0x46},
+       {CCI_REG8(0x0a0b), 0x40},
+       {CCI_REG8(0x0a0c), 0x48},
+       {CCI_REG8(0x0a0d), 0x40},
+       {CCI_REG8(0x0a0e), 0x3a},
+       {CCI_REG8(0x0a0f), 0x40},
+       {CCI_REG8(0x0a10), 0x1c},
+       {CCI_REG8(0x0a11), 0x00},
+       {CCI_REG8(0x0a12), 0x06},
+       {CCI_REG8(0x0a13), 0x00},
+       {CCI_REG8(0x0a14), 0x09},
+       {CCI_REG8(0x0a15), 0x00},
+       {CCI_REG8(0x0a16), 0x25},
+       {CCI_REG8(0x0a17), 0x00},
+       {CCI_REG8(0x0a18), 0x32},
+       {CCI_REG8(0x0a19), 0x40},
+       {CCI_REG8(0x0a1a), 0x45},
+       {CCI_REG8(0x0a1b), 0x40},
+       {CCI_REG8(0x0a1c), 0x51},
+       {CCI_REG8(0x0a1d), 0x40},
+       {CCI_REG8(0x0a1e), 0x36},
+       {CCI_REG8(0x0a1f), 0x40},
+       {CCI_REG8(0x0a70), 0x29},
+       {CCI_REG8(0x0a71), 0x00},
+       {CCI_REG8(0x0a72), 0x28},
+       {CCI_REG8(0x0a73), 0x00},
+       {CCI_REG8(0x0a74), 0x16},
+       {CCI_REG8(0x0a75), 0x00},
+       {CCI_REG8(0x0a76), 0x27},
+       {CCI_REG8(0x0a77), 0x00},
+       {CCI_REG8(0x0a78), 0x11},
+       {CCI_REG8(0x0a79), 0x00},
+       {CCI_REG8(0x0a7a), 0x18},
+       {CCI_REG8(0x0a7b), 0x00},
+       {CCI_REG8(0x0a7c), 0x11},
+       {CCI_REG8(0x0a7d), 0x00},
+       {CCI_REG8(0x0a7e), 0x10},
+       {CCI_REG8(0x0a7f), 0x00},
+       {CCI_REG8(0x0a80), 0x11},
+       {CCI_REG8(0x0a81), 0x00},
+       {CCI_REG8(0x0a82), 0x19},
+       {CCI_REG8(0x0a83), 0x00},
+       {CCI_REG8(0x0a84), 0x10},
+       {CCI_REG8(0x0a85), 0x00},
+       {CCI_REG8(0x0a86), 0x0d},
+       {CCI_REG8(0x0a87), 0x00},
+       {CCI_REG8(0x0a88), 0x08},
+       {CCI_REG8(0x0a89), 0x00},
+       {CCI_REG8(0x0a8a), 0x10},
+       {CCI_REG8(0x0a8b), 0x00},
+       {CCI_REG8(0x0a8c), 0x08},
+       {CCI_REG8(0x0a8d), 0x00},
+       {CCI_REG8(0x0a8e), 0x03},
+       {CCI_REG8(0x0a8f), 0x00},
+       {CCI_REG8(0x0a90), 0x04},
+       {CCI_REG8(0x0a91), 0x40},
+       {CCI_REG8(0x0a92), 0x09},
+       {CCI_REG8(0x0a93), 0x00},
+       {CCI_REG8(0x0a96), 0x03},
+       {CCI_REG8(0x0a97), 0x40},
+       {CCI_REG8(0x0a98), 0x06},
+       {CCI_REG8(0x0a99), 0x40},
+       {CCI_REG8(0x0a9a), 0x08},
+       {CCI_REG8(0x0a9b), 0x00},
+       {CCI_REG8(0x0a9e), 0x08},
+       {CCI_REG8(0x0a9f), 0x40},
+       {CCI_REG8(0x0aa0), 0x02},
+       {CCI_REG8(0x0aa1), 0x00},
+       {CCI_REG8(0x0aa2), 0x0b},
+       {CCI_REG8(0x0aa3), 0x00},
+       {CCI_REG8(0x0aa4), 0x02},
+       {CCI_REG8(0x0aa5), 0x00},
+       {CCI_REG8(0x0aa6), 0x01},
+       {CCI_REG8(0x0aa7), 0x00},
+       {CCI_REG8(0x0aa8), 0x02},
+       {CCI_REG8(0x0aa9), 0x00},
+       {CCI_REG8(0x0aaa), 0x0e},
+       {CCI_REG8(0x0aab), 0x00},
+       {CCI_REG8(0x0aac), 0x06},
+       {CCI_REG8(0x0aad), 0x00},
+       {CCI_REG8(0x0aae), 0x02},
+       {CCI_REG8(0x0aaf), 0x00},
+       {CCI_REG8(0x0ab0), 0x08},
+       {CCI_REG8(0x0ab1), 0x00},
+       {CCI_REG8(0x0ab2), 0x15},
+       {CCI_REG8(0x0ab3), 0x00},
+       {CCI_REG8(0x0ab4), 0x0a},
+       {CCI_REG8(0x0ab5), 0x00},
+       {CCI_REG8(0x0ab6), 0x07},
+       {CCI_REG8(0x0ab7), 0x00},
+       {CCI_REG8(0x0ab8), 0x02},
+       {CCI_REG8(0x0ab9), 0x00},
+       {CCI_REG8(0x0aba), 0x12},
+       {CCI_REG8(0x0abb), 0x00},
+       {CCI_REG8(0x0abc), 0x09},
+       {CCI_REG8(0x0abd), 0x00},
+       {CCI_REG8(0x0abe), 0x06},
+       {CCI_REG8(0x0abf), 0x00},
+       {CCI_REG8(0x0ac0), 0x25},
+       {CCI_REG8(0x0ac1), 0x00},
+       {CCI_REG8(0x0ac2), 0x2c},
+       {CCI_REG8(0x0ac3), 0x00},
+       {CCI_REG8(0x0ac4), 0x22},
+       {CCI_REG8(0x0ac5), 0x00},
+       {CCI_REG8(0x0ac6), 0x20},
+       {CCI_REG8(0x0ac7), 0x00},
+       {CCI_REG8(0x0ac8), 0x18},
+       {CCI_REG8(0x0ac9), 0x00},
+       {CCI_REG8(0x0aca), 0x26},
+       {CCI_REG8(0x0acb), 0x00},
+       {CCI_REG8(0x0acc), 0x1b},
+       {CCI_REG8(0x0acd), 0x00},
+       {CCI_REG8(0x0ace), 0x19},
+       {CCI_REG8(0x0acf), 0x00},
+       {CCI_REG8(0x0ad0), 0x15},
+       {CCI_REG8(0x0ad1), 0x00},
+       {CCI_REG8(0x0ad2), 0x23},
+       {CCI_REG8(0x0ad3), 0x00},
+       {CCI_REG8(0x0ad4), 0x18},
+       {CCI_REG8(0x0ad5), 0x00},
+       {CCI_REG8(0x0ad6), 0x14},
+       {CCI_REG8(0x0ad7), 0x00},
+       {CCI_REG8(0x0ad8), 0x0e},
+       {CCI_REG8(0x0ad9), 0x00},
+       {CCI_REG8(0x0ada), 0x1c},
+       {CCI_REG8(0x0adb), 0x00},
+       {CCI_REG8(0x0adc), 0x13},
+       {CCI_REG8(0x0add), 0x00},
+       {CCI_REG8(0x0ade), 0x0f},
+       {CCI_REG8(0x0adf), 0x00},
+       {CCI_REG8(0x0ae0), 0x07},
+       {CCI_REG8(0x0ae1), 0x00},
+       {CCI_REG8(0x0ae2), 0x17},
+       {CCI_REG8(0x0ae3), 0x00},
+       {CCI_REG8(0x0ae4), 0x0c},
+       {CCI_REG8(0x0ae5), 0x00},
+       {CCI_REG8(0x0ae6), 0x07},
+       {CCI_REG8(0x0ae7), 0x00},
+       {CCI_REG8(0x0ae8), 0x04},
+       {CCI_REG8(0x0ae9), 0x00},
+       {CCI_REG8(0x0aea), 0x16},
+       {CCI_REG8(0x0aeb), 0x00},
+       {CCI_REG8(0x0aec), 0x0b},
+       {CCI_REG8(0x0aed), 0x00},
+       {CCI_REG8(0x0aee), 0x04},
+       {CCI_REG8(0x0aef), 0x00},
+       {CCI_REG8(0x0af0), 0x06},
+       {CCI_REG8(0x0af1), 0x00},
+       {CCI_REG8(0x0af2), 0x17},
+       {CCI_REG8(0x0af3), 0x00},
+       {CCI_REG8(0x0af4), 0x0d},
+       {CCI_REG8(0x0af5), 0x00},
+       {CCI_REG8(0x0af6), 0x06},
+       {CCI_REG8(0x0af7), 0x00},
+       {CCI_REG8(0x0af8), 0x08},
+       {CCI_REG8(0x0af9), 0x00},
+       {CCI_REG8(0x0afa), 0x1b},
+       {CCI_REG8(0x0afb), 0x00},
+       {CCI_REG8(0x0afc), 0x10},
+       {CCI_REG8(0x0afd), 0x00},
+       {CCI_REG8(0x0afe), 0x08},
+       {CCI_REG8(0x0aff), 0x00},
+       {CCI_REG8(0x0b00), 0x11},
+       {CCI_REG8(0x0b01), 0x00},
+       {CCI_REG8(0x0b02), 0x21},
+       {CCI_REG8(0x0b03), 0x00},
+       {CCI_REG8(0x0b04), 0x16},
+       {CCI_REG8(0x0b05), 0x00},
+       {CCI_REG8(0x0b06), 0x0f},
+       {CCI_REG8(0x0b07), 0x00},
+       {CCI_REG8(0x0b08), 0x07},
+       {CCI_REG8(0x0b09), 0x00},
+       {CCI_REG8(0x0b0a), 0x1a},
+       {CCI_REG8(0x0b0b), 0x00},
+       {CCI_REG8(0x0b0c), 0x0f},
+       {CCI_REG8(0x0b0d), 0x00},
+       {CCI_REG8(0x0b0e), 0x07},
+       {CCI_REG8(0x0b0f), 0x00},
+       {CCI_REG8(0x0b10), 0x15},
+       {CCI_REG8(0x0b11), 0x00},
+       {CCI_REG8(0x0b12), 0x1f},
+       {CCI_REG8(0x0b13), 0x00},
+       {CCI_REG8(0x0b14), 0x17},
+       {CCI_REG8(0x0b15), 0x00},
+       {CCI_REG8(0x0b16), 0x15},
+       {CCI_REG8(0x0b17), 0x00},
+       {CCI_REG8(0x0b18), 0x12},
+       {CCI_REG8(0x0b19), 0x00},
+       {CCI_REG8(0x0b1a), 0x1d},
+       {CCI_REG8(0x0b1b), 0x00},
+       {CCI_REG8(0x0b1c), 0x13},
+       {CCI_REG8(0x0b1d), 0x00},
+       {CCI_REG8(0x0b1e), 0x0f},
+       {CCI_REG8(0x0b1f), 0x00},
+       {CCI_REG8(0x0b20), 0x10},
+       {CCI_REG8(0x0b21), 0x00},
+       {CCI_REG8(0x0b22), 0x1c},
+       {CCI_REG8(0x0b23), 0x00},
+       {CCI_REG8(0x0b24), 0x13},
+       {CCI_REG8(0x0b25), 0x00},
+       {CCI_REG8(0x0b26), 0x0e},
+       {CCI_REG8(0x0b27), 0x00},
+       {CCI_REG8(0x0b28), 0x0a},
+       {CCI_REG8(0x0b29), 0x00},
+       {CCI_REG8(0x0b2a), 0x17},
+       {CCI_REG8(0x0b2b), 0x00},
+       {CCI_REG8(0x0b2c), 0x0d},
+       {CCI_REG8(0x0b2d), 0x00},
+       {CCI_REG8(0x0b2e), 0x07},
+       {CCI_REG8(0x0b2f), 0x00},
+       {CCI_REG8(0x0b30), 0x02},
+       {CCI_REG8(0x0b31), 0x00},
+       {CCI_REG8(0x0b32), 0x11},
+       {CCI_REG8(0x0b33), 0x00},
+       {CCI_REG8(0x0b34), 0x07},
+       {CCI_REG8(0x0b35), 0x00},
+       {CCI_REG8(0x0b36), 0x00},
+       {CCI_REG8(0x0b37), 0x40},
+       {CCI_REG8(0x0b38), 0x01},
+       {CCI_REG8(0x0b39), 0x40},
+       {CCI_REG8(0x0b3a), 0x10},
+       {CCI_REG8(0x0b3b), 0x00},
+       {CCI_REG8(0x0b3c), 0x06},
+       {CCI_REG8(0x0b3d), 0x00},
+       {CCI_REG8(0x0b3e), 0x03},
+       {CCI_REG8(0x0b3f), 0x40},
+       {CCI_REG8(0x0b40), 0x03},
+       {CCI_REG8(0x0b41), 0x00},
+       {CCI_REG8(0x0b42), 0x12},
+       {CCI_REG8(0x0b43), 0x00},
+       {CCI_REG8(0x0b44), 0x07},
+       {CCI_REG8(0x0b45), 0x00},
+       {CCI_REG8(0x0b46), 0x01},
+       {CCI_REG8(0x0b47), 0x00},
+       {CCI_REG8(0x0b48), 0x04},
+       {CCI_REG8(0x0b49), 0x00},
+       {CCI_REG8(0x0b4a), 0x15},
+       {CCI_REG8(0x0b4b), 0x00},
+       {CCI_REG8(0x0b4c), 0x0a},
+       {CCI_REG8(0x0b4d), 0x00},
+       {CCI_REG8(0x0b4e), 0x01},
+       {CCI_REG8(0x0b4f), 0x00},
+       {CCI_REG8(0x0b50), 0x09},
+       {CCI_REG8(0x0b51), 0x00},
+       {CCI_REG8(0x0b52), 0x1b},
+       {CCI_REG8(0x0b53), 0x00},
+       {CCI_REG8(0x0b54), 0x0e},
+       {CCI_REG8(0x0b55), 0x00},
+       {CCI_REG8(0x0b56), 0x07},
+       {CCI_REG8(0x0b57), 0x00},
+       {CCI_REG8(0x0b58), 0x04},
+       {CCI_REG8(0x0b59), 0x00},
+       {CCI_REG8(0x0b5a), 0x15},
+       {CCI_REG8(0x0b5b), 0x00},
+       {CCI_REG8(0x0b5c), 0x0b},
+       {CCI_REG8(0x0b5d), 0x00},
+       {CCI_REG8(0x0b5e), 0x01},
+       {CCI_REG8(0x0b5f), 0x00},
+       {CCI_REG8(0x0b60), 0x0a},
+       {CCI_REG8(0x0b61), 0x00},
+       {CCI_REG8(0x0b62), 0x1b},
+       {CCI_REG8(0x0b63), 0x00},
+       {CCI_REG8(0x0b64), 0x0d},
+       {CCI_REG8(0x0b65), 0x00},
+       {CCI_REG8(0x0b66), 0x09},
+       {CCI_REG8(0x0b67), 0x00},
+       {CCI_REG8(0x0b68), 0x09},
+       {CCI_REG8(0x0b69), 0x00},
+       {CCI_REG8(0x0b6a), 0x18},
+       {CCI_REG8(0x0b6b), 0x00},
+       {CCI_REG8(0x0b6c), 0x0d},
+       {CCI_REG8(0x0b6d), 0x00},
+       {CCI_REG8(0x0b6e), 0x0a},
+       {CCI_REG8(0x0b6f), 0x00},
+       {CCI_REG8(0x0b70), 0x0b},
+       {CCI_REG8(0x0b71), 0x00},
+       {CCI_REG8(0x0b72), 0x1a},
+       {CCI_REG8(0x0b73), 0x00},
+       {CCI_REG8(0x0b74), 0x10},
+       {CCI_REG8(0x0b75), 0x00},
+       {CCI_REG8(0x0b76), 0x0b},
+       {CCI_REG8(0x0b77), 0x00},
+       {CCI_REG8(0x0b78), 0x07},
+       {CCI_REG8(0x0b79), 0x00},
+       {CCI_REG8(0x0b7a), 0x16},
+       {CCI_REG8(0x0b7b), 0x00},
+       {CCI_REG8(0x0b7c), 0x0c},
+       {CCI_REG8(0x0b7d), 0x00},
+       {CCI_REG8(0x0b7e), 0x07},
+       {CCI_REG8(0x0b7f), 0x00},
+       {CCI_REG8(0x0b80), 0x01},
+       {CCI_REG8(0x0b81), 0x40},
+       {CCI_REG8(0x0b82), 0x11},
+       {CCI_REG8(0x0b83), 0x00},
+       {CCI_REG8(0x0b84), 0x07},
+       {CCI_REG8(0x0b85), 0x00},
+       {CCI_REG8(0x0b88), 0x02},
+       {CCI_REG8(0x0b89), 0x40},
+       {CCI_REG8(0x0b8a), 0x12},
+       {CCI_REG8(0x0b8b), 0x00},
+       {CCI_REG8(0x0b8c), 0x08},
+       {CCI_REG8(0x0b8d), 0x00},
+       {CCI_REG8(0x0b8e), 0x01},
+       {CCI_REG8(0x0b8f), 0x40},
+       {CCI_REG8(0x0b90), 0x03},
+       {CCI_REG8(0x0b91), 0x00},
+       {CCI_REG8(0x0b92), 0x14},
+       {CCI_REG8(0x0b93), 0x00},
+       {CCI_REG8(0x0b94), 0x09},
+       {CCI_REG8(0x0b95), 0x00},
+       {CCI_REG8(0x0b96), 0x02},
+       {CCI_REG8(0x0b97), 0x00},
+       {CCI_REG8(0x0b98), 0x02},
+       {CCI_REG8(0x0b99), 0x00},
+       {CCI_REG8(0x0b9a), 0x16},
+       {CCI_REG8(0x0b9b), 0x00},
+       {CCI_REG8(0x0b9c), 0x0b},
+       {CCI_REG8(0x0b9d), 0x00},
+       {CCI_REG8(0x0b9e), 0x01},
+       {CCI_REG8(0x0b9f), 0x00},
+       {CCI_REG8(0x0ba0), 0x07},
+       {CCI_REG8(0x0ba1), 0x00},
+       {CCI_REG8(0x0ba2), 0x1a},
+       {CCI_REG8(0x0ba3), 0x00},
+       {CCI_REG8(0x0ba4), 0x0f},
+       {CCI_REG8(0x0ba5), 0x00},
+       {CCI_REG8(0x0ba6), 0x06},
+       {CCI_REG8(0x0ba7), 0x00},
+       {CCI_REG8(0x0ba8), 0x02},
+       {CCI_REG8(0x0ba9), 0x00},
+       {CCI_REG8(0x0baa), 0x16},
+       {CCI_REG8(0x0bab), 0x00},
+       {CCI_REG8(0x0bac), 0x0b},
+       {CCI_REG8(0x0bad), 0x00},
+       {CCI_REG8(0x0bae), 0x01},
+       {CCI_REG8(0x0baf), 0x40},
+       {CCI_REG8(0x0bb0), 0x16},
+       {CCI_REG8(0x0bb1), 0x00},
+       {CCI_REG8(0x0bb2), 0x20},
+       {CCI_REG8(0x0bb3), 0x00},
+       {CCI_REG8(0x0bb4), 0x10},
+       {CCI_REG8(0x0bb5), 0x00},
+       {CCI_REG8(0x0bb6), 0x10},
+       {CCI_REG8(0x0bb7), 0x00},
+       {CCI_REG8(0x0bb8), 0x13},
+       {CCI_REG8(0x0bb9), 0x00},
+       {CCI_REG8(0x0bba), 0x20},
+       {CCI_REG8(0x0bbb), 0x00},
+       {CCI_REG8(0x0bbc), 0x16},
+       {CCI_REG8(0x0bbd), 0x00},
+       {CCI_REG8(0x0bbe), 0x12},
+       {CCI_REG8(0x0bbf), 0x00},
+       {CCI_REG8(0x0bc0), 0x1a},
+       {CCI_REG8(0x0bc1), 0x00},
+       {CCI_REG8(0x0bc2), 0x28},
+       {CCI_REG8(0x0bc3), 0x00},
+       {CCI_REG8(0x0bc4), 0x1d},
+       {CCI_REG8(0x0bc5), 0x00},
+       {CCI_REG8(0x0bc6), 0x18},
+       {CCI_REG8(0x0bc7), 0x00},
+       {CCI_REG8(0x0bc8), 0x17},
+       {CCI_REG8(0x0bc9), 0x00},
+       {CCI_REG8(0x0bca), 0x25},
+       {CCI_REG8(0x0bcb), 0x00},
+       {CCI_REG8(0x0bcc), 0x1c},
+       {CCI_REG8(0x0bcd), 0x00},
+       {CCI_REG8(0x0bce), 0x17},
+       {CCI_REG8(0x0bcf), 0x00},
+       {CCI_REG8(0x0bd0), 0x12},
+       {CCI_REG8(0x0bd1), 0x00},
+       {CCI_REG8(0x0bd2), 0x23},
+       {CCI_REG8(0x0bd3), 0x00},
+       {CCI_REG8(0x0bd4), 0x17},
+       {CCI_REG8(0x0bd5), 0x00},
+       {CCI_REG8(0x0bd6), 0x10},
+       {CCI_REG8(0x0bd7), 0x00},
+       {CCI_REG8(0x0bd8), 0x12},
+       {CCI_REG8(0x0bd9), 0x00},
+       {CCI_REG8(0x0bda), 0x23},
+       {CCI_REG8(0x0bdb), 0x00},
+       {CCI_REG8(0x0bdc), 0x19},
+       {CCI_REG8(0x0bdd), 0x00},
+       {CCI_REG8(0x0bde), 0x11},
+       {CCI_REG8(0x0bdf), 0x00},
+       {CCI_REG8(0x0be0), 0x17},
+       {CCI_REG8(0x0be1), 0x00},
+       {CCI_REG8(0x0be2), 0x27},
+       {CCI_REG8(0x0be3), 0x00},
+       {CCI_REG8(0x0be4), 0x1c},
+       {CCI_REG8(0x0be5), 0x00},
+       {CCI_REG8(0x0be6), 0x16},
+       {CCI_REG8(0x0be7), 0x00},
+       {CCI_REG8(0x0be8), 0x17},
+       {CCI_REG8(0x0be9), 0x00},
+       {CCI_REG8(0x0bea), 0x29},
+       {CCI_REG8(0x0beb), 0x00},
+       {CCI_REG8(0x0bec), 0x1e},
+       {CCI_REG8(0x0bed), 0x00},
+       {CCI_REG8(0x0bee), 0x16},
+       {CCI_REG8(0x0bef), 0x00},
+       {CCI_REG8(0x0bf0), 0x1c},
+       {CCI_REG8(0x0bf1), 0x00},
+       {CCI_REG8(0x0bf2), 0x2d},
+       {CCI_REG8(0x0bf3), 0x00},
+       {CCI_REG8(0x0bf4), 0x20},
+       {CCI_REG8(0x0bf5), 0x00},
+       {CCI_REG8(0x0bf6), 0x19},
+       {CCI_REG8(0x0bf7), 0x00},
+       {CCI_REG8(0x0bf8), 0x15},
+       {CCI_REG8(0x0bf9), 0x00},
+       {CCI_REG8(0x0bfa), 0x28},
+       {CCI_REG8(0x0bfb), 0x00},
+       {CCI_REG8(0x0bfc), 0x1d},
+       {CCI_REG8(0x0bfd), 0x00},
+       {CCI_REG8(0x0bfe), 0x13},
+       {CCI_REG8(0x0bff), 0x00},
+       {CCI_REG8(0x0c00), 0x05},
+       {CCI_REG8(0x0c01), 0x00},
+       {CCI_REG8(0x0c02), 0x0e},
+       {CCI_REG8(0x0c03), 0x00},
+       {CCI_REG8(0x0c04), 0x10},
+       {CCI_REG8(0x0c05), 0x00},
+       {CCI_REG8(0x0c06), 0x05},
+       {CCI_REG8(0x0c07), 0x00},
+       {CCI_REG8(0x0c08), 0x09},
+       {CCI_REG8(0x0c09), 0x00},
+       {CCI_REG8(0x0c0a), 0x18},
+       {CCI_REG8(0x0c0b), 0x00},
+       {CCI_REG8(0x0c0c), 0x0d},
+       {CCI_REG8(0x0c0d), 0x00},
+       {CCI_REG8(0x0c0e), 0x06},
+       {CCI_REG8(0x0c0f), 0x00},
+       {CCI_REG8(0x0c10), 0x14},
+       {CCI_REG8(0x0c11), 0x00},
+       {CCI_REG8(0x0c12), 0x22},
+       {CCI_REG8(0x0c13), 0x00},
+       {CCI_REG8(0x0c14), 0x1a},
+       {CCI_REG8(0x0c15), 0x00},
+       {CCI_REG8(0x0c16), 0x13},
+       {CCI_REG8(0x0c17), 0x00},
+       {CCI_REG8(0x0c18), 0x18},
+       {CCI_REG8(0x0c19), 0x00},
+       {CCI_REG8(0x0c1a), 0x26},
+       {CCI_REG8(0x0c1b), 0x00},
+       {CCI_REG8(0x0c1c), 0x1b},
+       {CCI_REG8(0x0c1d), 0x00},
+       {CCI_REG8(0x0c1e), 0x14},
+       {CCI_REG8(0x0c1f), 0x00},
+       {CCI_REG8(0x0c20), 0x10},
+       {CCI_REG8(0x0c21), 0x00},
+       {CCI_REG8(0x0c22), 0x22},
+       {CCI_REG8(0x0c23), 0x00},
+       {CCI_REG8(0x0c24), 0x19},
+       {CCI_REG8(0x0c25), 0x00},
+       {CCI_REG8(0x0c26), 0x10},
+       {CCI_REG8(0x0c27), 0x00},
+       {CCI_REG8(0x0c28), 0x14},
+       {CCI_REG8(0x0c29), 0x00},
+       {CCI_REG8(0x0c2a), 0x26},
+       {CCI_REG8(0x0c2b), 0x00},
+       {CCI_REG8(0x0c2c), 0x1d},
+       {CCI_REG8(0x0c2d), 0x00},
+       {CCI_REG8(0x0c2e), 0x14},
+       {CCI_REG8(0x0c2f), 0x00},
+       {CCI_REG8(0x0c30), 0x1b},
+       {CCI_REG8(0x0c31), 0x00},
+       {CCI_REG8(0x0c32), 0x2c},
+       {CCI_REG8(0x0c33), 0x00},
+       {CCI_REG8(0x0c34), 0x22},
+       {CCI_REG8(0x0c35), 0x00},
+       {CCI_REG8(0x0c36), 0x1b},
+       {CCI_REG8(0x0c37), 0x00},
+       {CCI_REG8(0x0c38), 0x1c},
+       {CCI_REG8(0x0c39), 0x00},
+       {CCI_REG8(0x0c3a), 0x2d},
+       {CCI_REG8(0x0c3b), 0x00},
+       {CCI_REG8(0x0c3c), 0x22},
+       {CCI_REG8(0x0c3d), 0x00},
+       {CCI_REG8(0x0c3e), 0x17},
+       {CCI_REG8(0x0c3f), 0x00},
+       {CCI_REG8(0x0c40), 0x20},
+       {CCI_REG8(0x0c41), 0x00},
+       {CCI_REG8(0x0c42), 0x33},
+       {CCI_REG8(0x0c43), 0x00},
+       {CCI_REG8(0x0c44), 0x29},
+       {CCI_REG8(0x0c45), 0x00},
+       {CCI_REG8(0x0c46), 0x22},
+       {CCI_REG8(0x0c47), 0x00},
+       {CCI_REG8(0x0c48), 0x1b},
+       {CCI_REG8(0x0c49), 0x00},
+       {CCI_REG8(0x0c4a), 0x2e},
+       {CCI_REG8(0x0c4b), 0x00},
+       {CCI_REG8(0x0c4c), 0x23},
+       {CCI_REG8(0x0c4d), 0x00},
+       {CCI_REG8(0x0c4e), 0x18},
+       {CCI_REG8(0x0c4f), 0x00},
+       {CCI_REG8(0x0c50), 0x27},
+       {CCI_REG8(0x0c51), 0x00},
+       {CCI_REG8(0x0c52), 0x38},
+       {CCI_REG8(0x0c53), 0x00},
+       {CCI_REG8(0x0c54), 0x0d},
+       {CCI_REG8(0x0c55), 0x00},
+       {CCI_REG8(0x0c56), 0x1d},
+       {CCI_REG8(0x0c57), 0x00},
+       {CCI_REG8(0x0c58), 0x1b},
+       {CCI_REG8(0x0c59), 0x00},
+       {CCI_REG8(0x0c5a), 0x25},
+       {CCI_REG8(0x0c5b), 0x00},
+       {CCI_REG8(0x0c5c), 0x1e},
+       {CCI_REG8(0x0c5d), 0x00},
+       {CCI_REG8(0x0c5e), 0x22},
+       {CCI_REG8(0x0c5f), 0x00},
+       {CCI_REG8(0x0c60), 0x1b},
+       {CCI_REG8(0x0c61), 0x00},
+       {CCI_REG8(0x0c62), 0x2d},
+       {CCI_REG8(0x0c63), 0x00},
+       {CCI_REG8(0x0c64), 0x1f},
+       {CCI_REG8(0x0c65), 0x00},
+       {CCI_REG8(0x0c66), 0x1e},
+       {CCI_REG8(0x0c67), 0x00},
+       {CCI_REG8(0x0c68), 0x10},
+       {CCI_REG8(0x0c69), 0x00},
+       {CCI_REG8(0x0c6a), 0x21},
+       {CCI_REG8(0x0c6b), 0x00},
+       {CCI_REG8(0x0c6c), 0x17},
+       {CCI_REG8(0x0c6d), 0x00},
+       {CCI_REG8(0x0c6e), 0x19},
+       {CCI_REG8(0x0c6f), 0x00},
+       {CCI_REG8(0x0c70), 0x11},
+       {CCI_REG8(0x0c71), 0x00},
+       {CCI_REG8(0x0c72), 0x20},
+       {CCI_REG8(0x0c73), 0x00},
+       {CCI_REG8(0x0c74), 0x12},
+       {CCI_REG8(0x0c75), 0x00},
+       {CCI_REG8(0x0c76), 0x0c},
+       {CCI_REG8(0x0c77), 0x00},
+       {CCI_REG8(0x0c78), 0x0d},
+       {CCI_REG8(0x0c79), 0x00},
+       {CCI_REG8(0x0c7a), 0x1b},
+       {CCI_REG8(0x0c7b), 0x00},
+       {CCI_REG8(0x0c7c), 0x0e},
+       {CCI_REG8(0x0c7d), 0x00},
+       {CCI_REG8(0x0c7e), 0x0a},
+       {CCI_REG8(0x0c7f), 0x00},
+       {CCI_REG8(0x0c80), 0x0e},
+       {CCI_REG8(0x0c81), 0x00},
+       {CCI_REG8(0x0c82), 0x1f},
+       {CCI_REG8(0x0c83), 0x00},
+       {CCI_REG8(0x0c84), 0x13},
+       {CCI_REG8(0x0c85), 0x00},
+       {CCI_REG8(0x0c86), 0x0e},
+       {CCI_REG8(0x0c87), 0x00},
+       {CCI_REG8(0x0c88), 0x0c},
+       {CCI_REG8(0x0c89), 0x00},
+       {CCI_REG8(0x0c8a), 0x20},
+       {CCI_REG8(0x0c8b), 0x00},
+       {CCI_REG8(0x0c8c), 0x15},
+       {CCI_REG8(0x0c8d), 0x00},
+       {CCI_REG8(0x0c8e), 0x13},
+       {CCI_REG8(0x0c8f), 0x00},
+       {CCI_REG8(0x0c90), 0x12},
+       {CCI_REG8(0x0c91), 0x00},
+       {CCI_REG8(0x0c92), 0x23},
+       {CCI_REG8(0x0c93), 0x00},
+       {CCI_REG8(0x0c94), 0x14},
+       {CCI_REG8(0x0c95), 0x00},
+       {CCI_REG8(0x0c96), 0x0a},
+       {CCI_REG8(0x0c97), 0x00},
+       {CCI_REG8(0x0c98), 0x0f},
+       {CCI_REG8(0x0c99), 0x00},
+       {CCI_REG8(0x0c9a), 0x19},
+       {CCI_REG8(0x0c9b), 0x00},
+       {CCI_REG8(0x0c9c), 0x12},
+       {CCI_REG8(0x0c9d), 0x00},
+       {CCI_REG8(0x0c9e), 0x0c},
+       {CCI_REG8(0x0c9f), 0x00},
+       {CCI_REG8(0xffff), 0x01},
+       {CCI_REG8(0xf920), 0x49},
+       {CCI_REG8(0xf921), 0x01},
+       {CCI_REG8(0xf922), 0x1e},
+       {CCI_REG8(0xf923), 0x01},
+       {CCI_REG8(0xf924), 0x1e},
+       {CCI_REG8(0xf925), 0x01},
+       {CCI_REG8(0xf926), 0x0e},
+       {CCI_REG8(0xf927), 0x01},
+       {CCI_REG8(0xf928), 0x19},
+       {CCI_REG8(0xf929), 0x01},
+       {CCI_REG8(0xf92a), 0xfe},
+       {CCI_REG8(0xf92b), 0x00},
+       {CCI_REG8(0xf92c), 0xfd},
+       {CCI_REG8(0xf92d), 0x00},
+       {CCI_REG8(0xf92e), 0xf6},
+       {CCI_REG8(0xf92f), 0x00},
+       {CCI_REG8(0xf930), 0x16},
+       {CCI_REG8(0xf931), 0x01},
+       {CCI_REG8(0xf932), 0x05},
+       {CCI_REG8(0xf933), 0x01},
+       {CCI_REG8(0xf934), 0x04},
+       {CCI_REG8(0xf935), 0x01},
+       {CCI_REG8(0xf936), 0xff},
+       {CCI_REG8(0xf937), 0x00},
+       {CCI_REG8(0xf938), 0x0a},
+       {CCI_REG8(0xf939), 0x01},
+       {CCI_REG8(0xf93a), 0x00},
+       {CCI_REG8(0xf93b), 0x01},
+       {CCI_REG8(0xf93c), 0xff},
+       {CCI_REG8(0xf93d), 0x00},
+       {CCI_REG8(0xf93e), 0xff},
+       {CCI_REG8(0xf93f), 0x00},
+       {CCI_REG8(0xf940), 0x08},
+       {CCI_REG8(0xf941), 0x01},
+       {CCI_REG8(0xf942), 0x00},
+       {CCI_REG8(0xf943), 0x01},
+       {CCI_REG8(0xf944), 0xff},
+       {CCI_REG8(0xf945), 0x00},
+       {CCI_REG8(0xf946), 0xfe},
+       {CCI_REG8(0xf947), 0x00},
+       {CCI_REG8(0xf948), 0x08},
+       {CCI_REG8(0xf949), 0x01},
+       {CCI_REG8(0xf94a), 0xff},
+       {CCI_REG8(0xf94b), 0x00},
+       {CCI_REG8(0xf94c), 0xfe},
+       {CCI_REG8(0xf94d), 0x00},
+       {CCI_REG8(0xf94e), 0xfc},
+       {CCI_REG8(0xf94f), 0x00},
+       {CCI_REG8(0xf950), 0x0b},
+       {CCI_REG8(0xf951), 0x01},
+       {CCI_REG8(0xf952), 0x00},
+       {CCI_REG8(0xf953), 0x01},
+       {CCI_REG8(0xf954), 0x00},
+       {CCI_REG8(0xf955), 0x01},
+       {CCI_REG8(0xf956), 0xfe},
+       {CCI_REG8(0xf957), 0x00},
+       {CCI_REG8(0xf958), 0x17},
+       {CCI_REG8(0xf959), 0x01},
+       {CCI_REG8(0xf95a), 0x04},
+       {CCI_REG8(0xf95b), 0x01},
+       {CCI_REG8(0xf95c), 0x04},
+       {CCI_REG8(0xf95d), 0x01},
+       {CCI_REG8(0xf95e), 0xfc},
+       {CCI_REG8(0xf95f), 0x00},
+       {CCI_REG8(0xf960), 0x2e},
+       {CCI_REG8(0xf961), 0x01},
+       {CCI_REG8(0xf962), 0x0a},
+       {CCI_REG8(0xf963), 0x01},
+       {CCI_REG8(0xf964), 0x0b},
+       {CCI_REG8(0xf965), 0x01},
+       {CCI_REG8(0xf966), 0xfc},
+       {CCI_REG8(0xf967), 0x00},
+       {CCI_REG8(0xf968), 0x18},
+       {CCI_REG8(0xf969), 0x01},
+       {CCI_REG8(0xf96a), 0x03},
+       {CCI_REG8(0xf96b), 0x01},
+       {CCI_REG8(0xf96c), 0x03},
+       {CCI_REG8(0xf96d), 0x01},
+       {CCI_REG8(0xf96e), 0xfb},
+       {CCI_REG8(0xf96f), 0x00},
+       {CCI_REG8(0xf970), 0x20},
+       {CCI_REG8(0xf971), 0x01},
+       {CCI_REG8(0xf972), 0xff},
+       {CCI_REG8(0xf973), 0x00},
+       {CCI_REG8(0xf974), 0xfe},
+       {CCI_REG8(0xf975), 0x00},
+       {CCI_REG8(0xf976), 0xf4},
+       {CCI_REG8(0xf977), 0x00},
+       {CCI_REG8(0xf978), 0x14},
+       {CCI_REG8(0xf979), 0x01},
+       {CCI_REG8(0xf97a), 0x00},
+       {CCI_REG8(0xf97b), 0x01},
+       {CCI_REG8(0xf97c), 0xff},
+       {CCI_REG8(0xf97d), 0x00},
+       {CCI_REG8(0xf97e), 0xf8},
+       {CCI_REG8(0xf97f), 0x00},
+       {CCI_REG8(0xf980), 0x0a},
+       {CCI_REG8(0xf981), 0x01},
+       {CCI_REG8(0xf982), 0x00},
+       {CCI_REG8(0xf983), 0x01},
+       {CCI_REG8(0xf984), 0xff},
+       {CCI_REG8(0xf985), 0x00},
+       {CCI_REG8(0xf986), 0xfd},
+       {CCI_REG8(0xf987), 0x00},
+       {CCI_REG8(0xf988), 0x04},
+       {CCI_REG8(0xf989), 0x01},
+       {CCI_REG8(0xf98a), 0xff},
+       {CCI_REG8(0xf98b), 0x00},
+       {CCI_REG8(0xf98c), 0xfe},
+       {CCI_REG8(0xf98d), 0x00},
+       {CCI_REG8(0xf98e), 0xfc},
+       {CCI_REG8(0xf98f), 0x00},
+       {CCI_REG8(0xf990), 0x02},
+       {CCI_REG8(0xf991), 0x01},
+       {CCI_REG8(0xf992), 0xff},
+       {CCI_REG8(0xf993), 0x00},
+       {CCI_REG8(0xf994), 0xff},
+       {CCI_REG8(0xf995), 0x00},
+       {CCI_REG8(0xf996), 0xfe},
+       {CCI_REG8(0xf997), 0x00},
+       {CCI_REG8(0xf998), 0x04},
+       {CCI_REG8(0xf999), 0x01},
+       {CCI_REG8(0xf99a), 0x01},
+       {CCI_REG8(0xf99b), 0x01},
+       {CCI_REG8(0xf99c), 0x01},
+       {CCI_REG8(0xf99d), 0x01},
+       {CCI_REG8(0xf99e), 0x00},
+       {CCI_REG8(0xf99f), 0x01},
+       {CCI_REG8(0xf9a0), 0x07},
+       {CCI_REG8(0xf9a1), 0x01},
+       {CCI_REG8(0xf9a2), 0x00},
+       {CCI_REG8(0xf9a3), 0x01},
+       {CCI_REG8(0xf9a4), 0x00},
+       {CCI_REG8(0xf9a5), 0x01},
+       {CCI_REG8(0xf9a6), 0xfd},
+       {CCI_REG8(0xf9a7), 0x00},
+       {CCI_REG8(0xf9a8), 0x0b},
+       {CCI_REG8(0xf9a9), 0x01},
+       {CCI_REG8(0xf9aa), 0xff},
+       {CCI_REG8(0xf9ab), 0x00},
+       {CCI_REG8(0xf9ac), 0xff},
+       {CCI_REG8(0xf9ad), 0x00},
+       {CCI_REG8(0xf9ae), 0xfb},
+       {CCI_REG8(0xf9af), 0x00},
+       {CCI_REG8(0xf9b0), 0x22},
+       {CCI_REG8(0xf9b1), 0x01},
+       {CCI_REG8(0xf9b2), 0x04},
+       {CCI_REG8(0xf9b3), 0x01},
+       {CCI_REG8(0xf9b4), 0x05},
+       {CCI_REG8(0xf9b5), 0x01},
+       {CCI_REG8(0xf9b6), 0xfb},
+       {CCI_REG8(0xf9b7), 0x00},
+       {CCI_REG8(0xf9b8), 0x0b},
+       {CCI_REG8(0xf9b9), 0x01},
+       {CCI_REG8(0xf9ba), 0xff},
+       {CCI_REG8(0xf9bb), 0x00},
+       {CCI_REG8(0xf9bc), 0xff},
+       {CCI_REG8(0xf9bd), 0x00},
+       {CCI_REG8(0xf9be), 0xfb},
+       {CCI_REG8(0xf9bf), 0x00},
+       {CCI_REG8(0xf9c0), 0x1f},
+       {CCI_REG8(0xf9c1), 0x01},
+       {CCI_REG8(0xf9c2), 0x01},
+       {CCI_REG8(0xf9c3), 0x01},
+       {CCI_REG8(0xf9c4), 0x01},
+       {CCI_REG8(0xf9c5), 0x01},
+       {CCI_REG8(0xf9c6), 0xf6},
+       {CCI_REG8(0xf9c7), 0x00},
+       {CCI_REG8(0xf9c8), 0x0f},
+       {CCI_REG8(0xf9c9), 0x01},
+       {CCI_REG8(0xf9ca), 0x00},
+       {CCI_REG8(0xf9cb), 0x01},
+       {CCI_REG8(0xf9cc), 0xff},
+       {CCI_REG8(0xf9cd), 0x00},
+       {CCI_REG8(0xf9ce), 0xfa},
+       {CCI_REG8(0xf9cf), 0x00},
+       {CCI_REG8(0xf9d0), 0x05},
+       {CCI_REG8(0xf9d1), 0x01},
+       {CCI_REG8(0xf9d2), 0xff},
+       {CCI_REG8(0xf9d3), 0x00},
+       {CCI_REG8(0xf9d4), 0xff},
+       {CCI_REG8(0xf9d5), 0x00},
+       {CCI_REG8(0xf9d6), 0xfc},
+       {CCI_REG8(0xf9d7), 0x00},
+       {CCI_REG8(0xf9d8), 0x03},
+       {CCI_REG8(0xf9d9), 0x01},
+       {CCI_REG8(0xf9da), 0x01},
+       {CCI_REG8(0xf9db), 0x01},
+       {CCI_REG8(0xf9dc), 0x00},
+       {CCI_REG8(0xf9dd), 0x01},
+       {CCI_REG8(0xf9de), 0xff},
+       {CCI_REG8(0xf9df), 0x00},
+       {CCI_REG8(0xf9e0), 0x00},
+       {CCI_REG8(0xf9e1), 0x01},
+       {CCI_REG8(0xf9e2), 0x00},
+       {CCI_REG8(0xf9e3), 0x01},
+       {CCI_REG8(0xf9e4), 0x00},
+       {CCI_REG8(0xf9e5), 0x01},
+       {CCI_REG8(0xf9e6), 0xff},
+       {CCI_REG8(0xf9e7), 0x00},
+       {CCI_REG8(0xf9e8), 0xff},
+       {CCI_REG8(0xf9e9), 0x00},
+       {CCI_REG8(0xf9ea), 0x00},
+       {CCI_REG8(0xf9eb), 0x01},
+       {CCI_REG8(0xf9ec), 0x00},
+       {CCI_REG8(0xf9ed), 0x01},
+       {CCI_REG8(0xf9ee), 0xff},
+       {CCI_REG8(0xf9ef), 0x00},
+       {CCI_REG8(0xf9f0), 0x06},
+       {CCI_REG8(0xf9f1), 0x01},
+       {CCI_REG8(0xf9f2), 0x02},
+       {CCI_REG8(0xf9f3), 0x01},
+       {CCI_REG8(0xf9f4), 0x03},
+       {CCI_REG8(0xf9f5), 0x01},
+       {CCI_REG8(0xf9f6), 0x00},
+       {CCI_REG8(0xf9f7), 0x01},
+       {CCI_REG8(0xf9f8), 0x08},
+       {CCI_REG8(0xf9f9), 0x01},
+       {CCI_REG8(0xf9fa), 0xff},
+       {CCI_REG8(0xf9fb), 0x00},
+       {CCI_REG8(0xf9fc), 0xff},
+       {CCI_REG8(0xf9fd), 0x00},
+       {CCI_REG8(0xf9fe), 0xfd},
+       {CCI_REG8(0xf9ff), 0x00},
+       {CCI_REG8(0xfa00), 0x1a},
+       {CCI_REG8(0xfa01), 0x01},
+       {CCI_REG8(0xfa02), 0x00},
+       {CCI_REG8(0xfa03), 0x01},
+       {CCI_REG8(0xfa04), 0x01},
+       {CCI_REG8(0xfa05), 0x01},
+       {CCI_REG8(0xfa06), 0xfa},
+       {CCI_REG8(0xfa07), 0x00},
+       {CCI_REG8(0xfa08), 0x0a},
+       {CCI_REG8(0xfa09), 0x01},
+       {CCI_REG8(0xfa0a), 0x00},
+       {CCI_REG8(0xfa0b), 0x01},
+       {CCI_REG8(0xfa0c), 0x00},
+       {CCI_REG8(0xfa0d), 0x01},
+       {CCI_REG8(0xfa0e), 0xfd},
+       {CCI_REG8(0xfa0f), 0x00},
+       {CCI_REG8(0xfa10), 0x1c},
+       {CCI_REG8(0xfa11), 0x01},
+       {CCI_REG8(0xfa12), 0xff},
+       {CCI_REG8(0xfa13), 0x00},
+       {CCI_REG8(0xfa14), 0xfe},
+       {CCI_REG8(0xfa15), 0x00},
+       {CCI_REG8(0xfa16), 0xf3},
+       {CCI_REG8(0xfa17), 0x00},
+       {CCI_REG8(0xfa18), 0x10},
+       {CCI_REG8(0xfa19), 0x01},
+       {CCI_REG8(0xfa1a), 0x02},
+       {CCI_REG8(0xfa1b), 0x01},
+       {CCI_REG8(0xfa1c), 0x01},
+       {CCI_REG8(0xfa1d), 0x01},
+       {CCI_REG8(0xfa1e), 0xfc},
+       {CCI_REG8(0xfa1f), 0x00},
+       {CCI_REG8(0xfa20), 0x08},
+       {CCI_REG8(0xfa21), 0x01},
+       {CCI_REG8(0xfa22), 0x02},
+       {CCI_REG8(0xfa23), 0x01},
+       {CCI_REG8(0xfa24), 0x02},
+       {CCI_REG8(0xfa25), 0x01},
+       {CCI_REG8(0xfa26), 0xff},
+       {CCI_REG8(0xfa27), 0x00},
+       {CCI_REG8(0xfa28), 0x01},
+       {CCI_REG8(0xfa29), 0x01},
+       {CCI_REG8(0xfa2a), 0x00},
+       {CCI_REG8(0xfa2b), 0x01},
+       {CCI_REG8(0xfa2c), 0x00},
+       {CCI_REG8(0xfa2d), 0x01},
+       {CCI_REG8(0xfa2e), 0xfe},
+       {CCI_REG8(0xfa2f), 0x00},
+       {CCI_REG8(0xfa30), 0x00},
+       {CCI_REG8(0xfa31), 0x01},
+       {CCI_REG8(0xfa32), 0x01},
+       {CCI_REG8(0xfa33), 0x01},
+       {CCI_REG8(0xfa34), 0x01},
+       {CCI_REG8(0xfa35), 0x01},
+       {CCI_REG8(0xfa36), 0x01},
+       {CCI_REG8(0xfa37), 0x01},
+       {CCI_REG8(0xfa38), 0xff},
+       {CCI_REG8(0xfa39), 0x00},
+       {CCI_REG8(0xfa3a), 0xff},
+       {CCI_REG8(0xfa3b), 0x00},
+       {CCI_REG8(0xfa3c), 0xff},
+       {CCI_REG8(0xfa3d), 0x00},
+       {CCI_REG8(0xfa3e), 0xff},
+       {CCI_REG8(0xfa3f), 0x00},
+       {CCI_REG8(0xfa40), 0x05},
+       {CCI_REG8(0xfa41), 0x01},
+       {CCI_REG8(0xfa42), 0x01},
+       {CCI_REG8(0xfa43), 0x01},
+       {CCI_REG8(0xfa44), 0x01},
+       {CCI_REG8(0xfa45), 0x01},
+       {CCI_REG8(0xfa46), 0x00},
+       {CCI_REG8(0xfa47), 0x01},
+       {CCI_REG8(0xfa48), 0x08},
+       {CCI_REG8(0xfa49), 0x01},
+       {CCI_REG8(0xfa4a), 0xff},
+       {CCI_REG8(0xfa4b), 0x00},
+       {CCI_REG8(0xfa4c), 0xff},
+       {CCI_REG8(0xfa4d), 0x00},
+       {CCI_REG8(0xfa4e), 0xfe},
+       {CCI_REG8(0xfa4f), 0x00},
+       {CCI_REG8(0xfa50), 0x17},
+       {CCI_REG8(0xfa51), 0x01},
+       {CCI_REG8(0xfa52), 0xfe},
+       {CCI_REG8(0xfa53), 0x00},
+       {CCI_REG8(0xfa54), 0xfe},
+       {CCI_REG8(0xfa55), 0x00},
+       {CCI_REG8(0xfa56), 0xf8},
+       {CCI_REG8(0xfa57), 0x00},
+       {CCI_REG8(0xfa58), 0x0a},
+       {CCI_REG8(0xfa59), 0x01},
+       {CCI_REG8(0xfa5a), 0x00},
+       {CCI_REG8(0xfa5b), 0x01},
+       {CCI_REG8(0xfa5c), 0x00},
+       {CCI_REG8(0xfa5d), 0x01},
+       {CCI_REG8(0xfa5e), 0xfe},
+       {CCI_REG8(0xfa5f), 0x00},
+       {CCI_REG8(0xfa60), 0x1b},
+       {CCI_REG8(0xfa61), 0x01},
+       {CCI_REG8(0xfa62), 0xfc},
+       {CCI_REG8(0xfa63), 0x00},
+       {CCI_REG8(0xfa64), 0xfb},
+       {CCI_REG8(0xfa65), 0x00},
+       {CCI_REG8(0xfa66), 0xf1},
+       {CCI_REG8(0xfa67), 0x00},
+       {CCI_REG8(0xfa68), 0x14},
+       {CCI_REG8(0xfa69), 0x01},
+       {CCI_REG8(0xfa6a), 0x01},
+       {CCI_REG8(0xfa6b), 0x01},
+       {CCI_REG8(0xfa6c), 0x01},
+       {CCI_REG8(0xfa6d), 0x01},
+       {CCI_REG8(0xfa6e), 0xf9},
+       {CCI_REG8(0xfa6f), 0x00},
+       {CCI_REG8(0xfa70), 0x08},
+       {CCI_REG8(0xfa71), 0x01},
+       {CCI_REG8(0xfa72), 0x01},
+       {CCI_REG8(0xfa73), 0x01},
+       {CCI_REG8(0xfa74), 0x00},
+       {CCI_REG8(0xfa75), 0x01},
+       {CCI_REG8(0xfa76), 0xfd},
+       {CCI_REG8(0xfa77), 0x00},
+       {CCI_REG8(0xfa78), 0x06},
+       {CCI_REG8(0xfa79), 0x01},
+       {CCI_REG8(0xfa7a), 0x02},
+       {CCI_REG8(0xfa7b), 0x01},
+       {CCI_REG8(0xfa7c), 0x02},
+       {CCI_REG8(0xfa7d), 0x01},
+       {CCI_REG8(0xfa7e), 0xff},
+       {CCI_REG8(0xfa7f), 0x00},
+       {CCI_REG8(0xfa80), 0x01},
+       {CCI_REG8(0xfa81), 0x01},
+       {CCI_REG8(0xfa82), 0xff},
+       {CCI_REG8(0xfa83), 0x00},
+       {CCI_REG8(0xfa84), 0xfe},
+       {CCI_REG8(0xfa85), 0x00},
+       {CCI_REG8(0xfa86), 0xfe},
+       {CCI_REG8(0xfa87), 0x00},
+       {CCI_REG8(0xfa88), 0x03},
+       {CCI_REG8(0xfa89), 0x01},
+       {CCI_REG8(0xfa8a), 0x00},
+       {CCI_REG8(0xfa8b), 0x01},
+       {CCI_REG8(0xfa8c), 0x00},
+       {CCI_REG8(0xfa8d), 0x01},
+       {CCI_REG8(0xfa8e), 0xff},
+       {CCI_REG8(0xfa8f), 0x00},
+       {CCI_REG8(0xfa90), 0x07},
+       {CCI_REG8(0xfa91), 0x01},
+       {CCI_REG8(0xfa92), 0x00},
+       {CCI_REG8(0xfa93), 0x01},
+       {CCI_REG8(0xfa94), 0x00},
+       {CCI_REG8(0xfa95), 0x01},
+       {CCI_REG8(0xfa96), 0xff},
+       {CCI_REG8(0xfa97), 0x00},
+       {CCI_REG8(0xfa98), 0x0b},
+       {CCI_REG8(0xfa99), 0x01},
+       {CCI_REG8(0xfa9a), 0xff},
+       {CCI_REG8(0xfa9b), 0x00},
+       {CCI_REG8(0xfa9c), 0xff},
+       {CCI_REG8(0xfa9d), 0x00},
+       {CCI_REG8(0xfa9e), 0xfd},
+       {CCI_REG8(0xfa9f), 0x00},
+       {CCI_REG8(0xfaa0), 0x1d},
+       {CCI_REG8(0xfaa1), 0x01},
+       {CCI_REG8(0xfaa2), 0xff},
+       {CCI_REG8(0xfaa3), 0x00},
+       {CCI_REG8(0xfaa4), 0x00},
+       {CCI_REG8(0xfaa5), 0x01},
+       {CCI_REG8(0xfaa6), 0xf8},
+       {CCI_REG8(0xfaa7), 0x00},
+       {CCI_REG8(0xfaa8), 0x0c},
+       {CCI_REG8(0xfaa9), 0x01},
+       {CCI_REG8(0xfaaa), 0xff},
+       {CCI_REG8(0xfaab), 0x00},
+       {CCI_REG8(0xfaac), 0xff},
+       {CCI_REG8(0xfaad), 0x00},
+       {CCI_REG8(0xfaae), 0xfd},
+       {CCI_REG8(0xfaaf), 0x00},
+       {CCI_REG8(0xfab0), 0x37},
+       {CCI_REG8(0xfab1), 0x01},
+       {CCI_REG8(0xfab2), 0x10},
+       {CCI_REG8(0xfab3), 0x01},
+       {CCI_REG8(0xfab4), 0x0f},
+       {CCI_REG8(0xfab5), 0x01},
+       {CCI_REG8(0xfab6), 0x00},
+       {CCI_REG8(0xfab7), 0x01},
+       {CCI_REG8(0xfab8), 0x16},
+       {CCI_REG8(0xfab9), 0x01},
+       {CCI_REG8(0xfaba), 0xfe},
+       {CCI_REG8(0xfabb), 0x00},
+       {CCI_REG8(0xfabc), 0xfd},
+       {CCI_REG8(0xfabd), 0x00},
+       {CCI_REG8(0xfabe), 0xf3},
+       {CCI_REG8(0xfabf), 0x00},
+       {CCI_REG8(0xfac0), 0x13},
+       {CCI_REG8(0xfac1), 0x01},
+       {CCI_REG8(0xfac2), 0x04},
+       {CCI_REG8(0xfac3), 0x01},
+       {CCI_REG8(0xfac4), 0x04},
+       {CCI_REG8(0xfac5), 0x01},
+       {CCI_REG8(0xfac6), 0xfe},
+       {CCI_REG8(0xfac7), 0x00},
+       {CCI_REG8(0xfac8), 0x0b},
+       {CCI_REG8(0xfac9), 0x01},
+       {CCI_REG8(0xfaca), 0x02},
+       {CCI_REG8(0xfacb), 0x01},
+       {CCI_REG8(0xfacc), 0x01},
+       {CCI_REG8(0xfacd), 0x01},
+       {CCI_REG8(0xface), 0xff},
+       {CCI_REG8(0xfacf), 0x00},
+       {CCI_REG8(0xfad0), 0x08},
+       {CCI_REG8(0xfad1), 0x01},
+       {CCI_REG8(0xfad2), 0x00},
+       {CCI_REG8(0xfad3), 0x01},
+       {CCI_REG8(0xfad4), 0x00},
+       {CCI_REG8(0xfad5), 0x01},
+       {CCI_REG8(0xfad6), 0xfe},
+       {CCI_REG8(0xfad7), 0x00},
+       {CCI_REG8(0xfad8), 0x07},
+       {CCI_REG8(0xfad9), 0x01},
+       {CCI_REG8(0xfada), 0xff},
+       {CCI_REG8(0xfadb), 0x00},
+       {CCI_REG8(0xfadc), 0xff},
+       {CCI_REG8(0xfadd), 0x00},
+       {CCI_REG8(0xfade), 0xfe},
+       {CCI_REG8(0xfadf), 0x00},
+       {CCI_REG8(0xfae0), 0x0c},
+       {CCI_REG8(0xfae1), 0x01},
+       {CCI_REG8(0xfae2), 0xff},
+       {CCI_REG8(0xfae3), 0x00},
+       {CCI_REG8(0xfae4), 0xff},
+       {CCI_REG8(0xfae5), 0x00},
+       {CCI_REG8(0xfae6), 0xfe},
+       {CCI_REG8(0xfae7), 0x00},
+       {CCI_REG8(0xfae8), 0x15},
+       {CCI_REG8(0xfae9), 0x01},
+       {CCI_REG8(0xfaea), 0x00},
+       {CCI_REG8(0xfaeb), 0x01},
+       {CCI_REG8(0xfaec), 0x01},
+       {CCI_REG8(0xfaed), 0x01},
+       {CCI_REG8(0xfaee), 0xfd},
+       {CCI_REG8(0xfaef), 0x00},
+       {CCI_REG8(0xfaf0), 0x22},
+       {CCI_REG8(0xfaf1), 0x01},
+       {CCI_REG8(0xfaf2), 0xfc},
+       {CCI_REG8(0xfaf3), 0x00},
+       {CCI_REG8(0xfaf4), 0xfc},
+       {CCI_REG8(0xfaf5), 0x00},
+       {CCI_REG8(0xfaf6), 0xf4},
+       {CCI_REG8(0xfaf7), 0x00},
+       {CCI_REG8(0xfaf8), 0x15},
+       {CCI_REG8(0xfaf9), 0x01},
+       {CCI_REG8(0xfafa), 0xff},
+       {CCI_REG8(0xfafb), 0x00},
+       {CCI_REG8(0xfafc), 0xfe},
+       {CCI_REG8(0xfafd), 0x00},
+       {CCI_REG8(0xfafe), 0xfb},
+       {CCI_REG8(0xfaff), 0x00},
+       {CCI_REG8(0xfb00), 0xf5},
+       {CCI_REG8(0xfb01), 0x00},
+       {CCI_REG8(0xfb02), 0xe0},
+       {CCI_REG8(0xfb03), 0x00},
+       {CCI_REG8(0xfb04), 0xdf},
+       {CCI_REG8(0xfb05), 0x00},
+       {CCI_REG8(0xfb06), 0xda},
+       {CCI_REG8(0xfb07), 0x00},
+       {CCI_REG8(0xfb08), 0x10},
+       {CCI_REG8(0xfb09), 0x01},
+       {CCI_REG8(0xfb0a), 0x06},
+       {CCI_REG8(0xfb0b), 0x01},
+       {CCI_REG8(0xfb0c), 0x06},
+       {CCI_REG8(0xfb0d), 0x01},
+       {CCI_REG8(0xfb0e), 0x01},
+       {CCI_REG8(0xfb0f), 0x01},
+       {CCI_REG8(0xfb10), 0xfd},
+       {CCI_REG8(0xfb11), 0x00},
+       {CCI_REG8(0xfb12), 0xfd},
+       {CCI_REG8(0xfb13), 0x00},
+       {CCI_REG8(0xfb14), 0xfd},
+       {CCI_REG8(0xfb15), 0x00},
+       {CCI_REG8(0xfb16), 0xfd},
+       {CCI_REG8(0xfb17), 0x00},
+       {CCI_REG8(0xfb18), 0xff},
+       {CCI_REG8(0xfb19), 0x00},
+       {CCI_REG8(0xfb1a), 0x02},
+       {CCI_REG8(0xfb1b), 0x01},
+       {CCI_REG8(0xfb1c), 0x01},
+       {CCI_REG8(0xfb1d), 0x01},
+       {CCI_REG8(0xfb1e), 0xff},
+       {CCI_REG8(0xfb1f), 0x00},
+       {CCI_REG8(0xfb20), 0xf8},
+       {CCI_REG8(0xfb21), 0x00},
+       {CCI_REG8(0xfb22), 0xfd},
+       {CCI_REG8(0xfb23), 0x00},
+       {CCI_REG8(0xfb24), 0xfe},
+       {CCI_REG8(0xfb25), 0x00},
+       {CCI_REG8(0xfb26), 0xfe},
+       {CCI_REG8(0xfb27), 0x00},
+       {CCI_REG8(0xfb28), 0xfd},
+       {CCI_REG8(0xfb29), 0x00},
+       {CCI_REG8(0xfb2a), 0x01},
+       {CCI_REG8(0xfb2b), 0x01},
+       {CCI_REG8(0xfb2c), 0x02},
+       {CCI_REG8(0xfb2d), 0x01},
+       {CCI_REG8(0xfb2e), 0x01},
+       {CCI_REG8(0xfb2f), 0x01},
+       {CCI_REG8(0xfb30), 0x01},
+       {CCI_REG8(0xfb31), 0x01},
+       {CCI_REG8(0xfb32), 0x00},
+       {CCI_REG8(0xfb33), 0x01},
+       {CCI_REG8(0xfb34), 0x01},
+       {CCI_REG8(0xfb35), 0x01},
+       {CCI_REG8(0xfb36), 0xff},
+       {CCI_REG8(0xfb37), 0x00},
+       {CCI_REG8(0xfb38), 0xfe},
+       {CCI_REG8(0xfb39), 0x00},
+       {CCI_REG8(0xfb3a), 0xfd},
+       {CCI_REG8(0xfb3b), 0x00},
+       {CCI_REG8(0xfb3c), 0xfd},
+       {CCI_REG8(0xfb3d), 0x00},
+       {CCI_REG8(0xfb3e), 0xfd},
+       {CCI_REG8(0xfb3f), 0x00},
+       {CCI_REG8(0xfb40), 0x16},
+       {CCI_REG8(0xfb41), 0x01},
+       {CCI_REG8(0xfb42), 0x02},
+       {CCI_REG8(0xfb43), 0x01},
+       {CCI_REG8(0xfb44), 0x03},
+       {CCI_REG8(0xfb45), 0x01},
+       {CCI_REG8(0xfb46), 0xfd},
+       {CCI_REG8(0xfb47), 0x00},
+       {CCI_REG8(0xfb48), 0x02},
+       {CCI_REG8(0xfb49), 0x01},
+       {CCI_REG8(0xfb4a), 0xff},
+       {CCI_REG8(0xfb4b), 0x00},
+       {CCI_REG8(0xfb4c), 0xff},
+       {CCI_REG8(0xfb4d), 0x00},
+       {CCI_REG8(0xfb4e), 0x00},
+       {CCI_REG8(0xfb4f), 0x01},
+       {CCI_REG8(0xfb50), 0x5f},
+       {CCI_REG8(0xfb51), 0x01},
+       {CCI_REG8(0xfb52), 0x2b},
+       {CCI_REG8(0xfb53), 0x01},
+       {CCI_REG8(0xfb54), 0x2b},
+       {CCI_REG8(0xfb55), 0x01},
+       {CCI_REG8(0xfb56), 0x0e},
+       {CCI_REG8(0xfb57), 0x01},
+       {CCI_REG8(0xfb58), 0x2e},
+       {CCI_REG8(0xfb59), 0x01},
+       {CCI_REG8(0xfb5a), 0x08},
+       {CCI_REG8(0xfb5b), 0x01},
+       {CCI_REG8(0xfb5c), 0x07},
+       {CCI_REG8(0xfb5d), 0x01},
+       {CCI_REG8(0xfb5e), 0xf9},
+       {CCI_REG8(0xfb5f), 0x00},
+       {CCI_REG8(0xfb60), 0x26},
+       {CCI_REG8(0xfb61), 0x01},
+       {CCI_REG8(0xfb62), 0x10},
+       {CCI_REG8(0xfb63), 0x01},
+       {CCI_REG8(0xfb64), 0x0f},
+       {CCI_REG8(0xfb65), 0x01},
+       {CCI_REG8(0xfb66), 0x07},
+       {CCI_REG8(0xfb67), 0x01},
+       {CCI_REG8(0xfb68), 0x16},
+       {CCI_REG8(0xfb69), 0x01},
+       {CCI_REG8(0xfb6a), 0x0a},
+       {CCI_REG8(0xfb6b), 0x01},
+       {CCI_REG8(0xfb6c), 0x0a},
+       {CCI_REG8(0xfb6d), 0x01},
+       {CCI_REG8(0xfb6e), 0x08},
+       {CCI_REG8(0xfb6f), 0x01},
+       {CCI_REG8(0xfb70), 0x11},
+       {CCI_REG8(0xfb71), 0x01},
+       {CCI_REG8(0xfb72), 0x08},
+       {CCI_REG8(0xfb73), 0x01},
+       {CCI_REG8(0xfb74), 0x07},
+       {CCI_REG8(0xfb75), 0x01},
+       {CCI_REG8(0xfb76), 0x05},
+       {CCI_REG8(0xfb77), 0x01},
+       {CCI_REG8(0xfb78), 0x0f},
+       {CCI_REG8(0xfb79), 0x01},
+       {CCI_REG8(0xfb7a), 0x07},
+       {CCI_REG8(0xfb7b), 0x01},
+       {CCI_REG8(0xfb7c), 0x06},
+       {CCI_REG8(0xfb7d), 0x01},
+       {CCI_REG8(0xfb7e), 0x02},
+       {CCI_REG8(0xfb7f), 0x01},
+       {CCI_REG8(0xfb80), 0x15},
+       {CCI_REG8(0xfb81), 0x01},
+       {CCI_REG8(0xfb82), 0x0a},
+       {CCI_REG8(0xfb83), 0x01},
+       {CCI_REG8(0xfb84), 0x0a},
+       {CCI_REG8(0xfb85), 0x01},
+       {CCI_REG8(0xfb86), 0x07},
+       {CCI_REG8(0xfb87), 0x01},
+       {CCI_REG8(0xfb88), 0x20},
+       {CCI_REG8(0xfb89), 0x01},
+       {CCI_REG8(0xfb8a), 0x0e},
+       {CCI_REG8(0xfb8b), 0x01},
+       {CCI_REG8(0xfb8c), 0x0d},
+       {CCI_REG8(0xfb8d), 0x01},
+       {CCI_REG8(0xfb8e), 0x04},
+       {CCI_REG8(0xfb8f), 0x01},
+       {CCI_REG8(0xfb90), 0x38},
+       {CCI_REG8(0xfb91), 0x01},
+       {CCI_REG8(0xfb92), 0x15},
+       {CCI_REG8(0xfb93), 0x01},
+       {CCI_REG8(0xfb94), 0x14},
+       {CCI_REG8(0xfb95), 0x01},
+       {CCI_REG8(0xfb96), 0xff},
+       {CCI_REG8(0xfb97), 0x00},
+       {CCI_REG8(0xfb98), 0x20},
+       {CCI_REG8(0xfb99), 0x01},
+       {CCI_REG8(0xfb9a), 0x0d},
+       {CCI_REG8(0xfb9b), 0x01},
+       {CCI_REG8(0xfb9c), 0x0d},
+       {CCI_REG8(0xfb9d), 0x01},
+       {CCI_REG8(0xfb9e), 0x03},
+       {CCI_REG8(0xfb9f), 0x01},
+       {CCI_REG8(0xfba0), 0x31},
+       {CCI_REG8(0xfba1), 0x01},
+       {CCI_REG8(0xfba2), 0x09},
+       {CCI_REG8(0xfba3), 0x01},
+       {CCI_REG8(0xfba4), 0x09},
+       {CCI_REG8(0xfba5), 0x01},
+       {CCI_REG8(0xfba6), 0xf4},
+       {CCI_REG8(0xfba7), 0x00},
+       {CCI_REG8(0xfba8), 0x1e},
+       {CCI_REG8(0xfba9), 0x01},
+       {CCI_REG8(0xfbaa), 0x06},
+       {CCI_REG8(0xfbab), 0x01},
+       {CCI_REG8(0xfbac), 0x05},
+       {CCI_REG8(0xfbad), 0x01},
+       {CCI_REG8(0xfbae), 0xfb},
+       {CCI_REG8(0xfbaf), 0x00},
+       {CCI_REG8(0xfbb0), 0x10},
+       {CCI_REG8(0xfbb1), 0x01},
+       {CCI_REG8(0xfbb2), 0x05},
+       {CCI_REG8(0xfbb3), 0x01},
+       {CCI_REG8(0xfbb4), 0x05},
+       {CCI_REG8(0xfbb5), 0x01},
+       {CCI_REG8(0xfbb6), 0x01},
+       {CCI_REG8(0xfbb7), 0x01},
+       {CCI_REG8(0xfbb8), 0x06},
+       {CCI_REG8(0xfbb9), 0x01},
+       {CCI_REG8(0xfbba), 0x00},
+       {CCI_REG8(0xfbbb), 0x01},
+       {CCI_REG8(0xfbbc), 0x00},
+       {CCI_REG8(0xfbbd), 0x01},
+       {CCI_REG8(0xfbbe), 0xfd},
+       {CCI_REG8(0xfbbf), 0x00},
+       {CCI_REG8(0xfbc0), 0x03},
+       {CCI_REG8(0xfbc1), 0x01},
+       {CCI_REG8(0xfbc2), 0x01},
+       {CCI_REG8(0xfbc3), 0x01},
+       {CCI_REG8(0xfbc4), 0x01},
+       {CCI_REG8(0xfbc5), 0x01},
+       {CCI_REG8(0xfbc6), 0xff},
+       {CCI_REG8(0xfbc7), 0x00},
+       {CCI_REG8(0xfbc8), 0x05},
+       {CCI_REG8(0xfbc9), 0x01},
+       {CCI_REG8(0xfbca), 0x03},
+       {CCI_REG8(0xfbcb), 0x01},
+       {CCI_REG8(0xfbcc), 0x02},
+       {CCI_REG8(0xfbcd), 0x01},
+       {CCI_REG8(0xfbce), 0x01},
+       {CCI_REG8(0xfbcf), 0x01},
+       {CCI_REG8(0xfbd0), 0x09},
+       {CCI_REG8(0xfbd1), 0x01},
+       {CCI_REG8(0xfbd2), 0x03},
+       {CCI_REG8(0xfbd3), 0x01},
+       {CCI_REG8(0xfbd4), 0x03},
+       {CCI_REG8(0xfbd5), 0x01},
+       {CCI_REG8(0xfbd6), 0xff},
+       {CCI_REG8(0xfbd7), 0x00},
+       {CCI_REG8(0xfbd8), 0x0f},
+       {CCI_REG8(0xfbd9), 0x01},
+       {CCI_REG8(0xfbda), 0x05},
+       {CCI_REG8(0xfbdb), 0x01},
+       {CCI_REG8(0xfbdc), 0x04},
+       {CCI_REG8(0xfbdd), 0x01},
+       {CCI_REG8(0xfbde), 0xff},
+       {CCI_REG8(0xfbdf), 0x00},
+       {CCI_REG8(0xfbe0), 0x2a},
+       {CCI_REG8(0xfbe1), 0x01},
+       {CCI_REG8(0xfbe2), 0x0e},
+       {CCI_REG8(0xfbe3), 0x01},
+       {CCI_REG8(0xfbe4), 0x0d},
+       {CCI_REG8(0xfbe5), 0x01},
+       {CCI_REG8(0xfbe6), 0xfe},
+       {CCI_REG8(0xfbe7), 0x00},
+       {CCI_REG8(0xfbe8), 0x0f},
+       {CCI_REG8(0xfbe9), 0x01},
+       {CCI_REG8(0xfbea), 0x04},
+       {CCI_REG8(0xfbeb), 0x01},
+       {CCI_REG8(0xfbec), 0x04},
+       {CCI_REG8(0xfbed), 0x01},
+       {CCI_REG8(0xfbee), 0xfe},
+       {CCI_REG8(0xfbef), 0x00},
+       {CCI_REG8(0xfbf0), 0x2a},
+       {CCI_REG8(0xfbf1), 0x01},
+       {CCI_REG8(0xfbf2), 0x08},
+       {CCI_REG8(0xfbf3), 0x01},
+       {CCI_REG8(0xfbf4), 0x08},
+       {CCI_REG8(0xfbf5), 0x01},
+       {CCI_REG8(0xfbf6), 0xf5},
+       {CCI_REG8(0xfbf7), 0x00},
+       {CCI_REG8(0xfbf8), 0x18},
+       {CCI_REG8(0xfbf9), 0x01},
+       {CCI_REG8(0xfbfa), 0x07},
+       {CCI_REG8(0xfbfb), 0x01},
+       {CCI_REG8(0xfbfc), 0x07},
+       {CCI_REG8(0xfbfd), 0x01},
+       {CCI_REG8(0xfbfe), 0xfe},
+       {CCI_REG8(0xfbff), 0x00},
+       {CCI_REG8(0xfc00), 0x09},
+       {CCI_REG8(0xfc01), 0x01},
+       {CCI_REG8(0xfc02), 0x02},
+       {CCI_REG8(0xfc03), 0x01},
+       {CCI_REG8(0xfc04), 0x02},
+       {CCI_REG8(0xfc05), 0x01},
+       {CCI_REG8(0xfc06), 0xfe},
+       {CCI_REG8(0xfc07), 0x00},
+       {CCI_REG8(0xfc08), 0x03},
+       {CCI_REG8(0xfc09), 0x01},
+       {CCI_REG8(0xfc0a), 0x01},
+       {CCI_REG8(0xfc0b), 0x01},
+       {CCI_REG8(0xfc0c), 0x01},
+       {CCI_REG8(0xfc0d), 0x01},
+       {CCI_REG8(0xfc0e), 0xff},
+       {CCI_REG8(0xfc0f), 0x00},
+       {CCI_REG8(0xfc10), 0xff},
+       {CCI_REG8(0xfc11), 0x00},
+       {CCI_REG8(0xfc12), 0xff},
+       {CCI_REG8(0xfc13), 0x00},
+       {CCI_REG8(0xfc14), 0xff},
+       {CCI_REG8(0xfc15), 0x00},
+       {CCI_REG8(0xfc16), 0xff},
+       {CCI_REG8(0xfc17), 0x00},
+       {CCI_REG8(0xfc18), 0x00},
+       {CCI_REG8(0xfc19), 0x01},
+       {CCI_REG8(0xfc1a), 0x00},
+       {CCI_REG8(0xfc1b), 0x01},
+       {CCI_REG8(0xfc1c), 0xff},
+       {CCI_REG8(0xfc1d), 0x00},
+       {CCI_REG8(0xfc1e), 0x00},
+       {CCI_REG8(0xfc1f), 0x01},
+       {CCI_REG8(0xfc20), 0x07},
+       {CCI_REG8(0xfc21), 0x01},
+       {CCI_REG8(0xfc22), 0x04},
+       {CCI_REG8(0xfc23), 0x01},
+       {CCI_REG8(0xfc24), 0x04},
+       {CCI_REG8(0xfc25), 0x01},
+       {CCI_REG8(0xfc26), 0x01},
+       {CCI_REG8(0xfc27), 0x01},
+       {CCI_REG8(0xfc28), 0x0c},
+       {CCI_REG8(0xfc29), 0x01},
+       {CCI_REG8(0xfc2a), 0x04},
+       {CCI_REG8(0xfc2b), 0x01},
+       {CCI_REG8(0xfc2c), 0x03},
+       {CCI_REG8(0xfc2d), 0x01},
+       {CCI_REG8(0xfc2e), 0x00},
+       {CCI_REG8(0xfc2f), 0x01},
+       {CCI_REG8(0xfc30), 0x24},
+       {CCI_REG8(0xfc31), 0x01},
+       {CCI_REG8(0xfc32), 0x09},
+       {CCI_REG8(0xfc33), 0x01},
+       {CCI_REG8(0xfc34), 0x09},
+       {CCI_REG8(0xfc35), 0x01},
+       {CCI_REG8(0xfc36), 0xfd},
+       {CCI_REG8(0xfc37), 0x00},
+       {CCI_REG8(0xfc38), 0x0e},
+       {CCI_REG8(0xfc39), 0x01},
+       {CCI_REG8(0xfc3a), 0x04},
+       {CCI_REG8(0xfc3b), 0x01},
+       {CCI_REG8(0xfc3c), 0x04},
+       {CCI_REG8(0xfc3d), 0x01},
+       {CCI_REG8(0xfc3e), 0xff},
+       {CCI_REG8(0xfc3f), 0x00},
+       {CCI_REG8(0xfc40), 0x26},
+       {CCI_REG8(0xfc41), 0x01},
+       {CCI_REG8(0xfc42), 0x07},
+       {CCI_REG8(0xfc43), 0x01},
+       {CCI_REG8(0xfc44), 0x07},
+       {CCI_REG8(0xfc45), 0x01},
+       {CCI_REG8(0xfc46), 0xf4},
+       {CCI_REG8(0xfc47), 0x00},
+       {CCI_REG8(0xfc48), 0x19},
+       {CCI_REG8(0xfc49), 0x01},
+       {CCI_REG8(0xfc4a), 0x0a},
+       {CCI_REG8(0xfc4b), 0x01},
+       {CCI_REG8(0xfc4c), 0x0a},
+       {CCI_REG8(0xfc4d), 0x01},
+       {CCI_REG8(0xfc4e), 0x02},
+       {CCI_REG8(0xfc4f), 0x01},
+       {CCI_REG8(0xfc50), 0x0b},
+       {CCI_REG8(0xfc51), 0x01},
+       {CCI_REG8(0xfc52), 0x06},
+       {CCI_REG8(0xfc53), 0x01},
+       {CCI_REG8(0xfc54), 0x06},
+       {CCI_REG8(0xfc55), 0x01},
+       {CCI_REG8(0xfc56), 0x02},
+       {CCI_REG8(0xfc57), 0x01},
+       {CCI_REG8(0xfc58), 0x02},
+       {CCI_REG8(0xfc59), 0x01},
+       {CCI_REG8(0xfc5a), 0x01},
+       {CCI_REG8(0xfc5b), 0x01},
+       {CCI_REG8(0xfc5c), 0x01},
+       {CCI_REG8(0xfc5d), 0x01},
+       {CCI_REG8(0xfc5e), 0xff},
+       {CCI_REG8(0xfc5f), 0x00},
+       {CCI_REG8(0xfc60), 0x01},
+       {CCI_REG8(0xfc61), 0x01},
+       {CCI_REG8(0xfc62), 0x01},
+       {CCI_REG8(0xfc63), 0x01},
+       {CCI_REG8(0xfc64), 0x01},
+       {CCI_REG8(0xfc65), 0x01},
+       {CCI_REG8(0xfc66), 0x01},
+       {CCI_REG8(0xfc67), 0x01},
+       {CCI_REG8(0xfc68), 0x00},
+       {CCI_REG8(0xfc69), 0x01},
+       {CCI_REG8(0xfc6a), 0x00},
+       {CCI_REG8(0xfc6b), 0x01},
+       {CCI_REG8(0xfc6c), 0x00},
+       {CCI_REG8(0xfc6d), 0x01},
+       {CCI_REG8(0xfc6e), 0x00},
+       {CCI_REG8(0xfc6f), 0x01},
+       {CCI_REG8(0xfc70), 0x07},
+       {CCI_REG8(0xfc71), 0x01},
+       {CCI_REG8(0xfc72), 0x03},
+       {CCI_REG8(0xfc73), 0x01},
+       {CCI_REG8(0xfc74), 0x03},
+       {CCI_REG8(0xfc75), 0x01},
+       {CCI_REG8(0xfc76), 0x00},
+       {CCI_REG8(0xfc77), 0x01},
+       {CCI_REG8(0xfc78), 0x0d},
+       {CCI_REG8(0xfc79), 0x01},
+       {CCI_REG8(0xfc7a), 0x03},
+       {CCI_REG8(0xfc7b), 0x01},
+       {CCI_REG8(0xfc7c), 0x03},
+       {CCI_REG8(0xfc7d), 0x01},
+       {CCI_REG8(0xfc7e), 0xff},
+       {CCI_REG8(0xfc7f), 0x00},
+       {CCI_REG8(0xfc80), 0x23},
+       {CCI_REG8(0xfc81), 0x01},
+       {CCI_REG8(0xfc82), 0x07},
+       {CCI_REG8(0xfc83), 0x01},
+       {CCI_REG8(0xfc84), 0x07},
+       {CCI_REG8(0xfc85), 0x01},
+       {CCI_REG8(0xfc86), 0xfc},
+       {CCI_REG8(0xfc87), 0x00},
+       {CCI_REG8(0xfc88), 0x0f},
+       {CCI_REG8(0xfc89), 0x01},
+       {CCI_REG8(0xfc8a), 0x04},
+       {CCI_REG8(0xfc8b), 0x01},
+       {CCI_REG8(0xfc8c), 0x04},
+       {CCI_REG8(0xfc8d), 0x01},
+       {CCI_REG8(0xfc8e), 0xff},
+       {CCI_REG8(0xfc8f), 0x00},
+       {CCI_REG8(0xfc90), 0x25},
+       {CCI_REG8(0xfc91), 0x01},
+       {CCI_REG8(0xfc92), 0x06},
+       {CCI_REG8(0xfc93), 0x01},
+       {CCI_REG8(0xfc94), 0x06},
+       {CCI_REG8(0xfc95), 0x01},
+       {CCI_REG8(0xfc96), 0xf3},
+       {CCI_REG8(0xfc97), 0x00},
+       {CCI_REG8(0xfc98), 0x1b},
+       {CCI_REG8(0xfc99), 0x01},
+       {CCI_REG8(0xfc9a), 0x09},
+       {CCI_REG8(0xfc9b), 0x01},
+       {CCI_REG8(0xfc9c), 0x09},
+       {CCI_REG8(0xfc9d), 0x01},
+       {CCI_REG8(0xfc9e), 0xfe},
+       {CCI_REG8(0xfc9f), 0x00},
+       {CCI_REG8(0xfca0), 0x0e},
+       {CCI_REG8(0xfca1), 0x01},
+       {CCI_REG8(0xfca2), 0x07},
+       {CCI_REG8(0xfca3), 0x01},
+       {CCI_REG8(0xfca4), 0x07},
+       {CCI_REG8(0xfca5), 0x01},
+       {CCI_REG8(0xfca6), 0x02},
+       {CCI_REG8(0xfca7), 0x01},
+       {CCI_REG8(0xfca8), 0x09},
+       {CCI_REG8(0xfca9), 0x01},
+       {CCI_REG8(0xfcaa), 0x04},
+       {CCI_REG8(0xfcab), 0x01},
+       {CCI_REG8(0xfcac), 0x04},
+       {CCI_REG8(0xfcad), 0x01},
+       {CCI_REG8(0xfcae), 0x01},
+       {CCI_REG8(0xfcaf), 0x01},
+       {CCI_REG8(0xfcb0), 0x03},
+       {CCI_REG8(0xfcb1), 0x01},
+       {CCI_REG8(0xfcb2), 0x00},
+       {CCI_REG8(0xfcb3), 0x01},
+       {CCI_REG8(0xfcb4), 0x00},
+       {CCI_REG8(0xfcb5), 0x01},
+       {CCI_REG8(0xfcb6), 0xfe},
+       {CCI_REG8(0xfcb7), 0x00},
+       {CCI_REG8(0xfcb8), 0x06},
+       {CCI_REG8(0xfcb9), 0x01},
+       {CCI_REG8(0xfcba), 0x03},
+       {CCI_REG8(0xfcbb), 0x01},
+       {CCI_REG8(0xfcbc), 0x02},
+       {CCI_REG8(0xfcbd), 0x01},
+       {CCI_REG8(0xfcbe), 0x01},
+       {CCI_REG8(0xfcbf), 0x01},
+       {CCI_REG8(0xfcc0), 0x0c},
+       {CCI_REG8(0xfcc1), 0x01},
+       {CCI_REG8(0xfcc2), 0x03},
+       {CCI_REG8(0xfcc3), 0x01},
+       {CCI_REG8(0xfcc4), 0x03},
+       {CCI_REG8(0xfcc5), 0x01},
+       {CCI_REG8(0xfcc6), 0x01},
+       {CCI_REG8(0xfcc7), 0x01},
+       {CCI_REG8(0xfcc8), 0x13},
+       {CCI_REG8(0xfcc9), 0x01},
+       {CCI_REG8(0xfcca), 0x05},
+       {CCI_REG8(0xfccb), 0x01},
+       {CCI_REG8(0xfccc), 0x04},
+       {CCI_REG8(0xfccd), 0x01},
+       {CCI_REG8(0xfcce), 0x01},
+       {CCI_REG8(0xfccf), 0x01},
+       {CCI_REG8(0xfcd0), 0x2b},
+       {CCI_REG8(0xfcd1), 0x01},
+       {CCI_REG8(0xfcd2), 0x07},
+       {CCI_REG8(0xfcd3), 0x01},
+       {CCI_REG8(0xfcd4), 0x07},
+       {CCI_REG8(0xfcd5), 0x01},
+       {CCI_REG8(0xfcd6), 0xfb},
+       {CCI_REG8(0xfcd7), 0x00},
+       {CCI_REG8(0xfcd8), 0x14},
+       {CCI_REG8(0xfcd9), 0x01},
+       {CCI_REG8(0xfcda), 0x04},
+       {CCI_REG8(0xfcdb), 0x01},
+       {CCI_REG8(0xfcdc), 0x04},
+       {CCI_REG8(0xfcdd), 0x01},
+       {CCI_REG8(0xfcde), 0x01},
+       {CCI_REG8(0xfcdf), 0x01},
+       {CCI_REG8(0xfce0), 0x44},
+       {CCI_REG8(0xfce1), 0x01},
+       {CCI_REG8(0xfce2), 0x21},
+       {CCI_REG8(0xfce3), 0x01},
+       {CCI_REG8(0xfce4), 0x21},
+       {CCI_REG8(0xfce5), 0x01},
+       {CCI_REG8(0xfce6), 0x05},
+       {CCI_REG8(0xfce7), 0x01},
+       {CCI_REG8(0xfce8), 0x1e},
+       {CCI_REG8(0xfce9), 0x01},
+       {CCI_REG8(0xfcea), 0x06},
+       {CCI_REG8(0xfceb), 0x01},
+       {CCI_REG8(0xfcec), 0x06},
+       {CCI_REG8(0xfced), 0x01},
+       {CCI_REG8(0xfcee), 0xf8},
+       {CCI_REG8(0xfcef), 0x00},
+       {CCI_REG8(0xfcf0), 0x1a},
+       {CCI_REG8(0xfcf1), 0x01},
+       {CCI_REG8(0xfcf2), 0x0d},
+       {CCI_REG8(0xfcf3), 0x01},
+       {CCI_REG8(0xfcf4), 0x0d},
+       {CCI_REG8(0xfcf5), 0x01},
+       {CCI_REG8(0xfcf6), 0x05},
+       {CCI_REG8(0xfcf7), 0x01},
+       {CCI_REG8(0xfcf8), 0x0f},
+       {CCI_REG8(0xfcf9), 0x01},
+       {CCI_REG8(0xfcfa), 0x06},
+       {CCI_REG8(0xfcfb), 0x01},
+       {CCI_REG8(0xfcfc), 0x06},
+       {CCI_REG8(0xfcfd), 0x01},
+       {CCI_REG8(0xfcfe), 0x02},
+       {CCI_REG8(0xfcff), 0x01},
+       {CCI_REG8(0xfd00), 0x0c},
+       {CCI_REG8(0xfd01), 0x01},
+       {CCI_REG8(0xfd02), 0x04},
+       {CCI_REG8(0xfd03), 0x01},
+       {CCI_REG8(0xfd04), 0x04},
+       {CCI_REG8(0xfd05), 0x01},
+       {CCI_REG8(0xfd06), 0x00},
+       {CCI_REG8(0xfd07), 0x01},
+       {CCI_REG8(0xfd08), 0x0e},
+       {CCI_REG8(0xfd09), 0x01},
+       {CCI_REG8(0xfd0a), 0x03},
+       {CCI_REG8(0xfd0b), 0x01},
+       {CCI_REG8(0xfd0c), 0x03},
+       {CCI_REG8(0xfd0d), 0x01},
+       {CCI_REG8(0xfd0e), 0x00},
+       {CCI_REG8(0xfd0f), 0x01},
+       {CCI_REG8(0xfd10), 0x14},
+       {CCI_REG8(0xfd11), 0x01},
+       {CCI_REG8(0xfd12), 0x06},
+       {CCI_REG8(0xfd13), 0x01},
+       {CCI_REG8(0xfd14), 0x06},
+       {CCI_REG8(0xfd15), 0x01},
+       {CCI_REG8(0xfd16), 0x03},
+       {CCI_REG8(0xfd17), 0x01},
+       {CCI_REG8(0xfd18), 0x20},
+       {CCI_REG8(0xfd19), 0x01},
+       {CCI_REG8(0xfd1a), 0x07},
+       {CCI_REG8(0xfd1b), 0x01},
+       {CCI_REG8(0xfd1c), 0x07},
+       {CCI_REG8(0xfd1d), 0x01},
+       {CCI_REG8(0xfd1e), 0x01},
+       {CCI_REG8(0xfd1f), 0x01},
+       {CCI_REG8(0xfd20), 0x32},
+       {CCI_REG8(0xfd21), 0x01},
+       {CCI_REG8(0xfd22), 0x05},
+       {CCI_REG8(0xfd23), 0x01},
+       {CCI_REG8(0xfd24), 0x04},
+       {CCI_REG8(0xfd25), 0x01},
+       {CCI_REG8(0xfd26), 0xf5},
+       {CCI_REG8(0xfd27), 0x00},
+       {CCI_REG8(0xfd28), 0x1f},
+       {CCI_REG8(0xfd29), 0x01},
+       {CCI_REG8(0xfd2a), 0x05},
+       {CCI_REG8(0xfd2b), 0x01},
+       {CCI_REG8(0xfd2c), 0x05},
+       {CCI_REG8(0xfd2d), 0x01},
+       {CCI_REG8(0xfd2e), 0xfe},
+       {CCI_REG8(0xfd2f), 0x00},
+       {CCI_REG8(0xfd30), 0xfa},
+       {CCI_REG8(0xfd31), 0x00},
+       {CCI_REG8(0xfd32), 0xe2},
+       {CCI_REG8(0xfd33), 0x00},
+       {CCI_REG8(0xfd34), 0xe2},
+       {CCI_REG8(0xfd35), 0x00},
+       {CCI_REG8(0xfd36), 0xda},
+       {CCI_REG8(0xfd37), 0x00},
+       {CCI_REG8(0xfd38), 0x17},
+       {CCI_REG8(0xfd39), 0x01},
+       {CCI_REG8(0xfd3a), 0x0d},
+       {CCI_REG8(0xfd3b), 0x01},
+       {CCI_REG8(0xfd3c), 0x0d},
+       {CCI_REG8(0xfd3d), 0x01},
+       {CCI_REG8(0xfd3e), 0x07},
+       {CCI_REG8(0xfd3f), 0x01},
+       {CCI_REG8(0xfd40), 0xff},
+       {CCI_REG8(0xfd41), 0x00},
+       {CCI_REG8(0xfd42), 0x00},
+       {CCI_REG8(0xfd43), 0x01},
+       {CCI_REG8(0xfd44), 0x00},
+       {CCI_REG8(0xfd45), 0x01},
+       {CCI_REG8(0xfd46), 0x00},
+       {CCI_REG8(0xfd47), 0x01},
+       {CCI_REG8(0xfd48), 0x00},
+       {CCI_REG8(0xfd49), 0x01},
+       {CCI_REG8(0xfd4a), 0x01},
+       {CCI_REG8(0xfd4b), 0x01},
+       {CCI_REG8(0xfd4c), 0x02},
+       {CCI_REG8(0xfd4d), 0x01},
+       {CCI_REG8(0xfd4e), 0xfe},
+       {CCI_REG8(0xfd4f), 0x00},
+       {CCI_REG8(0xfd50), 0xf8},
+       {CCI_REG8(0xfd51), 0x00},
+       {CCI_REG8(0xfd52), 0xfc},
+       {CCI_REG8(0xfd53), 0x00},
+       {CCI_REG8(0xfd54), 0xfc},
+       {CCI_REG8(0xfd55), 0x00},
+       {CCI_REG8(0xfd56), 0xfe},
+       {CCI_REG8(0xfd57), 0x00},
+       {CCI_REG8(0xfd58), 0xfc},
+       {CCI_REG8(0xfd59), 0x00},
+       {CCI_REG8(0xfd5a), 0x00},
+       {CCI_REG8(0xfd5b), 0x01},
+       {CCI_REG8(0xfd5c), 0x01},
+       {CCI_REG8(0xfd5d), 0x01},
+       {CCI_REG8(0xfd5e), 0x01},
+       {CCI_REG8(0xfd5f), 0x01},
+       {CCI_REG8(0xfd60), 0x00},
+       {CCI_REG8(0xfd61), 0x01},
+       {CCI_REG8(0xfd62), 0xff},
+       {CCI_REG8(0xfd63), 0x00},
+       {CCI_REG8(0xfd64), 0x00},
+       {CCI_REG8(0xfd65), 0x01},
+       {CCI_REG8(0xfd66), 0xfe},
+       {CCI_REG8(0xfd67), 0x00},
+       {CCI_REG8(0xfd68), 0x03},
+       {CCI_REG8(0xfd69), 0x01},
+       {CCI_REG8(0xfd6a), 0x01},
+       {CCI_REG8(0xfd6b), 0x01},
+       {CCI_REG8(0xfd6c), 0x02},
+       {CCI_REG8(0xfd6d), 0x01},
+       {CCI_REG8(0xfd6e), 0x01},
+       {CCI_REG8(0xfd6f), 0x01},
+       {CCI_REG8(0xfd70), 0x20},
+       {CCI_REG8(0xfd71), 0x01},
+       {CCI_REG8(0xfd72), 0x0a},
+       {CCI_REG8(0xfd73), 0x01},
+       {CCI_REG8(0xfd74), 0x0a},
+       {CCI_REG8(0xfd75), 0x01},
+       {CCI_REG8(0xfd76), 0x02},
+       {CCI_REG8(0xfd77), 0x01},
+       {CCI_REG8(0xfd78), 0x06},
+       {CCI_REG8(0xfd79), 0x01},
+       {CCI_REG8(0xfd7a), 0x03},
+       {CCI_REG8(0xfd7b), 0x01},
+       {CCI_REG8(0xfd7c), 0x02},
+       {CCI_REG8(0xfd7d), 0x01},
+       {CCI_REG8(0xfd7e), 0x03},
+       {CCI_REG8(0xfd7f), 0x01},
+       {CCI_REG8(0xfd80), 0x54},
+       {CCI_REG8(0xfd81), 0x01},
+       {CCI_REG8(0xfd82), 0x22},
+       {CCI_REG8(0xfd83), 0x01},
+       {CCI_REG8(0xfd84), 0x22},
+       {CCI_REG8(0xfd85), 0x01},
+       {CCI_REG8(0xfd86), 0x13},
+       {CCI_REG8(0xfd87), 0x01},
+       {CCI_REG8(0xfd88), 0x1e},
+       {CCI_REG8(0xfd89), 0x01},
+       {CCI_REG8(0xfd8a), 0xff},
+       {CCI_REG8(0xfd8b), 0x00},
+       {CCI_REG8(0xfd8c), 0xfe},
+       {CCI_REG8(0xfd8d), 0x00},
+       {CCI_REG8(0xfd8e), 0xf9},
+       {CCI_REG8(0xfd8f), 0x00},
+       {CCI_REG8(0xfd90), 0x1a},
+       {CCI_REG8(0xfd91), 0x01},
+       {CCI_REG8(0xfd92), 0x06},
+       {CCI_REG8(0xfd93), 0x01},
+       {CCI_REG8(0xfd94), 0x06},
+       {CCI_REG8(0xfd95), 0x01},
+       {CCI_REG8(0xfd96), 0x02},
+       {CCI_REG8(0xfd97), 0x01},
+       {CCI_REG8(0xfd98), 0x0c},
+       {CCI_REG8(0xfd99), 0x01},
+       {CCI_REG8(0xfd9a), 0x02},
+       {CCI_REG8(0xfd9b), 0x01},
+       {CCI_REG8(0xfd9c), 0x01},
+       {CCI_REG8(0xfd9d), 0x01},
+       {CCI_REG8(0xfd9e), 0x01},
+       {CCI_REG8(0xfd9f), 0x01},
+       {CCI_REG8(0xfda0), 0x0a},
+       {CCI_REG8(0xfda1), 0x01},
+       {CCI_REG8(0xfda2), 0x01},
+       {CCI_REG8(0xfda3), 0x01},
+       {CCI_REG8(0xfda4), 0x01},
+       {CCI_REG8(0xfda5), 0x01},
+       {CCI_REG8(0xfda6), 0x00},
+       {CCI_REG8(0xfda7), 0x01},
+       {CCI_REG8(0xfda8), 0x09},
+       {CCI_REG8(0xfda9), 0x01},
+       {CCI_REG8(0xfdaa), 0x00},
+       {CCI_REG8(0xfdab), 0x01},
+       {CCI_REG8(0xfdac), 0xff},
+       {CCI_REG8(0xfdad), 0x00},
+       {CCI_REG8(0xfdae), 0xfe},
+       {CCI_REG8(0xfdaf), 0x00},
+       {CCI_REG8(0xfdb0), 0x0e},
+       {CCI_REG8(0xfdb1), 0x01},
+       {CCI_REG8(0xfdb2), 0x01},
+       {CCI_REG8(0xfdb3), 0x01},
+       {CCI_REG8(0xfdb4), 0x02},
+       {CCI_REG8(0xfdb5), 0x01},
+       {CCI_REG8(0xfdb6), 0x00},
+       {CCI_REG8(0xfdb7), 0x01},
+       {CCI_REG8(0xfdb8), 0x1b},
+       {CCI_REG8(0xfdb9), 0x01},
+       {CCI_REG8(0xfdba), 0x05},
+       {CCI_REG8(0xfdbb), 0x01},
+       {CCI_REG8(0xfdbc), 0x05},
+       {CCI_REG8(0xfdbd), 0x01},
+       {CCI_REG8(0xfdbe), 0xff},
+       {CCI_REG8(0xfdbf), 0x00},
+       {CCI_REG8(0xfdc0), 0x35},
+       {CCI_REG8(0xfdc1), 0x01},
+       {CCI_REG8(0xfdc2), 0x0d},
+       {CCI_REG8(0xfdc3), 0x01},
+       {CCI_REG8(0xfdc4), 0x0d},
+       {CCI_REG8(0xfdc5), 0x01},
+       {CCI_REG8(0xfdc6), 0x00},
+       {CCI_REG8(0xfdc7), 0x01},
+       {CCI_REG8(0xfdc8), 0x1b},
+       {CCI_REG8(0xfdc9), 0x01},
+       {CCI_REG8(0xfdca), 0x04},
+       {CCI_REG8(0xfdcb), 0x01},
+       {CCI_REG8(0xfdcc), 0x04},
+       {CCI_REG8(0xfdcd), 0x01},
+       {CCI_REG8(0xfdce), 0xfd},
+       {CCI_REG8(0xfdcf), 0x00},
+       {CCI_REG8(0xfdd0), 0x25},
+       {CCI_REG8(0xfdd1), 0x01},
+       {CCI_REG8(0xfdd2), 0x00},
+       {CCI_REG8(0xfdd3), 0x01},
+       {CCI_REG8(0xfdd4), 0x00},
+       {CCI_REG8(0xfdd5), 0x01},
+       {CCI_REG8(0xfdd6), 0xf7},
+       {CCI_REG8(0xfdd7), 0x00},
+       {CCI_REG8(0xfdd8), 0x17},
+       {CCI_REG8(0xfdd9), 0x01},
+       {CCI_REG8(0xfdda), 0x00},
+       {CCI_REG8(0xfddb), 0x01},
+       {CCI_REG8(0xfddc), 0x00},
+       {CCI_REG8(0xfddd), 0x01},
+       {CCI_REG8(0xfdde), 0xfa},
+       {CCI_REG8(0xfddf), 0x00},
+       {CCI_REG8(0xfde0), 0x0b},
+       {CCI_REG8(0xfde1), 0x01},
+       {CCI_REG8(0xfde2), 0x01},
+       {CCI_REG8(0xfde3), 0x01},
+       {CCI_REG8(0xfde4), 0x00},
+       {CCI_REG8(0xfde5), 0x01},
+       {CCI_REG8(0xfde6), 0xfe},
+       {CCI_REG8(0xfde7), 0x00},
+       {CCI_REG8(0xfde8), 0x05},
+       {CCI_REG8(0xfde9), 0x01},
+       {CCI_REG8(0xfdea), 0xff},
+       {CCI_REG8(0xfdeb), 0x00},
+       {CCI_REG8(0xfdec), 0xfe},
+       {CCI_REG8(0xfded), 0x00},
+       {CCI_REG8(0xfdee), 0xfd},
+       {CCI_REG8(0xfdef), 0x00},
+       {CCI_REG8(0xfdf0), 0x03},
+       {CCI_REG8(0xfdf1), 0x01},
+       {CCI_REG8(0xfdf2), 0x00},
+       {CCI_REG8(0xfdf3), 0x01},
+       {CCI_REG8(0xfdf4), 0xff},
+       {CCI_REG8(0xfdf5), 0x00},
+       {CCI_REG8(0xfdf6), 0xfe},
+       {CCI_REG8(0xfdf7), 0x00},
+       {CCI_REG8(0xfdf8), 0x05},
+       {CCI_REG8(0xfdf9), 0x01},
+       {CCI_REG8(0xfdfa), 0x02},
+       {CCI_REG8(0xfdfb), 0x01},
+       {CCI_REG8(0xfdfc), 0x02},
+       {CCI_REG8(0xfdfd), 0x01},
+       {CCI_REG8(0xfdfe), 0x00},
+       {CCI_REG8(0xfdff), 0x01},
+       {CCI_REG8(0xfe00), 0x08},
+       {CCI_REG8(0xfe01), 0x01},
+       {CCI_REG8(0xfe02), 0x01},
+       {CCI_REG8(0xfe03), 0x01},
+       {CCI_REG8(0xfe04), 0x01},
+       {CCI_REG8(0xfe05), 0x01},
+       {CCI_REG8(0xfe06), 0xfe},
+       {CCI_REG8(0xfe07), 0x00},
+       {CCI_REG8(0xfe08), 0x0d},
+       {CCI_REG8(0xfe09), 0x01},
+       {CCI_REG8(0xfe0a), 0x00},
+       {CCI_REG8(0xfe0b), 0x01},
+       {CCI_REG8(0xfe0c), 0x00},
+       {CCI_REG8(0xfe0d), 0x01},
+       {CCI_REG8(0xfe0e), 0xfd},
+       {CCI_REG8(0xfe0f), 0x00},
+       {CCI_REG8(0xfe10), 0x25},
+       {CCI_REG8(0xfe11), 0x01},
+       {CCI_REG8(0xfe12), 0x05},
+       {CCI_REG8(0xfe13), 0x01},
+       {CCI_REG8(0xfe14), 0x05},
+       {CCI_REG8(0xfe15), 0x01},
+       {CCI_REG8(0xfe16), 0xfe},
+       {CCI_REG8(0xfe17), 0x00},
+       {CCI_REG8(0xfe18), 0x0d},
+       {CCI_REG8(0xfe19), 0x01},
+       {CCI_REG8(0xfe1a), 0xff},
+       {CCI_REG8(0xfe1b), 0x00},
+       {CCI_REG8(0xfe1c), 0x00},
+       {CCI_REG8(0xfe1d), 0x01},
+       {CCI_REG8(0xfe1e), 0xfd},
+       {CCI_REG8(0xfe1f), 0x00},
+       {CCI_REG8(0xfe20), 0x23},
+       {CCI_REG8(0xfe21), 0x01},
+       {CCI_REG8(0xfe22), 0x00},
+       {CCI_REG8(0xfe23), 0x01},
+       {CCI_REG8(0xfe24), 0x00},
+       {CCI_REG8(0xfe25), 0x01},
+       {CCI_REG8(0xfe26), 0xf8},
+       {CCI_REG8(0xfe27), 0x00},
+       {CCI_REG8(0xfe28), 0x12},
+       {CCI_REG8(0xfe29), 0x01},
+       {CCI_REG8(0xfe2a), 0x00},
+       {CCI_REG8(0xfe2b), 0x01},
+       {CCI_REG8(0xfe2c), 0x00},
+       {CCI_REG8(0xfe2d), 0x01},
+       {CCI_REG8(0xfe2e), 0xfb},
+       {CCI_REG8(0xfe2f), 0x00},
+       {CCI_REG8(0xfe30), 0x06},
+       {CCI_REG8(0xfe31), 0x01},
+       {CCI_REG8(0xfe32), 0xff},
+       {CCI_REG8(0xfe33), 0x00},
+       {CCI_REG8(0xfe34), 0xff},
+       {CCI_REG8(0xfe35), 0x00},
+       {CCI_REG8(0xfe36), 0xfc},
+       {CCI_REG8(0xfe37), 0x00},
+       {CCI_REG8(0xfe38), 0x03},
+       {CCI_REG8(0xfe39), 0x01},
+       {CCI_REG8(0xfe3a), 0x01},
+       {CCI_REG8(0xfe3b), 0x01},
+       {CCI_REG8(0xfe3c), 0x00},
+       {CCI_REG8(0xfe3d), 0x01},
+       {CCI_REG8(0xfe3e), 0xff},
+       {CCI_REG8(0xfe3f), 0x00},
+       {CCI_REG8(0xfe40), 0x00},
+       {CCI_REG8(0xfe41), 0x01},
+       {CCI_REG8(0xfe42), 0x00},
+       {CCI_REG8(0xfe43), 0x01},
+       {CCI_REG8(0xfe44), 0x00},
+       {CCI_REG8(0xfe45), 0x01},
+       {CCI_REG8(0xfe46), 0x00},
+       {CCI_REG8(0xfe47), 0x01},
+       {CCI_REG8(0xfe48), 0x00},
+       {CCI_REG8(0xfe49), 0x01},
+       {CCI_REG8(0xfe4a), 0x00},
+       {CCI_REG8(0xfe4b), 0x01},
+       {CCI_REG8(0xfe4c), 0x00},
+       {CCI_REG8(0xfe4d), 0x01},
+       {CCI_REG8(0xfe4e), 0xff},
+       {CCI_REG8(0xfe4f), 0x00},
+       {CCI_REG8(0xfe50), 0x07},
+       {CCI_REG8(0xfe51), 0x01},
+       {CCI_REG8(0xfe52), 0x03},
+       {CCI_REG8(0xfe53), 0x01},
+       {CCI_REG8(0xfe54), 0x03},
+       {CCI_REG8(0xfe55), 0x01},
+       {CCI_REG8(0xfe56), 0x01},
+       {CCI_REG8(0xfe57), 0x01},
+       {CCI_REG8(0xfe58), 0x0a},
+       {CCI_REG8(0xfe59), 0x01},
+       {CCI_REG8(0xfe5a), 0x00},
+       {CCI_REG8(0xfe5b), 0x01},
+       {CCI_REG8(0xfe5c), 0x00},
+       {CCI_REG8(0xfe5d), 0x01},
+       {CCI_REG8(0xfe5e), 0xfe},
+       {CCI_REG8(0xfe5f), 0x00},
+       {CCI_REG8(0xfe60), 0x1d},
+       {CCI_REG8(0xfe61), 0x01},
+       {CCI_REG8(0xfe62), 0x01},
+       {CCI_REG8(0xfe63), 0x01},
+       {CCI_REG8(0xfe64), 0x02},
+       {CCI_REG8(0xfe65), 0x01},
+       {CCI_REG8(0xfe66), 0xfc},
+       {CCI_REG8(0xfe67), 0x00},
+       {CCI_REG8(0xfe68), 0x0b},
+       {CCI_REG8(0xfe69), 0x01},
+       {CCI_REG8(0xfe6a), 0x00},
+       {CCI_REG8(0xfe6b), 0x01},
+       {CCI_REG8(0xfe6c), 0x01},
+       {CCI_REG8(0xfe6d), 0x01},
+       {CCI_REG8(0xfe6e), 0xfe},
+       {CCI_REG8(0xfe6f), 0x00},
+       {CCI_REG8(0xfe70), 0x20},
+       {CCI_REG8(0xfe71), 0x01},
+       {CCI_REG8(0xfe72), 0xfe},
+       {CCI_REG8(0xfe73), 0x00},
+       {CCI_REG8(0xfe74), 0xfd},
+       {CCI_REG8(0xfe75), 0x00},
+       {CCI_REG8(0xfe76), 0xf5},
+       {CCI_REG8(0xfe77), 0x00},
+       {CCI_REG8(0xfe78), 0x12},
+       {CCI_REG8(0xfe79), 0x01},
+       {CCI_REG8(0xfe7a), 0x01},
+       {CCI_REG8(0xfe7b), 0x01},
+       {CCI_REG8(0xfe7c), 0x01},
+       {CCI_REG8(0xfe7d), 0x01},
+       {CCI_REG8(0xfe7e), 0xfd},
+       {CCI_REG8(0xfe7f), 0x00},
+       {CCI_REG8(0xfe80), 0x08},
+       {CCI_REG8(0xfe81), 0x01},
+       {CCI_REG8(0xfe82), 0x02},
+       {CCI_REG8(0xfe83), 0x01},
+       {CCI_REG8(0xfe84), 0x02},
+       {CCI_REG8(0xfe85), 0x01},
+       {CCI_REG8(0xfe86), 0xff},
+       {CCI_REG8(0xfe87), 0x00},
+       {CCI_REG8(0xfe88), 0x01},
+       {CCI_REG8(0xfe89), 0x01},
+       {CCI_REG8(0xfe8a), 0x00},
+       {CCI_REG8(0xfe8b), 0x01},
+       {CCI_REG8(0xfe8c), 0xff},
+       {CCI_REG8(0xfe8d), 0x00},
+       {CCI_REG8(0xfe8e), 0xfe},
+       {CCI_REG8(0xfe8f), 0x00},
+       {CCI_REG8(0xfe90), 0x00},
+       {CCI_REG8(0xfe91), 0x01},
+       {CCI_REG8(0xfe92), 0x01},
+       {CCI_REG8(0xfe93), 0x01},
+       {CCI_REG8(0xfe94), 0x01},
+       {CCI_REG8(0xfe95), 0x01},
+       {CCI_REG8(0xfe96), 0x01},
+       {CCI_REG8(0xfe97), 0x01},
+       {CCI_REG8(0xfe98), 0xff},
+       {CCI_REG8(0xfe99), 0x00},
+       {CCI_REG8(0xfe9a), 0xff},
+       {CCI_REG8(0xfe9b), 0x00},
+       {CCI_REG8(0xfe9c), 0xff},
+       {CCI_REG8(0xfe9d), 0x00},
+       {CCI_REG8(0xfe9e), 0xff},
+       {CCI_REG8(0xfe9f), 0x00},
+       {CCI_REG8(0xfea0), 0x05},
+       {CCI_REG8(0xfea1), 0x01},
+       {CCI_REG8(0xfea2), 0x01},
+       {CCI_REG8(0xfea3), 0x01},
+       {CCI_REG8(0xfea4), 0x01},
+       {CCI_REG8(0xfea5), 0x01},
+       {CCI_REG8(0xfea6), 0x00},
+       {CCI_REG8(0xfea7), 0x01},
+       {CCI_REG8(0xfea8), 0x09},
+       {CCI_REG8(0xfea9), 0x01},
+       {CCI_REG8(0xfeaa), 0x00},
+       {CCI_REG8(0xfeab), 0x01},
+       {CCI_REG8(0xfeac), 0x00},
+       {CCI_REG8(0xfead), 0x01},
+       {CCI_REG8(0xfeae), 0xfe},
+       {CCI_REG8(0xfeaf), 0x00},
+       {CCI_REG8(0xfeb0), 0x1a},
+       {CCI_REG8(0xfeb1), 0x01},
+       {CCI_REG8(0xfeb2), 0xfe},
+       {CCI_REG8(0xfeb3), 0x00},
+       {CCI_REG8(0xfeb4), 0xff},
+       {CCI_REG8(0xfeb5), 0x00},
+       {CCI_REG8(0xfeb6), 0xfa},
+       {CCI_REG8(0xfeb7), 0x00},
+       {CCI_REG8(0xfeb8), 0x0b},
+       {CCI_REG8(0xfeb9), 0x01},
+       {CCI_REG8(0xfeba), 0x00},
+       {CCI_REG8(0xfebb), 0x01},
+       {CCI_REG8(0xfebc), 0x00},
+       {CCI_REG8(0xfebd), 0x01},
+       {CCI_REG8(0xfebe), 0xff},
+       {CCI_REG8(0xfebf), 0x00},
+       {CCI_REG8(0xfec0), 0x1e},
+       {CCI_REG8(0xfec1), 0x01},
+       {CCI_REG8(0xfec2), 0xfb},
+       {CCI_REG8(0xfec3), 0x00},
+       {CCI_REG8(0xfec4), 0xfb},
+       {CCI_REG8(0xfec5), 0x00},
+       {CCI_REG8(0xfec6), 0xf2},
+       {CCI_REG8(0xfec7), 0x00},
+       {CCI_REG8(0xfec8), 0x16},
+       {CCI_REG8(0xfec9), 0x01},
+       {CCI_REG8(0xfeca), 0x01},
+       {CCI_REG8(0xfecb), 0x01},
+       {CCI_REG8(0xfecc), 0x00},
+       {CCI_REG8(0xfecd), 0x01},
+       {CCI_REG8(0xfece), 0xfa},
+       {CCI_REG8(0xfecf), 0x00},
+       {CCI_REG8(0xfed0), 0x09},
+       {CCI_REG8(0xfed1), 0x01},
+       {CCI_REG8(0xfed2), 0x00},
+       {CCI_REG8(0xfed3), 0x01},
+       {CCI_REG8(0xfed4), 0x00},
+       {CCI_REG8(0xfed5), 0x01},
+       {CCI_REG8(0xfed6), 0xfd},
+       {CCI_REG8(0xfed7), 0x00},
+       {CCI_REG8(0xfed8), 0x06},
+       {CCI_REG8(0xfed9), 0x01},
+       {CCI_REG8(0xfeda), 0x01},
+       {CCI_REG8(0xfedb), 0x01},
+       {CCI_REG8(0xfedc), 0x01},
+       {CCI_REG8(0xfedd), 0x01},
+       {CCI_REG8(0xfede), 0xff},
+       {CCI_REG8(0xfedf), 0x00},
+       {CCI_REG8(0xfee0), 0x01},
+       {CCI_REG8(0xfee1), 0x01},
+       {CCI_REG8(0xfee2), 0xfe},
+       {CCI_REG8(0xfee3), 0x00},
+       {CCI_REG8(0xfee4), 0xfe},
+       {CCI_REG8(0xfee5), 0x00},
+       {CCI_REG8(0xfee6), 0xfe},
+       {CCI_REG8(0xfee7), 0x00},
+       {CCI_REG8(0xfee8), 0x03},
+       {CCI_REG8(0xfee9), 0x01},
+       {CCI_REG8(0xfeea), 0x00},
+       {CCI_REG8(0xfeeb), 0x01},
+       {CCI_REG8(0xfeec), 0x00},
+       {CCI_REG8(0xfeed), 0x01},
+       {CCI_REG8(0xfeee), 0xff},
+       {CCI_REG8(0xfeef), 0x00},
+       {CCI_REG8(0xfef0), 0x07},
+       {CCI_REG8(0xfef1), 0x01},
+       {CCI_REG8(0xfef2), 0x00},
+       {CCI_REG8(0xfef3), 0x01},
+       {CCI_REG8(0xfef4), 0x00},
+       {CCI_REG8(0xfef5), 0x01},
+       {CCI_REG8(0xfef6), 0xff},
+       {CCI_REG8(0xfef7), 0x00},
+       {CCI_REG8(0xfef8), 0x0c},
+       {CCI_REG8(0xfef9), 0x01},
+       {CCI_REG8(0xfefa), 0xff},
+       {CCI_REG8(0xfefb), 0x00},
+       {CCI_REG8(0xfefc), 0xff},
+       {CCI_REG8(0xfefd), 0x00},
+       {CCI_REG8(0xfefe), 0xfd},
+       {CCI_REG8(0xfeff), 0x00},
+       {CCI_REG8(0xff00), 0x20},
+       {CCI_REG8(0xff01), 0x01},
+       {CCI_REG8(0xff02), 0xff},
+       {CCI_REG8(0xff03), 0x00},
+       {CCI_REG8(0xff04), 0x00},
+       {CCI_REG8(0xff05), 0x01},
+       {CCI_REG8(0xff06), 0xfa},
+       {CCI_REG8(0xff07), 0x00},
+       {CCI_REG8(0xff08), 0x0d},
+       {CCI_REG8(0xff09), 0x01},
+       {CCI_REG8(0xff0a), 0xff},
+       {CCI_REG8(0xff0b), 0x00},
+       {CCI_REG8(0xff0c), 0xff},
+       {CCI_REG8(0xff0d), 0x00},
+       {CCI_REG8(0xff0e), 0xfd},
+       {CCI_REG8(0xff0f), 0x00},
+       {CCI_REG8(0xff10), 0x3c},
+       {CCI_REG8(0xff11), 0x01},
+       {CCI_REG8(0xff12), 0x10},
+       {CCI_REG8(0xff13), 0x01},
+       {CCI_REG8(0xff14), 0x0f},
+       {CCI_REG8(0xff15), 0x01},
+       {CCI_REG8(0xff16), 0x01},
+       {CCI_REG8(0xff17), 0x01},
+       {CCI_REG8(0xff18), 0x19},
+       {CCI_REG8(0xff19), 0x01},
+       {CCI_REG8(0xff1a), 0xfc},
+       {CCI_REG8(0xff1b), 0x00},
+       {CCI_REG8(0xff1c), 0xfb},
+       {CCI_REG8(0xff1d), 0x00},
+       {CCI_REG8(0xff1e), 0xf5},
+       {CCI_REG8(0xff1f), 0x00},
+       {CCI_REG8(0xff20), 0x14},
+       {CCI_REG8(0xff21), 0x01},
+       {CCI_REG8(0xff22), 0x04},
+       {CCI_REG8(0xff23), 0x01},
+       {CCI_REG8(0xff24), 0x03},
+       {CCI_REG8(0xff25), 0x01},
+       {CCI_REG8(0xff26), 0xfe},
+       {CCI_REG8(0xff27), 0x00},
+       {CCI_REG8(0xff28), 0x0a},
+       {CCI_REG8(0xff29), 0x01},
+       {CCI_REG8(0xff2a), 0x01},
+       {CCI_REG8(0xff2b), 0x01},
+       {CCI_REG8(0xff2c), 0x01},
+       {CCI_REG8(0xff2d), 0x01},
+       {CCI_REG8(0xff2e), 0xff},
+       {CCI_REG8(0xff2f), 0x00},
+       {CCI_REG8(0xff30), 0x08},
+       {CCI_REG8(0xff31), 0x01},
+       {CCI_REG8(0xff32), 0x00},
+       {CCI_REG8(0xff33), 0x01},
+       {CCI_REG8(0xff34), 0xff},
+       {CCI_REG8(0xff35), 0x00},
+       {CCI_REG8(0xff36), 0xfe},
+       {CCI_REG8(0xff37), 0x00},
+       {CCI_REG8(0xff38), 0x07},
+       {CCI_REG8(0xff39), 0x01},
+       {CCI_REG8(0xff3a), 0xfe},
+       {CCI_REG8(0xff3b), 0x00},
+       {CCI_REG8(0xff3c), 0xfe},
+       {CCI_REG8(0xff3d), 0x00},
+       {CCI_REG8(0xff3e), 0xfd},
+       {CCI_REG8(0xff3f), 0x00},
+       {CCI_REG8(0xff40), 0x0c},
+       {CCI_REG8(0xff41), 0x01},
+       {CCI_REG8(0xff42), 0xff},
+       {CCI_REG8(0xff43), 0x00},
+       {CCI_REG8(0xff44), 0xff},
+       {CCI_REG8(0xff45), 0x00},
+       {CCI_REG8(0xff46), 0xfe},
+       {CCI_REG8(0xff47), 0x00},
+       {CCI_REG8(0xff48), 0x17},
+       {CCI_REG8(0xff49), 0x01},
+       {CCI_REG8(0xff4a), 0x00},
+       {CCI_REG8(0xff4b), 0x01},
+       {CCI_REG8(0xff4c), 0x00},
+       {CCI_REG8(0xff4d), 0x01},
+       {CCI_REG8(0xff4e), 0xfd},
+       {CCI_REG8(0xff4f), 0x00},
+       {CCI_REG8(0xff50), 0x25},
+       {CCI_REG8(0xff51), 0x01},
+       {CCI_REG8(0xff52), 0xfc},
+       {CCI_REG8(0xff53), 0x00},
+       {CCI_REG8(0xff54), 0xfd},
+       {CCI_REG8(0xff55), 0x00},
+       {CCI_REG8(0xff56), 0xf5},
+       {CCI_REG8(0xff57), 0x00},
+       {CCI_REG8(0xff58), 0x16},
+       {CCI_REG8(0xff59), 0x01},
+       {CCI_REG8(0xff5a), 0xfe},
+       {CCI_REG8(0xff5b), 0x00},
+       {CCI_REG8(0xff5c), 0xfe},
+       {CCI_REG8(0xff5d), 0x00},
+       {CCI_REG8(0xff5e), 0xfb},
+       {CCI_REG8(0xff5f), 0x00},
+       {CCI_REG8(0xff60), 0xf6},
+       {CCI_REG8(0xff61), 0x00},
+       {CCI_REG8(0xff62), 0xdf},
+       {CCI_REG8(0xff63), 0x00},
+       {CCI_REG8(0xff64), 0xdf},
+       {CCI_REG8(0xff65), 0x00},
+       {CCI_REG8(0xff66), 0xdc},
+       {CCI_REG8(0xff67), 0x00},
+       {CCI_REG8(0xff68), 0x12},
+       {CCI_REG8(0xff69), 0x01},
+       {CCI_REG8(0xff6a), 0x06},
+       {CCI_REG8(0xff6b), 0x01},
+       {CCI_REG8(0xff6c), 0x06},
+       {CCI_REG8(0xff6d), 0x01},
+       {CCI_REG8(0xff6e), 0x02},
+       {CCI_REG8(0xff6f), 0x01},
+       {CCI_REG8(0xff70), 0xfd},
+       {CCI_REG8(0xff71), 0x00},
+       {CCI_REG8(0xff72), 0xfd},
+       {CCI_REG8(0xff73), 0x00},
+       {CCI_REG8(0xff74), 0xfd},
+       {CCI_REG8(0xff75), 0x00},
+       {CCI_REG8(0xff76), 0xfd},
+       {CCI_REG8(0xff77), 0x00},
+       {CCI_REG8(0xff78), 0x00},
+       {CCI_REG8(0xff79), 0x01},
+       {CCI_REG8(0xff7a), 0x01},
+       {CCI_REG8(0xff7b), 0x01},
+       {CCI_REG8(0xff7c), 0x01},
+       {CCI_REG8(0xff7d), 0x01},
+       {CCI_REG8(0xff7e), 0xff},
+       {CCI_REG8(0xff7f), 0x00},
+       {CCI_REG8(0xff80), 0xf8},
+       {CCI_REG8(0xff81), 0x00},
+       {CCI_REG8(0xff82), 0xfd},
+       {CCI_REG8(0xff83), 0x00},
+       {CCI_REG8(0xff84), 0xfd},
+       {CCI_REG8(0xff85), 0x00},
+       {CCI_REG8(0xff86), 0xfe},
+       {CCI_REG8(0xff87), 0x00},
+       {CCI_REG8(0xff88), 0xfd},
+       {CCI_REG8(0xff89), 0x00},
+       {CCI_REG8(0xff8a), 0x01},
+       {CCI_REG8(0xff8b), 0x01},
+       {CCI_REG8(0xff8c), 0x01},
+       {CCI_REG8(0xff8d), 0x01},
+       {CCI_REG8(0xff8e), 0x01},
+       {CCI_REG8(0xff8f), 0x01},
+       {CCI_REG8(0xff90), 0x01},
+       {CCI_REG8(0xff91), 0x01},
+       {CCI_REG8(0xff92), 0x00},
+       {CCI_REG8(0xff93), 0x01},
+       {CCI_REG8(0xff94), 0x01},
+       {CCI_REG8(0xff95), 0x01},
+       {CCI_REG8(0xff96), 0x00},
+       {CCI_REG8(0xff97), 0x01},
+       {CCI_REG8(0xff98), 0xff},
+       {CCI_REG8(0xff99), 0x00},
+       {CCI_REG8(0xff9a), 0xfd},
+       {CCI_REG8(0xff9b), 0x00},
+       {CCI_REG8(0xff9c), 0xfe},
+       {CCI_REG8(0xff9d), 0x00},
+       {CCI_REG8(0xff9e), 0xfd},
+       {CCI_REG8(0xff9f), 0x00},
+       {CCI_REG8(0xffa0), 0x18},
+       {CCI_REG8(0xffa1), 0x01},
+       {CCI_REG8(0xffa2), 0x01},
+       {CCI_REG8(0xffa3), 0x01},
+       {CCI_REG8(0xffa4), 0x02},
+       {CCI_REG8(0xffa5), 0x01},
+       {CCI_REG8(0xffa6), 0x00},
+       {CCI_REG8(0xffa7), 0x01},
+       {CCI_REG8(0xffa8), 0x02},
+       {CCI_REG8(0xffa9), 0x01},
+       {CCI_REG8(0xffaa), 0x00},
+       {CCI_REG8(0xffab), 0x01},
+       {CCI_REG8(0xffac), 0x00},
+       {CCI_REG8(0xffad), 0x01},
+       {CCI_REG8(0xffae), 0x00},
+       {CCI_REG8(0xffaf), 0x01},
+       {CCI_REG8(0xffff), 0x00},
+       {CCI_REG8(0x9bfa), 0x01},
+       {CCI_REG8(0x9bfb), 0x00},
+       {CCI_REG8(0x9cbc), 0xab},
+       {CCI_REG8(0x9cbd), 0x0f},
+       {CCI_REG8(0x9cbe), 0xab},
+       {CCI_REG8(0x9cbf), 0x0f},
+       {CCI_REG8(0x9cc0), 0xca},
+       {CCI_REG8(0x9cc1), 0x0f},
+       {CCI_REG8(0x9cc2), 0xca},
+       {CCI_REG8(0x9cc3), 0x0f},
+       {CCI_REG8(0x9cc4), 0xc8},
+       {CCI_REG8(0x9cc5), 0x0f},
+       {CCI_REG8(0x9cc6), 0xc8},
+       {CCI_REG8(0x9cc7), 0x0f},
+       {CCI_REG8(0x9cc8), 0xb0},
+       {CCI_REG8(0x9cc9), 0x0f},
+       {CCI_REG8(0x9cca), 0xb0},
+       {CCI_REG8(0x9ccb), 0x0f},
+       {CCI_REG8(0x9ccc), 0x94},
+       {CCI_REG8(0x9ccd), 0x0f},
+       {CCI_REG8(0x9cce), 0x94},
+       {CCI_REG8(0x9ccf), 0x0f},
+       {CCI_REG8(0x9cd0), 0x83},
+       {CCI_REG8(0x9cd1), 0x0f},
+       {CCI_REG8(0x9cd2), 0x83},
+       {CCI_REG8(0x9cd3), 0x0f},
+       {CCI_REG8(0x9cd4), 0x80},
+       {CCI_REG8(0x9cd5), 0x0f},
+       {CCI_REG8(0x9cd6), 0x80},
+       {CCI_REG8(0x9cd7), 0x0f},
+       {CCI_REG8(0x9cd8), 0xac},
+       {CCI_REG8(0x9cd9), 0x0f},
+       {CCI_REG8(0x9cda), 0xac},
+       {CCI_REG8(0x9cdb), 0x0f},
+       {CCI_REG8(0x9cdc), 0x0f},
+       {CCI_REG8(0x9cdd), 0x12},
+       {CCI_REG8(0x9cde), 0x0f},
+       {CCI_REG8(0x9cdf), 0x12},
+       {CCI_REG8(0x9ce0), 0x34},
+       {CCI_REG8(0x9ce1), 0x12},
+       {CCI_REG8(0x9ce2), 0x34},
+       {CCI_REG8(0x9ce3), 0x12},
+       {CCI_REG8(0x9ce4), 0x3d},
+       {CCI_REG8(0x9ce5), 0x12},
+       {CCI_REG8(0x9ce6), 0x3d},
+       {CCI_REG8(0x9ce7), 0x12},
+       {CCI_REG8(0x9ce8), 0xf1},
+       {CCI_REG8(0x9ce9), 0x11},
+       {CCI_REG8(0x9cea), 0xf1},
+       {CCI_REG8(0x9ceb), 0x11},
+       {CCI_REG8(0x9cec), 0xe4},
+       {CCI_REG8(0x9ced), 0x0f},
+       {CCI_REG8(0x9cee), 0xe4},
+       {CCI_REG8(0x9cef), 0x0f},
+       {CCI_REG8(0x9cf0), 0x0a},
+       {CCI_REG8(0x9cf1), 0x10},
+       {CCI_REG8(0x9cf2), 0x0a},
+       {CCI_REG8(0x9cf3), 0x10},
+       {CCI_REG8(0x9cf4), 0x09},
+       {CCI_REG8(0x9cf5), 0x10},
+       {CCI_REG8(0x9cf6), 0x09},
+       {CCI_REG8(0x9cf7), 0x10},
+       {CCI_REG8(0x9cf8), 0xfb},
+       {CCI_REG8(0x9cf9), 0x0f},
+       {CCI_REG8(0x9cfa), 0xfb},
+       {CCI_REG8(0x9cfb), 0x0f},
+       {CCI_REG8(0xc8f1), 0xab},
+       {CCI_REG8(0xc8f2), 0x0f},
+       {CCI_REG8(0xc8f3), 0xab},
+       {CCI_REG8(0xc8f4), 0x0f},
+       {CCI_REG8(0xc8f5), 0xca},
+       {CCI_REG8(0xc8f6), 0x0f},
+       {CCI_REG8(0xc8f7), 0xca},
+       {CCI_REG8(0xc8f8), 0x0f},
+       {CCI_REG8(0xc8f9), 0xc8},
+       {CCI_REG8(0xc8fa), 0x0f},
+       {CCI_REG8(0xc8fb), 0xc8},
+       {CCI_REG8(0xc8fc), 0x0f},
+       {CCI_REG8(0xc8fd), 0xb0},
+       {CCI_REG8(0xc8fe), 0x0f},
+       {CCI_REG8(0xc8ff), 0xb0},
+       {CCI_REG8(0xc900), 0x0f},
+       {CCI_REG8(0xc901), 0x94},
+       {CCI_REG8(0xc902), 0x0f},
+       {CCI_REG8(0xc903), 0x94},
+       {CCI_REG8(0xc904), 0x0f},
+       {CCI_REG8(0xc905), 0x83},
+       {CCI_REG8(0xc906), 0x0f},
+       {CCI_REG8(0xc907), 0x83},
+       {CCI_REG8(0xc908), 0x0f},
+       {CCI_REG8(0xc909), 0x80},
+       {CCI_REG8(0xc90a), 0x0f},
+       {CCI_REG8(0xc90b), 0x80},
+       {CCI_REG8(0xc90c), 0x0f},
+       {CCI_REG8(0xc90d), 0xac},
+       {CCI_REG8(0xc90e), 0x0f},
+       {CCI_REG8(0xc90f), 0xac},
+       {CCI_REG8(0xc910), 0x0f},
+       {CCI_REG8(0xc911), 0x0f},
+       {CCI_REG8(0xc912), 0x12},
+       {CCI_REG8(0xc913), 0x0f},
+       {CCI_REG8(0xc914), 0x12},
+       {CCI_REG8(0xc915), 0x34},
+       {CCI_REG8(0xc916), 0x12},
+       {CCI_REG8(0xc917), 0x34},
+       {CCI_REG8(0xc918), 0x12},
+       {CCI_REG8(0xc919), 0x3d},
+       {CCI_REG8(0xc91a), 0x12},
+       {CCI_REG8(0xc91b), 0x3d},
+       {CCI_REG8(0xc91c), 0x12},
+       {CCI_REG8(0xc91d), 0xf1},
+       {CCI_REG8(0xc91e), 0x11},
+       {CCI_REG8(0xc91f), 0xf1},
+       {CCI_REG8(0xc920), 0x11},
+       {CCI_REG8(0xc921), 0xe4},
+       {CCI_REG8(0xc922), 0x0f},
+       {CCI_REG8(0xc923), 0xe4},
+       {CCI_REG8(0xc924), 0x0f},
+       {CCI_REG8(0xc925), 0x0a},
+       {CCI_REG8(0xc926), 0x10},
+       {CCI_REG8(0xc927), 0x0a},
+       {CCI_REG8(0xc928), 0x10},
+       {CCI_REG8(0xc929), 0x09},
+       {CCI_REG8(0xc92a), 0x10},
+       {CCI_REG8(0xc92b), 0x09},
+       {CCI_REG8(0xc92c), 0x10},
+       {CCI_REG8(0xc92d), 0xfb},
+       {CCI_REG8(0xc92e), 0x0f},
+       {CCI_REG8(0xc92f), 0xfb},
+       {CCI_REG8(0xc930), 0x0f},
+       {CCI_REG8(0xca27), 0xab},
+       {CCI_REG8(0xca28), 0x0f},
+       {CCI_REG8(0xca29), 0xab},
+       {CCI_REG8(0xca2a), 0x0f},
+       {CCI_REG8(0xca2b), 0xca},
+       {CCI_REG8(0xca2c), 0x0f},
+       {CCI_REG8(0xca2d), 0xca},
+       {CCI_REG8(0xca2e), 0x0f},
+       {CCI_REG8(0xca2f), 0xc8},
+       {CCI_REG8(0xca30), 0x0f},
+       {CCI_REG8(0xca31), 0xc8},
+       {CCI_REG8(0xca32), 0x0f},
+       {CCI_REG8(0xca33), 0xb0},
+       {CCI_REG8(0xca34), 0x0f},
+       {CCI_REG8(0xca35), 0xb0},
+       {CCI_REG8(0xca36), 0x0f},
+       {CCI_REG8(0xca37), 0x94},
+       {CCI_REG8(0xca38), 0x0f},
+       {CCI_REG8(0xca39), 0x94},
+       {CCI_REG8(0xca3a), 0x0f},
+       {CCI_REG8(0xca3b), 0x83},
+       {CCI_REG8(0xca3c), 0x0f},
+       {CCI_REG8(0xca3d), 0x83},
+       {CCI_REG8(0xca3e), 0x0f},
+       {CCI_REG8(0xca3f), 0x80},
+       {CCI_REG8(0xca40), 0x0f},
+       {CCI_REG8(0xca41), 0x80},
+       {CCI_REG8(0xca42), 0x0f},
+       {CCI_REG8(0xca43), 0xac},
+       {CCI_REG8(0xca44), 0x0f},
+       {CCI_REG8(0xca45), 0xac},
+       {CCI_REG8(0xca46), 0x0f},
+       {CCI_REG8(0xca47), 0x0f},
+       {CCI_REG8(0xca48), 0x12},
+       {CCI_REG8(0xca49), 0x0f},
+       {CCI_REG8(0xca4a), 0x12},
+       {CCI_REG8(0xca4b), 0x34},
+       {CCI_REG8(0xca4c), 0x12},
+       {CCI_REG8(0xca4d), 0x34},
+       {CCI_REG8(0xca4e), 0x12},
+       {CCI_REG8(0xca4f), 0x3d},
+       {CCI_REG8(0xca50), 0x12},
+       {CCI_REG8(0xca51), 0x3d},
+       {CCI_REG8(0xca52), 0x12},
+       {CCI_REG8(0xca53), 0xf1},
+       {CCI_REG8(0xca54), 0x11},
+       {CCI_REG8(0xca55), 0xf1},
+       {CCI_REG8(0xca56), 0x11},
+       {CCI_REG8(0xca57), 0xe4},
+       {CCI_REG8(0xca58), 0x0f},
+       {CCI_REG8(0xca59), 0xe4},
+       {CCI_REG8(0xca5a), 0x0f},
+       {CCI_REG8(0xca5b), 0x0a},
+       {CCI_REG8(0xca5c), 0x10},
+       {CCI_REG8(0xca5d), 0x0a},
+       {CCI_REG8(0xca5e), 0x10},
+       {CCI_REG8(0xca5f), 0x09},
+       {CCI_REG8(0xca60), 0x10},
+       {CCI_REG8(0xca61), 0x09},
+       {CCI_REG8(0xca62), 0x10},
+       {CCI_REG8(0xca63), 0xfb},
+       {CCI_REG8(0xca64), 0x0f},
+       {CCI_REG8(0xca65), 0xfb},
+       {CCI_REG8(0xca66), 0x0f},
+       {CCI_REG8(0xcb5d), 0xab},
+       {CCI_REG8(0xcb5e), 0x0f},
+       {CCI_REG8(0xcb5f), 0xab},
+       {CCI_REG8(0xcb60), 0x0f},
+       {CCI_REG8(0xcb61), 0xca},
+       {CCI_REG8(0xcb62), 0x0f},
+       {CCI_REG8(0xcb63), 0xca},
+       {CCI_REG8(0xcb64), 0x0f},
+       {CCI_REG8(0xcb65), 0xc8},
+       {CCI_REG8(0xcb66), 0x0f},
+       {CCI_REG8(0xcb67), 0xc8},
+       {CCI_REG8(0xcb68), 0x0f},
+       {CCI_REG8(0xcb69), 0xb0},
+       {CCI_REG8(0xcb6a), 0x0f},
+       {CCI_REG8(0xcb6b), 0xb0},
+       {CCI_REG8(0xcb6c), 0x0f},
+       {CCI_REG8(0xcb6d), 0x94},
+       {CCI_REG8(0xcb6e), 0x0f},
+       {CCI_REG8(0xcb6f), 0x94},
+       {CCI_REG8(0xcb70), 0x0f},
+       {CCI_REG8(0xcb71), 0x83},
+       {CCI_REG8(0xcb72), 0x0f},
+       {CCI_REG8(0xcb73), 0x83},
+       {CCI_REG8(0xcb74), 0x0f},
+       {CCI_REG8(0xcb75), 0x80},
+       {CCI_REG8(0xcb76), 0x0f},
+       {CCI_REG8(0xcb77), 0x80},
+       {CCI_REG8(0xcb78), 0x0f},
+       {CCI_REG8(0xcb79), 0xac},
+       {CCI_REG8(0xcb7a), 0x0f},
+       {CCI_REG8(0xcb7b), 0xac},
+       {CCI_REG8(0xcb7c), 0x0f},
+       {CCI_REG8(0xcb7d), 0x0f},
+       {CCI_REG8(0xcb7e), 0x12},
+       {CCI_REG8(0xcb7f), 0x0f},
+       {CCI_REG8(0xcb80), 0x12},
+       {CCI_REG8(0xcb81), 0x34},
+       {CCI_REG8(0xcb82), 0x12},
+       {CCI_REG8(0xcb83), 0x34},
+       {CCI_REG8(0xcb84), 0x12},
+       {CCI_REG8(0xcb85), 0x3d},
+       {CCI_REG8(0xcb86), 0x12},
+       {CCI_REG8(0xcb87), 0x3d},
+       {CCI_REG8(0xcb88), 0x12},
+       {CCI_REG8(0xcb89), 0xf1},
+       {CCI_REG8(0xcb8a), 0x11},
+       {CCI_REG8(0xcb8b), 0xf1},
+       {CCI_REG8(0xcb8c), 0x11},
+       {CCI_REG8(0xcb8d), 0xe4},
+       {CCI_REG8(0xcb8e), 0x0f},
+       {CCI_REG8(0xcb8f), 0xe4},
+       {CCI_REG8(0xcb90), 0x0f},
+       {CCI_REG8(0xcb91), 0x0a},
+       {CCI_REG8(0xcb92), 0x10},
+       {CCI_REG8(0xcb93), 0x0a},
+       {CCI_REG8(0xcb94), 0x10},
+       {CCI_REG8(0xcb95), 0x09},
+       {CCI_REG8(0xcb96), 0x10},
+       {CCI_REG8(0xcb97), 0x09},
+       {CCI_REG8(0xcb98), 0x10},
+       {CCI_REG8(0xcb99), 0xfb},
+       {CCI_REG8(0xcb9a), 0x0f},
+       {CCI_REG8(0xcb9b), 0xfb},
+       {CCI_REG8(0xcb9c), 0x0f},
+       {CCI_REG8(0xcc93), 0xab},
+       {CCI_REG8(0xcc94), 0x0f},
+       {CCI_REG8(0xcc95), 0xab},
+       {CCI_REG8(0xcc96), 0x0f},
+       {CCI_REG8(0xcc97), 0xca},
+       {CCI_REG8(0xcc98), 0x0f},
+       {CCI_REG8(0xcc99), 0xca},
+       {CCI_REG8(0xcc9a), 0x0f},
+       {CCI_REG8(0xcc9b), 0xc8},
+       {CCI_REG8(0xcc9c), 0x0f},
+       {CCI_REG8(0xcc9d), 0xc8},
+       {CCI_REG8(0xcc9e), 0x0f},
+       {CCI_REG8(0xcc9f), 0xb0},
+       {CCI_REG8(0xcca0), 0x0f},
+       {CCI_REG8(0xcca1), 0xb0},
+       {CCI_REG8(0xcca2), 0x0f},
+       {CCI_REG8(0xcca3), 0x94},
+       {CCI_REG8(0xcca4), 0x0f},
+       {CCI_REG8(0xcca5), 0x94},
+       {CCI_REG8(0xcca6), 0x0f},
+       {CCI_REG8(0xcca7), 0x83},
+       {CCI_REG8(0xcca8), 0x0f},
+       {CCI_REG8(0xcca9), 0x83},
+       {CCI_REG8(0xccaa), 0x0f},
+       {CCI_REG8(0xccab), 0x80},
+       {CCI_REG8(0xccac), 0x0f},
+       {CCI_REG8(0xccad), 0x80},
+       {CCI_REG8(0xccae), 0x0f},
+       {CCI_REG8(0xccaf), 0xac},
+       {CCI_REG8(0xccb0), 0x0f},
+       {CCI_REG8(0xccb1), 0xac},
+       {CCI_REG8(0xccb2), 0x0f},
+       {CCI_REG8(0xccb3), 0x0f},
+       {CCI_REG8(0xccb4), 0x12},
+       {CCI_REG8(0xccb5), 0x0f},
+       {CCI_REG8(0xccb6), 0x12},
+       {CCI_REG8(0xccb7), 0x34},
+       {CCI_REG8(0xccb8), 0x12},
+       {CCI_REG8(0xccb9), 0x34},
+       {CCI_REG8(0xccba), 0x12},
+       {CCI_REG8(0xccbb), 0x3d},
+       {CCI_REG8(0xccbc), 0x12},
+       {CCI_REG8(0xccbd), 0x3d},
+       {CCI_REG8(0xccbe), 0x12},
+       {CCI_REG8(0xccbf), 0xf1},
+       {CCI_REG8(0xccc0), 0x11},
+       {CCI_REG8(0xccc1), 0xf1},
+       {CCI_REG8(0xccc2), 0x11},
+       {CCI_REG8(0xccc3), 0xe4},
+       {CCI_REG8(0xccc4), 0x0f},
+       {CCI_REG8(0xccc5), 0xe4},
+       {CCI_REG8(0xccc6), 0x0f},
+       {CCI_REG8(0xccc7), 0x0a},
+       {CCI_REG8(0xccc8), 0x10},
+       {CCI_REG8(0xccc9), 0x0a},
+       {CCI_REG8(0xccca), 0x10},
+       {CCI_REG8(0xcccb), 0x09},
+       {CCI_REG8(0xcccc), 0x10},
+       {CCI_REG8(0xcccd), 0x09},
+       {CCI_REG8(0xccce), 0x10},
+       {CCI_REG8(0xcccf), 0xfb},
+       {CCI_REG8(0xccd0), 0x0f},
+       {CCI_REG8(0xccd1), 0xfb},
+       {CCI_REG8(0xccd2), 0x0f},
+       {CCI_REG8(0xcdc9), 0xab},
+       {CCI_REG8(0xcdca), 0x0f},
+       {CCI_REG8(0xcdcb), 0xab},
+       {CCI_REG8(0xcdcc), 0x0f},
+       {CCI_REG8(0xcdcd), 0xca},
+       {CCI_REG8(0xcdce), 0x0f},
+       {CCI_REG8(0xcdcf), 0xca},
+       {CCI_REG8(0xcdd0), 0x0f},
+       {CCI_REG8(0xcdd1), 0xc8},
+       {CCI_REG8(0xcdd2), 0x0f},
+       {CCI_REG8(0xcdd3), 0xc8},
+       {CCI_REG8(0xcdd4), 0x0f},
+       {CCI_REG8(0xcdd5), 0xb0},
+       {CCI_REG8(0xcdd6), 0x0f},
+       {CCI_REG8(0xcdd7), 0xb0},
+       {CCI_REG8(0xcdd8), 0x0f},
+       {CCI_REG8(0xcdd9), 0x94},
+       {CCI_REG8(0xcdda), 0x0f},
+       {CCI_REG8(0xcddb), 0x94},
+       {CCI_REG8(0xcddc), 0x0f},
+       {CCI_REG8(0xcddd), 0x83},
+       {CCI_REG8(0xcdde), 0x0f},
+       {CCI_REG8(0xcddf), 0x83},
+       {CCI_REG8(0xcde0), 0x0f},
+       {CCI_REG8(0xcde1), 0x80},
+       {CCI_REG8(0xcde2), 0x0f},
+       {CCI_REG8(0xcde3), 0x80},
+       {CCI_REG8(0xcde4), 0x0f},
+       {CCI_REG8(0xcde5), 0xac},
+       {CCI_REG8(0xcde6), 0x0f},
+       {CCI_REG8(0xcde7), 0xac},
+       {CCI_REG8(0xcde8), 0x0f},
+       {CCI_REG8(0xcde9), 0x0f},
+       {CCI_REG8(0xcdea), 0x12},
+       {CCI_REG8(0xcdeb), 0x0f},
+       {CCI_REG8(0xcdec), 0x12},
+       {CCI_REG8(0xcded), 0x34},
+       {CCI_REG8(0xcdee), 0x12},
+       {CCI_REG8(0xcdef), 0x34},
+       {CCI_REG8(0xcdf0), 0x12},
+       {CCI_REG8(0xcdf1), 0x3d},
+       {CCI_REG8(0xcdf2), 0x12},
+       {CCI_REG8(0xcdf3), 0x3d},
+       {CCI_REG8(0xcdf4), 0x12},
+       {CCI_REG8(0xcdf5), 0xf1},
+       {CCI_REG8(0xcdf6), 0x11},
+       {CCI_REG8(0xcdf7), 0xf1},
+       {CCI_REG8(0xcdf8), 0x11},
+       {CCI_REG8(0xcdf9), 0xe4},
+       {CCI_REG8(0xcdfa), 0x0f},
+       {CCI_REG8(0xcdfb), 0xe4},
+       {CCI_REG8(0xcdfc), 0x0f},
+       {CCI_REG8(0xcdfd), 0x0a},
+       {CCI_REG8(0xcdfe), 0x10},
+       {CCI_REG8(0xcdff), 0x0a},
+       {CCI_REG8(0xce00), 0x10},
+       {CCI_REG8(0xce01), 0x09},
+       {CCI_REG8(0xce02), 0x10},
+       {CCI_REG8(0xce03), 0x09},
+       {CCI_REG8(0xce04), 0x10},
+       {CCI_REG8(0xce05), 0xfb},
+       {CCI_REG8(0xce06), 0x0f},
+       {CCI_REG8(0xce07), 0xfb},
+       {CCI_REG8(0xce08), 0x0f},
+       {CCI_REG8(0xceff), 0xab},
+       {CCI_REG8(0xcf00), 0x0f},
+       {CCI_REG8(0xcf01), 0xab},
+       {CCI_REG8(0xcf02), 0x0f},
+       {CCI_REG8(0xcf03), 0xca},
+       {CCI_REG8(0xcf04), 0x0f},
+       {CCI_REG8(0xcf05), 0xca},
+       {CCI_REG8(0xcf06), 0x0f},
+       {CCI_REG8(0xcf07), 0xc8},
+       {CCI_REG8(0xcf08), 0x0f},
+       {CCI_REG8(0xcf09), 0xc8},
+       {CCI_REG8(0xcf0a), 0x0f},
+       {CCI_REG8(0xcf0b), 0xb0},
+       {CCI_REG8(0xcf0c), 0x0f},
+       {CCI_REG8(0xcf0d), 0xb0},
+       {CCI_REG8(0xcf0e), 0x0f},
+       {CCI_REG8(0xcf0f), 0x94},
+       {CCI_REG8(0xcf10), 0x0f},
+       {CCI_REG8(0xcf11), 0x94},
+       {CCI_REG8(0xcf12), 0x0f},
+       {CCI_REG8(0xcf13), 0x83},
+       {CCI_REG8(0xcf14), 0x0f},
+       {CCI_REG8(0xcf15), 0x83},
+       {CCI_REG8(0xcf16), 0x0f},
+       {CCI_REG8(0xcf17), 0x80},
+       {CCI_REG8(0xcf18), 0x0f},
+       {CCI_REG8(0xcf19), 0x80},
+       {CCI_REG8(0xcf1a), 0x0f},
+       {CCI_REG8(0xcf1b), 0xac},
+       {CCI_REG8(0xcf1c), 0x0f},
+       {CCI_REG8(0xcf1d), 0xac},
+       {CCI_REG8(0xcf1e), 0x0f},
+       {CCI_REG8(0xcf1f), 0x0f},
+       {CCI_REG8(0xcf20), 0x12},
+       {CCI_REG8(0xcf21), 0x0f},
+       {CCI_REG8(0xcf22), 0x12},
+       {CCI_REG8(0xcf23), 0x34},
+       {CCI_REG8(0xcf24), 0x12},
+       {CCI_REG8(0xcf25), 0x34},
+       {CCI_REG8(0xcf26), 0x12},
+       {CCI_REG8(0xcf27), 0x3d},
+       {CCI_REG8(0xcf28), 0x12},
+       {CCI_REG8(0xcf29), 0x3d},
+       {CCI_REG8(0xcf2a), 0x12},
+       {CCI_REG8(0xcf2b), 0xf1},
+       {CCI_REG8(0xcf2c), 0x11},
+       {CCI_REG8(0xcf2d), 0xf1},
+       {CCI_REG8(0xcf2e), 0x11},
+       {CCI_REG8(0xcf2f), 0xe4},
+       {CCI_REG8(0xcf30), 0x0f},
+       {CCI_REG8(0xcf31), 0xe4},
+       {CCI_REG8(0xcf32), 0x0f},
+       {CCI_REG8(0xcf33), 0x0a},
+       {CCI_REG8(0xcf34), 0x10},
+       {CCI_REG8(0xcf35), 0x0a},
+       {CCI_REG8(0xcf36), 0x10},
+       {CCI_REG8(0xcf37), 0x09},
+       {CCI_REG8(0xcf38), 0x10},
+       {CCI_REG8(0xcf39), 0x09},
+       {CCI_REG8(0xcf3a), 0x10},
+       {CCI_REG8(0xcf3b), 0xfb},
+       {CCI_REG8(0xcf3c), 0x0f},
+       {CCI_REG8(0xcf3d), 0xfb},
+       {CCI_REG8(0xcf3e), 0x0f},
+       {CCI_REG8(0xac32), 0x80},
+       {CCI_REG8(0xac33), 0x80},
+       {CCI_REG8(0xac34), 0x80},
+       {CCI_REG8(0xac35), 0x80},
+       {CCI_REG8(0xac36), 0x80},
+       {CCI_REG8(0xac37), 0x80},
+       {CCI_REG8(0xac38), 0x80},
+       {CCI_REG8(0xac39), 0x80},
+       {CCI_REG8(0xac3a), 0x80},
+       {CCI_REG8(0xac3b), 0x80},
+       {CCI_REG8(0xac3c), 0x80},
+       {CCI_REG8(0xac3d), 0x80},
+       {CCI_REG8(0xac3e), 0x80},
+       {CCI_REG8(0xac3f), 0x80},
+       {CCI_REG8(0xac40), 0x80},
+       {CCI_REG8(0xac41), 0x80},
+       {CCI_REG8(0xac42), 0x80},
+       {CCI_REG8(0xac43), 0x80},
+       {CCI_REG8(0xac44), 0x80},
+       {CCI_REG8(0xac45), 0x80},
+       {CCI_REG8(0xacb2), 0x00},
+       {CCI_REG8(0xacb3), 0x04},
+       {CCI_REG8(0xacb4), 0x00},
+       {CCI_REG8(0xacb5), 0x04},
+       {CCI_REG8(0xacb6), 0x00},
+       {CCI_REG8(0xacb7), 0x04},
+       {CCI_REG8(0xacb8), 0x00},
+       {CCI_REG8(0xacb9), 0x04},
+       {CCI_REG8(0xacba), 0x00},
+       {CCI_REG8(0xacbb), 0x04},
+       {CCI_REG8(0xacbc), 0x00},
+       {CCI_REG8(0xacbd), 0x04},
+       {CCI_REG8(0xacbe), 0x00},
+       {CCI_REG8(0xacbf), 0x04},
+       {CCI_REG8(0xacc0), 0x00},
+       {CCI_REG8(0xacc1), 0x04},
+       {CCI_REG8(0xacc2), 0x00},
+       {CCI_REG8(0xacc3), 0x04},
+       {CCI_REG8(0xacc4), 0x00},
+       {CCI_REG8(0xacc5), 0x04},
+       {CCI_REG8(0xacc6), 0x00},
+       {CCI_REG8(0xacc7), 0x04},
+       {CCI_REG8(0xacc8), 0x00},
+       {CCI_REG8(0xacc9), 0x04},
+       {CCI_REG8(0xacca), 0x00},
+       {CCI_REG8(0xaccb), 0x04},
+       {CCI_REG8(0xaccc), 0x00},
+       {CCI_REG8(0xaccd), 0x04},
+       {CCI_REG8(0xacce), 0x00},
+       {CCI_REG8(0xaccf), 0x04},
+       {CCI_REG8(0xacd0), 0x00},
+       {CCI_REG8(0xacd1), 0x04},
+       {CCI_REG8(0xacd2), 0x00},
+       {CCI_REG8(0xacd3), 0x04},
+       {CCI_REG8(0xacd4), 0x00},
+       {CCI_REG8(0xacd5), 0x04},
+       {CCI_REG8(0xacd6), 0x00},
+       {CCI_REG8(0xacd7), 0x04},
+       {CCI_REG8(0xacd8), 0x00},
+       {CCI_REG8(0xacd9), 0x04},
+};
+
+static inline struct imx728 *to_imx728(struct v4l2_subdev *sd)
+{
+       return container_of(sd, struct imx728, subdev);
+}
+
+static int imx728_wait_for_state(struct imx728 *imx728, enum imx728_sensor_state state)
+{
+       int ret;
+       int i;
+       u64 val;
+
+       for (i = 0; i < 50; i++) {
+               ret = 0; // reset if previous cci_read attempt failed
+               cci_read(imx728->regmap, IMX728_REG_STATE, &val, &ret);
+               if (ret == 0 && val == state) {
+                       dev_dbg(imx728->dev, "%s: Enter state %llu\n", __func__, val);
+                       return 0;
+               }
+               usleep_range(1000, 10000);
+       }
+
+       return -EBUSY;
+}
+
+static void imx728_init_formats(struct v4l2_subdev_state *state)
+{
+       struct v4l2_mbus_framefmt *format;
+
+       format = v4l2_subdev_state_get_format(state, 0, 0);
+       format->code = imx728_mbus_formats[0];
+       format->width = imx728_framesizes[0].width;
+       format->height = imx728_framesizes[0].height;
+       format->field = V4L2_FIELD_NONE;
+       format->colorspace = V4L2_COLORSPACE_RAW;
+       format->quantization = V4L2_QUANTIZATION_FULL_RANGE;
+       format->xfer_func = V4L2_XFER_FUNC_NONE;
+       format->ycbcr_enc = V4L2_YCBCR_ENC_601;
+}
+
+static int _imx728_set_routing(struct v4l2_subdev *sd,
+                              struct v4l2_subdev_state *state)
+{
+       struct v4l2_subdev_route routes[] = {
+               {
+                       .source_pad = 0,
+                       .source_stream = 0,
+                       .flags = V4L2_SUBDEV_ROUTE_FL_ACTIVE,
+               },
+               {
+                       .source_pad = 0,
+                       .source_stream = 1,
+               }
+       };
+
+       struct v4l2_subdev_krouting routing = {
+               .num_routes = ARRAY_SIZE(routes),
+               .routes = routes,
+       };
+
+       int ret;
+
+       ret = v4l2_subdev_set_routing(sd, state, &routing);
+       if (ret < 0)
+               return ret;
+
+       imx728_init_formats(state);
+
+       return 0;
+}
+
+static int imx728_init_state(struct v4l2_subdev *sd,
+                          struct v4l2_subdev_state *state)
+{
+       return _imx728_set_routing(sd, state);
+}
+
+static int imx728_enum_mbus_code(struct v4l2_subdev *sd,
+                                struct v4l2_subdev_state *state,
+                                struct v4l2_subdev_mbus_code_enum *code)
+{
+
+       if (code->index >= ARRAY_SIZE(imx728_mbus_formats))
+               return -EINVAL;
+
+       code->code = imx728_mbus_formats[code->index];
+
+       return 0;
+}
+
+static int imx728_enum_frame_sizes(struct v4l2_subdev *sd,
+                                  struct v4l2_subdev_state *state,
+                                  struct v4l2_subdev_frame_size_enum *fse)
+{
+       unsigned int i;
+
+       for (i = 0; i < ARRAY_SIZE(imx728_mbus_formats); ++i) {
+               if (imx728_mbus_formats[i] == fse->code)
+                       break;
+       }
+
+       if (i == ARRAY_SIZE(imx728_mbus_formats))
+               return -EINVAL;
+
+       if (fse->index >= ARRAY_SIZE(imx728_framesizes))
+               return -EINVAL;
+
+       fse->min_width = imx728_framesizes[fse->index].width;
+       fse->max_width = fse->min_width;
+       fse->min_height = imx728_framesizes[fse->index].height;
+       fse->max_height = fse->min_height;
+
+       return 0;
+}
+
+static int imx728_get_selection(struct v4l2_subdev *sd,
+                               struct v4l2_subdev_state *state,
+                               struct v4l2_subdev_selection *sel)
+{
+       struct imx728 *imx728 = to_imx728(sd);
+       struct v4l2_mbus_framefmt *format;
+
+       switch (sel->target) {
+       case V4L2_SEL_TGT_CROP:
+               format = v4l2_subdev_state_get_format(state, 0, 0);
+
+               sel->r.top = IMX728_PIXEL_ARRAY_MARGIN_TOP
+                       + (IMX728_PIXEL_ARRAY_RECORDING_HEIGHT - format->height) / 2
+                       + imx728->ctrl.v_flip->val;
+               sel->r.left = IMX728_PIXEL_ARRAY_MARGIN_LEFT
+                       + (IMX728_PIXEL_ARRAY_RECORDING_WIDTH - format->width) / 2
+                       + imx728->ctrl.h_flip->val;
+               sel->r.height = format->height;
+               sel->r.width = format->width;
+               return 0;
+       case V4L2_SEL_TGT_NATIVE_SIZE:
+               sel->r.top = 0;
+               sel->r.left = 0;
+               sel->r.width = IMX728_PIXEL_ARRAY_WIDTH;
+               sel->r.height = IMX728_PIXEL_ARRAY_HEIGHT;
+               return 0;
+       case V4L2_SEL_TGT_CROP_DEFAULT:
+       case V4L2_SEL_TGT_CROP_BOUNDS:
+               sel->r.top = IMX728_PIXEL_ARRAY_MARGIN_TOP;
+               sel->r.left = IMX728_PIXEL_ARRAY_MARGIN_LEFT;
+               sel->r.width = IMX728_PIXEL_ARRAY_RECORDING_WIDTH;
+               sel->r.height = IMX728_PIXEL_ARRAY_RECORDING_HEIGHT;
+               return 0;
+       }
+
+       return -EINVAL;
+}
+
+
+static int imx728_set_fmt(struct v4l2_subdev *sd,
+                         struct v4l2_subdev_state *state,
+                         struct v4l2_subdev_format *fmt)
+{
+       struct imx728 *imx728 = to_imx728(sd);
+       struct v4l2_mbus_framefmt *format;
+       const struct v4l2_area *fsize;
+       unsigned int i;
+       u32 code;
+       int ret = 0;
+
+       if (fmt->pad != 0)
+               return -EINVAL;
+
+       if (fmt->stream != 0)
+               return -EINVAL;
+
+       for (i = 0; i < ARRAY_SIZE(imx728_mbus_formats); ++i) {
+               if (imx728_mbus_formats[i] == fmt->format.code) {
+                       code = fmt->format.code;
+                       break;
+               }
+       }
+
+       if (i == ARRAY_SIZE(imx728_mbus_formats))
+               code = imx728_mbus_formats[0];
+
+       fsize = v4l2_find_nearest_size(imx728_framesizes,
+                                      ARRAY_SIZE(imx728_framesizes), width,
+                                      height, fmt->format.width,
+                                      fmt->format.height);
+
+       mutex_lock(&imx728->lock);
+
+       fmt->format.field = V4L2_FIELD_NONE;
+       fmt->format.colorspace = V4L2_COLORSPACE_RAW;
+       fmt->format.ycbcr_enc = V4L2_YCBCR_ENC_601;
+       fmt->format.quantization = V4L2_QUANTIZATION_FULL_RANGE;
+       fmt->format.xfer_func = V4L2_XFER_FUNC_NONE;
+
+       fmt->format.width = fsize->width;
+       fmt->format.height = fsize->height;
+       fmt->format.code = code;
+
+       format = v4l2_subdev_state_get_format(state, fmt->pad, fmt->stream);
+
+       if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE && imx728->streaming) {
+               ret = -EBUSY;
+               goto done;
+       }
+
+       *format = fmt->format;
+
+done:
+       mutex_unlock(&imx728->lock);
+
+       return ret;
+}
+
+static int imx728_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad,
+                                struct v4l2_mbus_frame_desc *fd)
+{
+       struct v4l2_subdev_state *state;
+       struct v4l2_mbus_framefmt *fmt;
+       u32 bpp;
+       u32 dt;
+       int ret = 0;
+
+       if (pad != 0)
+               return -EINVAL;
+
+       state = v4l2_subdev_lock_and_get_active_state(sd);
+
+       fmt = v4l2_subdev_state_get_format(state, 0, 0);
+       if (!fmt) {
+               ret = -EPIPE;
+               goto out;
+       }
+
+       memset(fd, 0, sizeof(*fd));
+
+       fd->type = V4L2_MBUS_FRAME_DESC_TYPE_CSI2;
+
+       /* pixel stream */
+
+       switch (fmt->code) {
+       case MEDIA_BUS_FMT_SRGGB12_1X12:
+               bpp = 12;
+               dt = 0x2c; /* SRGGB12 */
+               break;
+       default:
+               ret = -EINVAL;
+               goto out;
+       }
+
+       fd->entry[fd->num_entries].stream = 0;
+
+       fd->entry[fd->num_entries].flags = V4L2_MBUS_FRAME_DESC_FL_LEN_MAX;
+       fd->entry[fd->num_entries].length = fmt->width * fmt->height * bpp / 8;
+       fd->entry[fd->num_entries].pixelcode = fmt->code;
+       fd->entry[fd->num_entries].bus.csi2.vc = 0;
+       fd->entry[fd->num_entries].bus.csi2.dt = dt;
+
+       fd->num_entries++;
+
+out:
+
+       v4l2_subdev_unlock_state(state);
+
+       return ret;
+}
+
+static int imx728_set_routing(struct v4l2_subdev *sd,
+                             struct v4l2_subdev_state *state,
+                             enum v4l2_subdev_format_whence which,
+                             struct v4l2_subdev_krouting *routing)
+{
+       int ret;
+
+       if (routing->num_routes == 0 || routing->num_routes > 1)
+               return -EINVAL;
+
+       ret = _imx728_set_routing(sd, state);
+
+       return ret;
+}
+
+static int imx728_set_ctrl(struct v4l2_ctrl *ctrl)
+{
+       struct imx728 *imx728 = container_of(ctrl->handler,
+                                            struct imx728, ctrl.handler);
+       int ret = 0;
+
+       dev_dbg(imx728->dev, "%s: %s, value: %d\n",
+                       __func__, ctrl->name, ctrl->val);
+
+       if (!pm_runtime_get_if_in_use(imx728->dev))
+               return 0;
+
+       switch (ctrl->id) {
+       case V4L2_CID_EXPOSURE:
+               cci_write(imx728->regmap,
+                       IMX728_REG_EXPOSURE_SP1, ctrl->val, &ret);
+               cci_write(imx728->regmap,
+                       IMX728_REG_EXPOSURE_SP2, ctrl->val, &ret);
+               cci_write(imx728->regmap,
+                       IMX728_REG_EXPOSURE_SP1VS, ctrl->val, &ret);
+               break;
+       case V4L2_CID_ANALOGUE_GAIN:
+               cci_write(imx728->regmap,
+                       IMX728_REG_FME_ISP_GAIN_FID0, ctrl->val, &ret);
+               break;
+       case V4L2_CID_HFLIP:
+               cci_update_bits(imx728->regmap, IMX728_REG_FLIP,
+                                        0x1, ctrl->val, &ret);
+               cci_update_bits(imx728->regmap, IMX728_REG_HFLIP,
+                                         0x1, ctrl->val, &ret);
+               break;
+       case V4L2_CID_VFLIP:
+               cci_update_bits(imx728->regmap, IMX728_REG_FLIP,
+                                        0x2, ctrl->val << 1, &ret);
+               cci_update_bits(imx728->regmap, IMX728_REG_VFLIP,
+                                        0x1, ctrl->val, &ret);
+               break;
+       default:
+               ret = -EINVAL;
+       }
+
+       pm_runtime_put_noidle(imx728->dev);
+       return ret;
+}
+
+static int imx728_detect(struct imx728 *imx728)
+{
+       int ret = 0;
+       u64 minor, major;
+
+       cci_read(imx728->regmap, IMX728_REG_VMAJOR, &major, &ret);
+       if (ret != 0) {
+               dev_err(imx728->dev, "Could not read PARAM_MAJOR_VER!");
+               return ret;
+       }
+       cci_read(imx728->regmap, IMX728_REG_VMINOR, &minor, &ret);
+       if (ret != 0) {
+               dev_err(imx728->dev, "Could not read PARAM_MINOR_VER!");
+               return ret;
+       }
+       dev_dbg(imx728->dev, "Got version: %lld.%lld", major, minor);
+
+       return 0;
+}
+
+static int imx728_reset(struct imx728 *imx728)
+{
+
+       int ret = 0;
+
+       // Prefer hardware reset if available.
+       if (!IS_ERR_OR_NULL(imx728->reset_gpio)) {
+               gpiod_set_value_cansleep(imx728->reset_gpio, 1);
+               usleep_range(1000, 10000);
+               gpiod_set_value_cansleep(imx728->reset_gpio, 0);
+               msleep(100);
+       } else {
+               // Software reset.
+               cci_write(imx728->regmap, IMX728_REG_RESET_0, 0xc3, &ret);
+               cci_update_bits(imx728->regmap, IMX728_REG_RESET_1, 0x1, 0x1, &ret);
+               msleep(100);
+       }
+
+       return ret;
+}
+
+static int imx728_power_on(struct imx728 *imx728)
+{
+       int ret;
+
+       ret = clk_prepare_enable(imx728->clk);
+       if (ret < 0)
+               return ret;
+
+       imx728_reset(imx728);
+       return 0;
+}
+
+static int imx728_power_off(struct imx728 *imx728)
+{
+
+       if (imx728->reset_gpio) {
+               gpiod_set_value_cansleep(imx728->reset_gpio, 1);
+
+               usleep_range(1, 10);
+       }
+       clk_disable_unprepare(imx728->clk);
+       return 0;
+}
+
+static int imx728_get_frame_interval(struct v4l2_subdev *sd,
+                                    struct v4l2_subdev_state *sd_state,
+                                    struct v4l2_subdev_frame_interval *fi)
+{
+       struct imx728 *imx728 = to_imx728(sd);
+
+       fi->interval.numerator = 1;
+       fi->interval.denominator = imx728->fps;
+       return 0;
+}
+
+static int imx728_set_frame_interval(struct v4l2_subdev *sd,
+                                    struct v4l2_subdev_state *sd_state,
+                                    struct v4l2_subdev_frame_interval *fi)
+{
+       struct imx728 *imx728 = to_imx728(sd);
+       u32 req_fps;
+
+       mutex_lock(&imx728->lock);
+
+       if (fi->interval.numerator == 0 || fi->interval.denominator == 0) {
+               fi->interval.denominator = IMX728_FRAMERATE_DEFAULT;
+               fi->interval.numerator = 1;
+       }
+
+       req_fps = clamp_val(DIV_ROUND_CLOSEST(fi->interval.denominator,
+                                             fi->interval.numerator),
+                           IMX728_FRAMERATE_MIN, IMX728_FRAMERATE_MAX);
+
+       fi->interval.numerator = 1;
+       fi->interval.denominator = req_fps;
+
+       imx728->fps = req_fps;
+
+       mutex_unlock(&imx728->lock);
+       dev_dbg(imx728->dev, "%s frame rate = %d\n", __func__, imx728->fps);
+
+       return 0;
+}
+
+static int imx728_powerup_to_standby(struct imx728 *imx728)
+{
+       int ret = 0;
+
+       dev_dbg(imx728->dev, "powerup -> standby...");
+
+       ret = imx728_reset(imx728);
+       if (ret) {
+               dev_err(imx728->dev, "Error resetting: %i", ret);
+               return ret;
+       }
+
+       ret = imx728_wait_for_state(imx728, IMX728_SENSOR_STATE_SLEEP);
+       if (ret < 0) {
+               dev_err(imx728->dev, "Could not transition to Sleep state!");
+               return ret;
+       }
+
+       cci_write(imx728->regmap, IMX728_REG_INCK_0, imx728->clk_rate / 1000000, &ret);
+       cci_write(imx728->regmap, IMX728_REG_INCK_1, 0x1, &ret);
+       if (ret < 0) {
+               dev_err(imx728->dev, "Couldn't write INCK frequency!");
+               return ret;
+       }
+
+       cci_write(imx728->regmap, IMX728_REG_SLEEP, 0xff, &ret);
+       if (ret < 0) {
+               dev_err(imx728->dev, "Couldn't write to SLEEP!");
+               return ret;
+       }
+
+       ret = imx728_wait_for_state(imx728, IMX728_SENSOR_STATE_STANDBY);
+       if (ret < 0) {
+               dev_err(imx728->dev, "Couldn't transition from Sleep to Standby state!");
+               return ret;
+       }
+
+       cci_write(imx728->regmap, IMX728_REG_REGMAP, IMX728_REMAP_MODE_STANDBY, &ret);
+       if (ret < 0) {
+               dev_err(imx728->dev, "Couldn't write remap mode!");
+               return ret;
+       }
+
+       return 0;
+}
+
+static int imx728_start_stream(struct imx728 *imx728)
+{
+       struct v4l2_subdev_state *state;
+       struct v4l2_mbus_framefmt *fmt;
+       int ret;
+
+       ret = imx728_powerup_to_standby(imx728);
+       if (ret < 0)
+               return ret;
+
+       state = v4l2_subdev_lock_and_get_active_state(&imx728->subdev);
+       fmt = v4l2_subdev_state_get_format(state, 0, 0);
+       v4l2_subdev_unlock_state(state);
+       if (!fmt)
+               return -EPIPE;
+
+       switch (fmt->code) {
+       case MEDIA_BUS_FMT_SRGGB12_1X12:
+               cci_multi_reg_write(imx728->regmap,
+                       imx728_wdr_12bit_3856x2176,
+                       ARRAY_SIZE(imx728_wdr_12bit_3856x2176),
+                       &ret);
+               break;
+       default:
+               return -EINVAL;
+       }
+       if (ret < 0)
+               return ret;
+       msleep(100);
+
+       cci_write(imx728->regmap,
+               IMX728_REG_UNIT_00, IMX728_FME_SHTVAL_UNIT_MICROSECONDS, &ret);
+       cci_write(imx728->regmap,
+               IMX728_REG_UNIT_01, IMX728_FME_SHTVAL_UNIT_MICROSECONDS, &ret);
+       cci_write(imx728->regmap,
+               IMX728_REG_UNIT_02, IMX728_FME_SHTVAL_UNIT_MICROSECONDS, &ret);
+       if (ret < 0) {
+               dev_err(imx728->dev, "Couldn't set exposure time unit to microseconds!");
+               return ret;
+       }
+
+       cci_write(imx728->regmap, IMX728_REG_OB_0, 0x28, &ret);
+       cci_write(imx728->regmap, IMX728_REG_OB_1, 0x0, &ret);
+       if (ret < 0) {
+               dev_err(imx728->dev, "Error disabling OB output.");
+               return ret;
+       }
+
+       cci_write(imx728->regmap, IMX728_REG_SKEW, 0x0, &ret);
+       if (ret < 0) {
+               dev_err(imx728->dev, "Error disabling skew calibration from sensor to SER");
+               return ret;
+       }
+
+       cci_update_bits(imx728->regmap,
+               IMX728_REG_SUBP_0, 0x7, IMX728_RAW_SEL_SP1H, &ret);
+       cci_update_bits(imx728->regmap,
+               IMX728_REG_SUBP_1, 0x7, IMX728_RAW_SEL_SP1H, &ret);
+       if (ret < 0) {
+               dev_err(imx728->dev, "Failed to set subpixel register");
+               return ret;
+       }
+
+       ret = __v4l2_ctrl_handler_setup(imx728->subdev.ctrl_handler);
+       if (ret < 0) {
+               dev_err(imx728->dev,
+                       "%s: failed to apply v4l2 ctrls: %d\n", __func__, ret);
+               return ret;
+       }
+
+       cci_write(imx728->regmap, IMX728_REG_STREAM_02, 0x5c, &ret);
+       if (ret < 0)
+               return ret;
+       cci_write(imx728->regmap, IMX728_REG_STREAM_02, 0xa3, &ret);
+       if (ret < 0)
+               return ret;
+
+       ret = imx728_wait_for_state(imx728, IMX728_SENSOR_STATE_STREAMING);
+       if (ret < 0) {
+               dev_err(imx728->dev, "Could not transition to Streaming!");
+               return ret;
+       }
+
+       msleep(20);
+
+       return 0;
+}
+
+static int imx728_stop_stream(struct imx728 *imx728)
+{
+       int ret;
+
+       cci_write(imx728->regmap, IMX728_REG_STREAM_02, 0xff, &ret);
+       if (ret < 0) {
+               dev_err(imx728->dev, "Error sending stop stream command: %i", ret);
+               return ret;
+       }
+
+       imx728_wait_for_state(imx728, IMX728_SENSOR_STATE_STANDBY);
+       if (ret < 0) {
+               dev_err(imx728->dev, "Couldn't transition out of Streaming mode!");
+               return ret;
+       }
+
+       return 0;
+}
+
+static int imx728_set_stream(struct v4l2_subdev *sd, int enable)
+{
+       struct imx728 *imx728 = to_imx728(sd);
+       int ret;
+
+       mutex_lock(&imx728->lock);
+       if (imx728->streaming == enable) {
+               mutex_unlock(&imx728->lock);
+               return 0;
+       }
+
+       if (enable) {
+               ret = pm_runtime_get_sync(imx728->dev);
+               if (ret < 0) {
+                       pm_runtime_put_noidle(imx728->dev);
+                       goto err_unlock;
+               }
+
+               ret = imx728_start_stream(imx728);
+               if (ret < 0)
+                       goto err_runtime_put;
+       } else {
+               ret = imx728_stop_stream(imx728);
+               if (ret < 0)
+                       goto err_runtime_put;
+               pm_runtime_mark_last_busy(imx728->dev);
+               pm_runtime_put_autosuspend(imx728->dev);
+       }
+
+       imx728->streaming = enable;
+
+       __v4l2_ctrl_grab(imx728->ctrl.h_flip, enable);
+       __v4l2_ctrl_grab(imx728->ctrl.v_flip, enable);
+
+       mutex_unlock(&imx728->lock);
+
+       return 0;
+
+err_runtime_put:
+       pm_runtime_put(imx728->dev);
+
+err_unlock:
+       mutex_unlock(&imx728->lock);
+       dev_err(imx728->dev,
+               "%s: failed to setup streaming %d\n", __func__, ret);
+       return ret;
+}
+
+static const struct v4l2_subdev_core_ops imx728_core_ops = {
+       .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
+       .unsubscribe_event = v4l2_event_subdev_unsubscribe,
+};
+
+static const struct v4l2_subdev_video_ops imx728_subdev_video_ops = {
+       .s_stream = imx728_set_stream,
+};
+
+static const struct v4l2_subdev_pad_ops imx728_subdev_pad_ops = {
+       .enum_frame_size = imx728_enum_frame_sizes,
+       .enum_mbus_code = imx728_enum_mbus_code,
+       .get_fmt = v4l2_subdev_get_fmt,
+       .get_frame_desc = imx728_get_frame_desc,
+       .get_frame_interval = imx728_get_frame_interval,
+       .get_selection = imx728_get_selection,
+       .set_fmt = imx728_set_fmt,
+       .set_frame_interval = imx728_set_frame_interval,
+       .set_routing = imx728_set_routing,
+};
+
+static const struct v4l2_subdev_ops imx728_subdev_ops = {
+       .core  = &imx728_core_ops,
+       .video = &imx728_subdev_video_ops,
+       .pad   = &imx728_subdev_pad_ops,
+};
+
+static const struct v4l2_subdev_internal_ops imx728_internal_ops = {
+       .init_state = imx728_init_state,
+};
+
+
+static const struct v4l2_ctrl_ops imx728_ctrl_ops = {
+       .s_ctrl = imx728_set_ctrl,
+};
+
+static int imx728_probe(struct i2c_client *client)
+{
+       struct imx728 *imx728;
+       struct v4l2_subdev *sd;
+       struct v4l2_ctrl_handler *ctrl_hdr;
+       int ret;
+
+       imx728 = devm_kzalloc(&client->dev, sizeof(*imx728), GFP_KERNEL);
+       if (!imx728)
+               return -ENOMEM;
+
+       imx728->dev = &client->dev;
+
+       imx728->regmap = devm_cci_regmap_init_i2c(client, 16);
+       if (IS_ERR(imx728->regmap))
+               return PTR_ERR(imx728->regmap);
+
+       imx728->reset_gpio = devm_gpiod_get_optional(imx728->dev,
+                                            "reset", GPIOD_OUT_LOW);
+       if (IS_ERR(imx728->reset_gpio))
+               return PTR_ERR(imx728->reset_gpio);
+
+       imx728->clk = devm_clk_get(imx728->dev, "inck");
+       if (IS_ERR(imx728->clk))
+               return PTR_ERR(imx728->clk);
+
+       imx728->clk_rate = clk_get_rate(imx728->clk);
+       if (imx728->clk_rate < 18000000 || imx728->clk_rate > 30000000)
+               return -EINVAL;
+
+       ret = imx728_power_on(imx728);
+       if (ret < 0)
+               return ret;
+
+       ret = imx728_detect(imx728);
+       if (ret < 0)
+               return ret;
+
+       sd = &imx728->subdev;
+       v4l2_i2c_subdev_init(sd, client, &imx728_subdev_ops);
+       sd->internal_ops = &imx728_internal_ops;
+
+       sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE |
+                    V4L2_SUBDEV_FL_HAS_EVENTS;
+
+       imx728->pad.flags = MEDIA_PAD_FL_SOURCE;
+       sd->entity.function = MEDIA_ENT_F_CAM_SENSOR;
+       ret = media_entity_pads_init(&sd->entity, 1, &imx728->pad);
+       if (ret < 0) {
+               dev_err(imx728->dev,
+                       "%s: media entity init failed %d\n", __func__, ret);
+               return ret;
+       }
+
+       ctrl_hdr = &imx728->ctrl.handler;
+       ret = v4l2_ctrl_handler_init(ctrl_hdr, 8);
+       if (ret < 0) {
+               dev_err(imx728->dev,
+                       "%s: ctrl handler init failed: %d\n", __func__, ret);
+               goto err_media_cleanup;
+       }
+
+       mutex_init(&imx728->lock);
+       imx728->ctrl.handler.lock = &imx728->lock;
+       imx728->fps = IMX728_FRAMERATE_DEFAULT;
+
+       imx728->ctrl.exposure = v4l2_ctrl_new_std(ctrl_hdr, &imx728_ctrl_ops,
+                                                 V4L2_CID_EXPOSURE,
+                                                 0, 33000,
+                                                 1,
+                                                 IMX728_EXPOSURE_DEFAULT);
+
+       imx728->ctrl.again = v4l2_ctrl_new_std(ctrl_hdr, &imx728_ctrl_ops,
+                                              V4L2_CID_ANALOGUE_GAIN,
+                                              0, 420,
+                                              1,
+                                              IMX728_AGAIN_DEFAULT);
+
+       imx728->ctrl.h_flip = v4l2_ctrl_new_std(ctrl_hdr, &imx728_ctrl_ops,
+                                               V4L2_CID_HFLIP, 0, 1, 1, 1);
+
+       imx728->ctrl.v_flip = v4l2_ctrl_new_std(ctrl_hdr, &imx728_ctrl_ops,
+                                               V4L2_CID_VFLIP, 0, 1, 1, 1);
+
+       imx728->ctrl.pixel_rate = v4l2_ctrl_new_std(ctrl_hdr, &imx728_ctrl_ops,
+                                            V4L2_CID_PIXEL_RATE,
+                                            IMX728_PIXEL_RATE,
+                                            IMX728_PIXEL_RATE, 1,
+                                            IMX728_PIXEL_RATE);
+
+       imx728->ctrl.link_freq = v4l2_ctrl_new_int_menu(ctrl_hdr, &imx728_ctrl_ops,
+                                                V4L2_CID_LINK_FREQ,
+                                                ARRAY_SIZE(imx728_link_freq_menu) - 1, 0,
+                                                imx728_link_freq_menu);
+
+       if (imx728->ctrl.link_freq)
+               imx728->ctrl.link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
+
+       imx728->subdev.ctrl_handler = ctrl_hdr;
+       if (imx728->ctrl.handler.error) {
+               ret = imx728->ctrl.handler.error;
+               dev_err(imx728->dev,
+                       "%s: failed to add the ctrls: %d\n", __func__, ret);
+               goto err_ctrl_free;
+       }
+
+       pm_runtime_set_active(imx728->dev);
+       pm_runtime_enable(imx728->dev);
+       pm_runtime_set_autosuspend_delay(imx728->dev, IMX728_PM_IDLE_TIMEOUT);
+       pm_runtime_use_autosuspend(imx728->dev);
+       pm_runtime_get_noresume(imx728->dev);
+
+       ret = v4l2_subdev_init_finalize(sd);
+       if (ret < 0)
+               goto err_pm_disable;
+
+       ret = v4l2_async_register_subdev(sd);
+       if (ret < 0) {
+               dev_err(imx728->dev,
+                       "%s: v4l2 subdev register failed %d\n", __func__, ret);
+               goto err_subdev_cleanup;
+       }
+
+       pm_runtime_mark_last_busy(imx728->dev);
+       pm_runtime_put_autosuspend(imx728->dev);
+       return 0;
+
+err_subdev_cleanup:
+       v4l2_subdev_cleanup(&imx728->subdev);
+
+err_pm_disable:
+       pm_runtime_dont_use_autosuspend(imx728->dev);
+       pm_runtime_put_noidle(imx728->dev);
+       pm_runtime_disable(imx728->dev);
+
+err_ctrl_free:
+       v4l2_ctrl_handler_free(ctrl_hdr);
+       mutex_destroy(&imx728->lock);
+
+err_media_cleanup:
+       media_entity_cleanup(&imx728->subdev.entity);
+
+       return ret;
+}
+
+static int __maybe_unused imx728_runtime_resume(struct device *dev)
+{
+       struct i2c_client *client = to_i2c_client(dev);
+       struct v4l2_subdev *sd = i2c_get_clientdata(client);
+       struct imx728 *imx728 = to_imx728(sd);
+       int ret;
+
+       ret = imx728_power_on(imx728);
+       if (ret < 0)
+               return ret;
+
+       return 0;
+}
+
+static int __maybe_unused imx728_runtime_suspend(struct device *dev)
+{
+       struct i2c_client *client = to_i2c_client(dev);
+       struct v4l2_subdev *sd = i2c_get_clientdata(client);
+       struct imx728 *imx728 = to_imx728(sd);
+
+       imx728_power_off(imx728);
+
+       return 0;
+}
+
+static int __maybe_unused imx728_suspend(struct device *dev)
+{
+       struct i2c_client *client = to_i2c_client(dev);
+       struct v4l2_subdev *sd = i2c_get_clientdata(client);
+       struct imx728 *imx728 = to_imx728(sd);
+       int ret;
+
+       if (imx728->streaming)
+               imx728_stop_stream(imx728);
+
+       ret = pm_runtime_force_suspend(dev);
+       if (ret < 0)
+               dev_warn(dev, "%s: failed to suspend: %i\n", __func__, ret);
+
+       return 0;
+}
+
+static int __maybe_unused imx728_resume(struct device *dev)
+{
+       struct i2c_client *client = to_i2c_client(dev);
+       struct v4l2_subdev *sd = i2c_get_clientdata(client);
+       struct imx728 *imx728 = to_imx728(sd);
+       int ret;
+
+       ret = pm_runtime_force_resume(dev);
+       if (ret < 0)
+               dev_warn(dev, "%s: failed to resume: %i\n", __func__, ret);
+
+       if (imx728->streaming)
+               ret = imx728_start_stream(imx728);
+
+       if (ret < 0) {
+               imx728_stop_stream(imx728);
+               imx728->streaming = 0;
+               return ret;
+       }
+
+       return 0;
+}
+
+static void imx728_remove(struct i2c_client *client)
+{
+       struct v4l2_subdev *sd = i2c_get_clientdata(client);
+       struct imx728 *imx728 = to_imx728(sd);
+
+       v4l2_async_unregister_subdev(sd);
+       v4l2_ctrl_handler_free(&imx728->ctrl.handler);
+       v4l2_subdev_cleanup(&imx728->subdev);
+       media_entity_cleanup(&sd->entity);
+       mutex_destroy(&imx728->lock);
+
+       pm_runtime_disable(imx728->dev);
+       pm_runtime_dont_use_autosuspend(imx728->dev);
+       pm_runtime_set_suspended(imx728->dev);
+}
+
+static const struct dev_pm_ops imx728_pm_ops = {
+       SET_RUNTIME_PM_OPS(imx728_runtime_suspend,
+                          imx728_runtime_resume, NULL)
+       SET_SYSTEM_SLEEP_PM_OPS(imx728_suspend, imx728_resume)
+};
+
+static const struct of_device_id imx728_dt_id[] = {
+       { .compatible = "sony,imx728" },
+       { /* sentinel */ }
+};
+
+MODULE_DEVICE_TABLE(of, imx728_dt_id);
+
+static struct i2c_driver imx728_i2c_driver = {
+       .driver = {
+               .name = "imx728",
+               .of_match_table = imx728_dt_id,
+               .pm = &imx728_pm_ops,
+       },
+       .probe = imx728_probe,
+       .remove = imx728_remove,
+};
+
+module_i2c_driver(imx728_i2c_driver);
+
+MODULE_DESCRIPTION("Camera Sensor Driver for Sony IMX728");
+MODULE_AUTHOR("Sebastian LaVine <slavine@d3embedded.com>");
+MODULE_LICENSE("GPL");
--
2.34.1

Please be aware that this email includes email addresses outside of the organization.

Re: [PATCH 2/4] media: i2c: Add driver for Sony IMX728

[Krzysztof Kozlowski]

On 12/02/2025 20:56, Sebastian LaVine wrote:
> +static int imx728_detect(struct imx728 *imx728)
> +{
> +       int ret = 0;
> +       u64 minor, major;
> +
> +       cci_read(imx728->regmap, IMX728_REG_VMAJOR, &major, &ret);
> +       if (ret != 0) {
> +               dev_err(imx728->dev, "Could not read PARAM_MAJOR_VER!");
> +               return ret;
> +       }
> +       cci_read(imx728->regmap, IMX728_REG_VMINOR, &minor, &ret);
> +       if (ret != 0) {
> +               dev_err(imx728->dev, "Could not read PARAM_MINOR_VER!");
> +               return ret;
> +       }
> +       dev_dbg(imx728->dev, "Got version: %lld.%lld", major, minor);
> +
> +       return 0;
> +}
> +
> +static int imx728_reset(struct imx728 *imx728)
> +{
> +
> +       int ret = 0;
> +
> +       // Prefer hardware reset if available.
> +       if (!IS_ERR_OR_NULL(imx728->reset_gpio)) {

Here can be ERR (although why?) but...

> +               gpiod_set_value_cansleep(imx728->reset_gpio, 1);
> +               usleep_range(1000, 10000);
> +               gpiod_set_value_cansleep(imx728->reset_gpio, 0);
> +               msleep(100);
> +       } else {
> +               // Software reset.
> +               cci_write(imx728->regmap, IMX728_REG_RESET_0, 0xc3, &ret);
> +               cci_update_bits(imx728->regmap, IMX728_REG_RESET_1, 0x1, 0x1, &ret);
> +               msleep(100);
> +       }
> +
> +       return ret;
> +}
> +
> +static int imx728_power_on(struct imx728 *imx728)
> +{
> +       int ret;
> +
> +       ret = clk_prepare_enable(imx728->clk);
> +       if (ret < 0)
> +               return ret;
> +
> +       imx728_reset(imx728);
> +       return 0;
> +}
> +
> +static int imx728_power_off(struct imx728 *imx728)
> +{
> +
> +       if (imx728->reset_gpio) {

Here cannot.

> +               gpiod_set_value_cansleep(imx728->reset_gpio, 1);
> +
> +               usleep_range(1, 10);
> +       }
> +       clk_disable_unprepare(imx728->clk);
> +       return 0;
> +}
> +


...

> +
> +static int imx728_set_stream(struct v4l2_subdev *sd, int enable)
> +{
> +       struct imx728 *imx728 = to_imx728(sd);
> +       int ret;
> +
> +       mutex_lock(&imx728->lock);

Just use guard. That's actually perfect candidate.


> +       if (imx728->streaming == enable) {
> +               mutex_unlock(&imx728->lock);
> +               return 0;
> +       }
> +
> +       if (enable) {
> +               ret = pm_runtime_get_sync(imx728->dev);
> +               if (ret < 0) {
> +                       pm_runtime_put_noidle(imx728->dev);
> +                       goto err_unlock;
> +               }
> +
> +               ret = imx728_start_stream(imx728);
> +               if (ret < 0)
> +                       goto err_runtime_put;
> +       } else {
> +               ret = imx728_stop_stream(imx728);
> +               if (ret < 0)
> +                       goto err_runtime_put;
> +               pm_runtime_mark_last_busy(imx728->dev);
> +               pm_runtime_put_autosuspend(imx728->dev);
> +       }
> +
> +       imx728->streaming = enable;
> +
> +       __v4l2_ctrl_grab(imx728->ctrl.h_flip, enable);
> +       __v4l2_ctrl_grab(imx728->ctrl.v_flip, enable);
> +
> +       mutex_unlock(&imx728->lock);
> +
> +       return 0;
> +
> +err_runtime_put:
> +       pm_runtime_put(imx728->dev);
> +
> +err_unlock:
> +       mutex_unlock(&imx728->lock);
> +       dev_err(imx728->dev,
> +               "%s: failed to setup streaming %d\n", __func__, ret);
> +       return ret;
> +}
> +
> +static const struct v4l2_subdev_core_ops imx728_core_ops = {
> +       .subscribe_event = v4l2_ctrl_subdev_subscribe_event,
> +       .unsubscribe_event = v4l2_event_subdev_unsubscribe,
> +};
> +
> +static const struct v4l2_subdev_video_ops imx728_subdev_video_ops = {
> +       .s_stream = imx728_set_stream,
> +};
> +
> +static const struct v4l2_subdev_pad_ops imx728_subdev_pad_ops = {
> +       .enum_frame_size = imx728_enum_frame_sizes,
> +       .enum_mbus_code = imx728_enum_mbus_code,
> +       .get_fmt = v4l2_subdev_get_fmt,
> +       .get_frame_desc = imx728_get_frame_desc,
> +       .get_frame_interval = imx728_get_frame_interval,
> +       .get_selection = imx728_get_selection,
> +       .set_fmt = imx728_set_fmt,
> +       .set_frame_interval = imx728_set_frame_interval,
> +       .set_routing = imx728_set_routing,
> +};
> +
> +static const struct v4l2_subdev_ops imx728_subdev_ops = {
> +       .core  = &imx728_core_ops,
> +       .video = &imx728_subdev_video_ops,
> +       .pad   = &imx728_subdev_pad_ops,
> +};
> +
> +static const struct v4l2_subdev_internal_ops imx728_internal_ops = {
> +       .init_state = imx728_init_state,
> +};
> +
> +
> +static const struct v4l2_ctrl_ops imx728_ctrl_ops = {
> +       .s_ctrl = imx728_set_ctrl,
> +};
> +
> +static int imx728_probe(struct i2c_client *client)
> +{
> +       struct imx728 *imx728;
> +       struct v4l2_subdev *sd;
> +       struct v4l2_ctrl_handler *ctrl_hdr;
> +       int ret;
> +
> +       imx728 = devm_kzalloc(&client->dev, sizeof(*imx728), GFP_KERNEL);
> +       if (!imx728)
> +               return -ENOMEM;
> +
> +       imx728->dev = &client->dev;
> +
> +       imx728->regmap = devm_cci_regmap_init_i2c(client, 16);
> +       if (IS_ERR(imx728->regmap))
> +               return PTR_ERR(imx728->regmap);
> +
> +       imx728->reset_gpio = devm_gpiod_get_optional(imx728->dev,
> +                                            "reset", GPIOD_OUT_LOW);
> +       if (IS_ERR(imx728->reset_gpio))
> +               return PTR_ERR(imx728->reset_gpio);

So can it be ERR after that point? Looks like not.



Best regards,
Krzysztof

Re: [PATCH 2/4] media: i2c: Add driver for Sony IMX728

[Sebastian LaVine]

On Wed Feb 12, 2025 at 3:11 PM EST, Krzysztof Kozlowski wrote:
> On 12/02/2025 20:56, Sebastian LaVine wrote:
>>
>> ...
>>
>> +static int imx728_reset(struct imx728 *imx728)
>> +{
>> +
>> +       int ret = 0;
>> +
>> +       // Prefer hardware reset if available.
>> +       if (!IS_ERR_OR_NULL(imx728->reset_gpio)) {
>
> Here can be ERR (although why?) but...
>
>> +               gpiod_set_value_cansleep(imx728->reset_gpio, 1);
>>
>> ...
>>
>> +static int imx728_power_off(struct imx728 *imx728)
>> +{
>> +
>> +       if (imx728->reset_gpio) {
>
> Here cannot.
>
>> +               gpiod_set_value_cansleep(imx728->reset_gpio, 1);
>> +
>> +               usleep_range(1, 10);
>> +       }
>> +       clk_disable_unprepare(imx728->clk);
>> +       return 0;
>> +}
>> +
>>
>> ...
>>
>> +static int imx728_probe(struct i2c_client *client)
>> +{
>> +       struct imx728 *imx728;
>> +       struct v4l2_subdev *sd;
>> +       struct v4l2_ctrl_handler *ctrl_hdr;
>> +       int ret;
>> +
>> +       imx728 = devm_kzalloc(&client->dev, sizeof(*imx728), GFP_KERNEL);
>> +       if (!imx728)
>> +               return -ENOMEM;
>> +
>> +       imx728->dev = &client->dev;
>> +
>> +       imx728->regmap = devm_cci_regmap_init_i2c(client, 16);
>> +       if (IS_ERR(imx728->regmap))
>> +               return PTR_ERR(imx728->regmap);
>> +
>> +       imx728->reset_gpio = devm_gpiod_get_optional(imx728->dev,
>> +                                            "reset", GPIOD_OUT_LOW);
>> +       if (IS_ERR(imx728->reset_gpio))
>> +               return PTR_ERR(imx728->reset_gpio);
>
> So can it be ERR after that point? Looks like not.
>

I see what you mean -- I'll change the check in imx728_reset to a simple
null check in v4. Thanks.

> (Jumping back up to previous inline feedback)
>
> ...
>
>> +
>> +static int imx728_set_stream(struct v4l2_subdev *sd, int enable)
>> +{
>> +       struct imx728 *imx728 = to_imx728(sd);
>> +       int ret;
>> +
>> +       mutex_lock(&imx728->lock);
>
> Just use guard. That's actually perfect candidate.
>

Okay -- I'll include this change in v4. I'm not so familiar with using
this interface, so please let me know if this is incorrect:

diff --git a/drivers/media/i2c/imx728.c b/drivers/media/i2c/imx728.c
index 4a6dfa0a6c58..d7d62e9917a4 100644
--- a/drivers/media/i2c/imx728.c
+++ b/drivers/media/i2c/imx728.c
@@ -9320,17 +9320,16 @@ static int imx728_set_stream(struct v4l2_subdev *sd, int enable)
        struct imx728 *imx728 = to_imx728(sd);
        int ret;

-       mutex_lock(&imx728->lock);
+       guard(mutex)(&imx728->lock);
+
-       if (imx728->streaming == enable) {
+       if (imx728->streaming == enable)
-               mutex_unlock(&imx728->lock);
                return 0;
-       }

        if (enable) {
                ret = pm_runtime_get_sync(imx728->dev);
                if (ret < 0) {
                        pm_runtime_put_noidle(imx728->dev);
-                       goto err_unlock;
+                       goto err;
                }

                ret = imx728_start_stream(imx728);
@@ -9349,15 +9348,12 @@ static int imx728_set_stream(struct v4l2_subdev *sd, int enable)
        __v4l2_ctrl_grab(imx728->ctrl.h_flip, enable);
        __v4l2_ctrl_grab(imx728->ctrl.v_flip, enable);

-       mutex_unlock(&imx728->lock);
-
        return 0;

 err_runtime_put:
        pm_runtime_put(imx728->dev);

-err_unlock:
-       mutex_unlock(&imx728->lock);
+err:
        dev_err(imx728->dev,
                "%s: failed to setup streaming %d\n", __func__, ret);
        return ret;


Thanks,

--
Sebastian

Please be aware that this email includes email addresses outside of the organization.

Re: [PATCH 2/4] media: i2c: Add driver for Sony IMX728

[Krzysztof Kozlowski]

On 26/02/2025 21:13, Sebastian LaVine wrote:
>> ...
>>
>>> +
>>> +static int imx728_set_stream(struct v4l2_subdev *sd, int enable)
>>> +{
>>> +       struct imx728 *imx728 = to_imx728(sd);
>>> +       int ret;
>>> +
>>> +       mutex_lock(&imx728->lock);
>>
>> Just use guard. That's actually perfect candidate.
>>
> 
> Okay -- I'll include this change in v4. I'm not so familiar with using
> this interface, so please let me know if this is incorrect:
> 


Yes, looks fine.

Best regards,
Krzysztof

Re: [PATCH 2/4] media: i2c: Add driver for Sony IMX728

[Laurent Pinchart]

Hi Sebastian,

Thank you for the patch.

I'll start with a partial review.

On Wed, Feb 12, 2025 at 02:56:54PM -0500, Sebastian LaVine wrote:
> Adds a driver for the Sony IMX728 image sensor.
> 
> Signed-off-by: Sebastian LaVine <slavine@d3embedded.com>
> Mentored-by: Stuart Burtner <sburtner@d3embedded.com>
> ---
>  MAINTAINERS                  |    1 +
>  arch/arm64/configs/defconfig |    1 +
>  drivers/media/i2c/Kconfig    |   12 +
>  drivers/media/i2c/Makefile   |    1 +
>  drivers/media/i2c/imx728.c   | 9655 ++++++++++++++++++++++++++++++++++
>  5 files changed, 9670 insertions(+)
>  create mode 100644 drivers/media/i2c/imx728.c

[snip]

> diff --git a/drivers/media/i2c/imx728.c b/drivers/media/i2c/imx728.c
> new file mode 100644
> index 000000000000..75120ca01ce6
> --- /dev/null
> +++ b/drivers/media/i2c/imx728.c
> @@ -0,0 +1,9655 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Sony IMX728 CMOS Image Sensor Driver
> + *
> + * Copyright (c) 2024-2025 Define Design Deploy Corp
> + */

[snip]

> +static const struct cci_reg_sequence imx728_wdr_12bit_3856x2176[] = {

This table is way too big, with over 8000 entries. Some are even
duplicated, with identical or different values for the same register. It
will take more than a second at 400kHz to program this.

At the very least I would expect a way to compact the table and make use
of I2C register address auto-increment. Default power-up values should
also likely be just dropped.

I haven't checked in details, but doesn't this table also contain tuning
data for your specific camera ?

[snip]

> +};

[snip]

> +static int imx728_get_frame_interval(struct v4l2_subdev *sd,
> +                                    struct v4l2_subdev_state *sd_state,
> +                                    struct v4l2_subdev_frame_interval *fi)
> +{
> +       struct imx728 *imx728 = to_imx728(sd);
> +
> +       fi->interval.numerator = 1;
> +       fi->interval.denominator = imx728->fps;
> +       return 0;
> +}
> +
> +static int imx728_set_frame_interval(struct v4l2_subdev *sd,
> +                                    struct v4l2_subdev_state *sd_state,
> +                                    struct v4l2_subdev_frame_interval *fi)
> +{
> +       struct imx728 *imx728 = to_imx728(sd);
> +       u32 req_fps;
> +
> +       mutex_lock(&imx728->lock);
> +
> +       if (fi->interval.numerator == 0 || fi->interval.denominator == 0) {
> +               fi->interval.denominator = IMX728_FRAMERATE_DEFAULT;
> +               fi->interval.numerator = 1;
> +       }
> +
> +       req_fps = clamp_val(DIV_ROUND_CLOSEST(fi->interval.denominator,
> +                                             fi->interval.numerator),
> +                           IMX728_FRAMERATE_MIN, IMX728_FRAMERATE_MAX);
> +
> +       fi->interval.numerator = 1;
> +       fi->interval.denominator = req_fps;
> +
> +       imx728->fps = req_fps;
> +
> +       mutex_unlock(&imx728->lock);
> +       dev_dbg(imx728->dev, "%s frame rate = %d\n", __func__, imx728->fps);
> +
> +       return 0;
> +}

The frame rate on raw sensors is controlled through h/v blanking. You
can drop thse functions, especially given that imx728->fps isn't used
anywhere else.

-- 
Regards,

Laurent Pinchart

Re: [PATCH 2/4] media: i2c: Add driver for Sony IMX728

[Sebastian LaVine]

On Thu Feb 13, 2025 at 5:19 AM EST, Laurent Pinchart wrote:
>
> ...
>
>> +static const struct cci_reg_sequence imx728_wdr_12bit_3856x2176[] = {
>
> This table is way too big, with over 8000 entries. Some are even
> duplicated, with identical or different values for the same register. It
> will take more than a second at 400kHz to program this.
>
> At the very least I would expect a way to compact the table and make use
> of I2C register address auto-increment. Default power-up values should
> also likely be just dropped.
>
> I haven't checked in details, but doesn't this table also contain tuning
> data for your specific camera ?
>

In my testing, it takes around two seconds to write this table to the sensor.

I can investigate how to condense the table further, though the
registers for this sensor are more complex than just writing values to
addresses. The meaning of certain address writes depend on previous
writes -- thus the "duplicated" writes you mentioned.

I do not believe this table contains tuning information for our camera
module in particular.

> [snip]
>
>> +};
>
> [snip]
>
>> +static int imx728_get_frame_interval(struct v4l2_subdev *sd,
>> +                                    struct v4l2_subdev_state *sd_state,
>> +                                    struct v4l2_subdev_frame_interval *fi)
>> +{
>> +       struct imx728 *imx728 = to_imx728(sd);
>> +
>> +       fi->interval.numerator = 1;
>> +       fi->interval.denominator = imx728->fps;
>> +       return 0;
>> +}
>> +
>> +static int imx728_set_frame_interval(struct v4l2_subdev *sd,
>> +                                    struct v4l2_subdev_state *sd_state,
>> +                                    struct v4l2_subdev_frame_interval *fi)
>> +{
>> +       struct imx728 *imx728 = to_imx728(sd);
>> +       u32 req_fps;
>> +
>> +       mutex_lock(&imx728->lock);
>> +
>> +       if (fi->interval.numerator == 0 || fi->interval.denominator == 0) {
>> +               fi->interval.denominator = IMX728_FRAMERATE_DEFAULT;
>> +               fi->interval.numerator = 1;
>> +       }
>> +
>> +       req_fps = clamp_val(DIV_ROUND_CLOSEST(fi->interval.denominator,
>> +                                             fi->interval.numerator),
>> +                           IMX728_FRAMERATE_MIN, IMX728_FRAMERATE_MAX);
>> +
>> +       fi->interval.numerator = 1;
>> +       fi->interval.denominator = req_fps;
>> +
>> +       imx728->fps = req_fps;
>> +
>> +       mutex_unlock(&imx728->lock);
>> +       dev_dbg(imx728->dev, "%s frame rate = %d\n", __func__, imx728->fps);
>> +
>> +       return 0;
>> +}
>
> The frame rate on raw sensors is controlled through h/v blanking. You
> can drop thse functions, especially given that imx728->fps isn't used
> anywhere else.

Okay, I will drop these functions in v4. Thanks.

--
Sebastian

Please be aware that this email includes email addresses outside of the organization.

Re: [PATCH 2/4] media: i2c: Add driver for Sony IMX728

[Sakari Ailus]

Hi Sebastian,

On Mon, Mar 10, 2025 at 03:39:02PM -0400, Sebastian LaVine wrote:
> On Thu Feb 13, 2025 at 5:19 AM EST, Laurent Pinchart wrote:
> >
> > ...
> >
> >> +static const struct cci_reg_sequence imx728_wdr_12bit_3856x2176[] = {
> >
> > This table is way too big, with over 8000 entries. Some are even
> > duplicated, with identical or different values for the same register. It
> > will take more than a second at 400kHz to program this.
> >
> > At the very least I would expect a way to compact the table and make use
> > of I2C register address auto-increment. Default power-up values should
> > also likely be just dropped.
> >
> > I haven't checked in details, but doesn't this table also contain tuning
> > data for your specific camera ?
> >
> 
> In my testing, it takes around two seconds to write this table to the sensor.
> 
> I can investigate how to condense the table further, though the
> registers for this sensor are more complex than just writing values to
> addresses. The meaning of certain address writes depend on previous
> writes -- thus the "duplicated" writes you mentioned.
> 
> I do not believe this table contains tuning information for our camera
> module in particular.

The amount of the data is significantly higher than what sensors mostly
have for configuring the analogue processing and does not look like
executable code either (I've seen that, too).

Any idea what that data is?

-- 
Kind regards,

Sakari Ailus

Re: [PATCH 2/4] media: i2c: Add driver for Sony IMX728

[Krzysztof Kozlowski]

On 12/02/2025 20:56, Sebastian LaVine wrote:
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 50bff3558d7d..27fb3c1be732 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -21890,6 +21890,7 @@ M:      Stuart Burtner <sburtner@d3embedded.com>
>  L:     linux-media@vger.kernel.org
>  S:     Odd Fixes
>  F:     Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml
> +F:     drivers/media/i2c/imx728.c
> 
>  SONY MEMORYSTICK SUBSYSTEM
>  M:     Maxim Levitsky <maximlevitsky@gmail.com>
> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
> index c62831e61586..0ff578bb4645 100644
> --- a/arch/arm64/configs/defconfig
> +++ b/arch/arm64/configs/defconfig
> @@ -852,6 +852,7 @@ CONFIG_VIDEO_TI_J721E_CSI2RX=m
>  CONFIG_VIDEO_HANTRO=m
>  CONFIG_VIDEO_IMX219=m
>  CONFIG_VIDEO_IMX412=m
> +CONFIG_VIDEO_IMX728=m
>  CONFIG_VIDEO_OV5640=m

This is not related to this patch and should target different subsystem
with its own explanation why you thing this should be in common defconfig.

Best regards,
Krzysztof

Re: [PATCH 2/4] media: i2c: Add driver for Sony IMX728

[Sebastian LaVine]

On Thu Feb 13, 2025 at 1:19 PM EST, Krzysztof Kozlowski wrote:
>
> ...
>
>> diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
>> index c62831e61586..0ff578bb4645 100644
>> --- a/arch/arm64/configs/defconfig
>> +++ b/arch/arm64/configs/defconfig
>> @@ -852,6 +852,7 @@ CONFIG_VIDEO_TI_J721E_CSI2RX=m
>>  CONFIG_VIDEO_HANTRO=m
>>  CONFIG_VIDEO_IMX219=m
>>  CONFIG_VIDEO_IMX412=m
>> +CONFIG_VIDEO_IMX728=m
>>  CONFIG_VIDEO_OV5640=m
>
> This is not related to this patch and should target different subsystem
> with its own explanation why you thing this should be in common defconfig.

Thanks, I will remove this in v4.

-Sebastian
Please be aware that this email includes email addresses outside of the organization.

Re: [PATCH 2/4] media: i2c: Add driver for Sony IMX728

[Markus Elfring]

> Adds a driver for the Sony IMX728 image sensor.

See also:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.14-rc3#n94


…
> +++ b/drivers/media/i2c/imx728.c
> @@ -0,0 +1,9655 @@
…
> +static int imx728_set_stream(struct v4l2_subdev *sd, int enable)
> +{
> +       struct imx728 *imx728 = to_imx728(sd);
> +       int ret;
> +
> +       mutex_lock(&imx728->lock);
…
> +       __v4l2_ctrl_grab(imx728->ctrl.v_flip, enable);
> +
> +       mutex_unlock(&imx728->lock);
…

Under which circumstances would you become interested to apply a statement
like “guard(mutex)(&imx728->lock);”?
https://elixir.bootlin.com/linux/v6.14-rc3/source/include/linux/mutex.h#L201

Regards,
Markus

Re: [PATCH 2/4] media: i2c: Add driver for Sony IMX728

[Sebastian LaVine]

Hello Markus,

On Wed Feb 19, 2025 at 12:51 PM EST, Markus Elfring wrote:
>> Adds a driver for the Sony IMX728 image sensor.
>
> See also:
> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/Documentation/process/submitting-patches.rst?h=v6.14-rc3#n94

Thanks, I'll modify the commit description in v4 to use the imperative
mood.

>
> …
>> +++ b/drivers/media/i2c/imx728.c
>> @@ -0,0 +1,9655 @@
> …
>> +static int imx728_set_stream(struct v4l2_subdev *sd, int enable)
>> +{
>> +       struct imx728 *imx728 = to_imx728(sd);
>> +       int ret;
>> +
>> +       mutex_lock(&imx728->lock);
> …
>> +       __v4l2_ctrl_grab(imx728->ctrl.v_flip, enable);
>> +
>> +       mutex_unlock(&imx728->lock);
> …
>
> Under which circumstances would you become interested to apply a statement
> like “guard(mutex)(&imx728->lock);”?
> https://elixir.bootlin.com/linux/v6.14-rc3/source/include/linux/mutex.h#L201

I will use this construct in v4.

Thanks,

--
Sebastian

Please be aware that this email includes email addresses outside of the organization.

[PATCH 3/4] arm64: dts: ti: k3-am62a7-sk: Add overlay for fusion 2 board

[Sebastian LaVine]

Adds an overlay for the Fusion 2 (FPD-Link IV) board on SK-AM62A.

Signed-off-by: Sebastian LaVine <slavine@d3embedded.com>
Mentored-by: Stuart Burtner <sburtner@d3embedded.com>
---
 MAINTAINERS                                   |   1 +
 arch/arm64/boot/dts/ti/Makefile               |   1 +
 .../boot/dts/ti/k3-am62a7-sk-fusion-2.dtso    | 115 ++++++++++++++++++
 3 files changed, 117 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso

diff --git a/MAINTAINERS b/MAINTAINERS
index 27fb3c1be732..bf6a48da0887 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21890,6 +21890,7 @@ M:      Stuart Burtner <sburtner@d3embedded.com>
 L:     linux-media@vger.kernel.org
 S:     Odd Fixes
 F:     Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml
+F:     arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
 F:     drivers/media/i2c/imx728.c

 SONY MEMORYSTICK SUBSYSTEM
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index f71360f14f23..fcd8d11e5678 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo
 # Boards with AM62Ax SoC
 dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
 dtb-$(CONFIG_ARCH_K3) += k3-am62a7-phyboard-lyra-rdk.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-fusion-2.dtbo

 # Boards with AM62Px SoC
 dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso b/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
new file mode 100644
index 000000000000..68e06d643bfd
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * DT Overlay for Fusion 2 (FPD-Link IV) board on SK-AM62A
+ * https://www.ti.com/tool/J7EXPAXEVM/
+ *
+ * Copyright (C) 2024 D3 Embedded - https://www.d3embedded.com
+ */
+
+ /dts-v1/;
+ /plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+&{/} {
+       clk_fusion2_25M_fixed: fixed-clock-25M {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <25000000>;
+       };
+};
+
+&exp2 {
+       p9-hog {
+               /* P9 - CSI_RSTz */
+               gpio-hog;
+               gpios = <9 GPIO_ACTIVE_HIGH>;
+               output-high;
+               line-name = "CSI_RSTz";
+       };
+
+       p19-hog {
+               /* P19 -CSI_SEL2 */
+               gpio-hog;
+               gpios = <19 GPIO_ACTIVE_HIGH>;
+               output-low;
+               line-name = "CSI_SEL2";
+       };
+};
+
+&main_i2c2 {
+       #address-cells = <1>;
+       #size-cells = <0>;
+       status = "okay";
+
+       i2c-switch@71 {
+               compatible = "nxp,pca9543";
+               #address-cells = <1>;
+               #size-cells = <0>;
+               reg = <0x71>;
+
+               i2c@1 {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       reg = <1>;
+
+                       deser@3d {
+                               compatible = "ti,ds90ub9702-q1";
+                               reg = <0x3d>;
+
+                               clock-names = "refclk";
+                               clocks = <&clk_fusion2_25M_fixed>;
+
+                               i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>;
+
+                               ds90ub9702_0_ports: ports {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+
+                                       /* CSI-2 TX */
+                                       port@4 {
+                                               reg = <4>;
+                                               ds90ub9702_0_csi_out: endpoint {
+                                                       data-lanes = <1 2 3 4>;
+                                                       clock-lanes = <0>;
+                                                       link-frequencies = /bits/ 64 <800000000>;
+                                                       remote-endpoint = <&csi2_phy0>;
+                                               };
+                                       };
+                               };
+
+                               ds90ub9702_0_links: links {
+                                       #address-cells = <1>;
+                                       #size-cells = <0>;
+                               };
+                       };
+               };
+       };
+};
+
+&cdns_csi2rx0 {
+       ports {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               csi0_port0: port@0 {
+                       reg = <0>;
+                       status = "okay";
+
+                       csi2_phy0: endpoint {
+                               remote-endpoint = <&ds90ub9702_0_csi_out>;
+                               data-lanes = <1 2 3 4>;
+                               clock-lanes = <0>;
+                               link-frequencies = /bits/ 64 <800000000>;
+                       };
+               };
+       };
+};
+
+&ti_csi2rx0 {
+       status = "okay";
+};
+
+&dphy0 {
+       status = "okay";
+};
--
2.34.1

Please be aware that this email includes email addresses outside of the organization.

Re: [PATCH 3/4] arm64: dts: ti: k3-am62a7-sk: Add overlay for fusion 2 board

[Krzysztof Kozlowski]

On 12/02/2025 20:56, Sebastian LaVine wrote:
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 27fb3c1be732..bf6a48da0887 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -21890,6 +21890,7 @@ M:      Stuart Burtner <sburtner@d3embedded.com>
>  L:     linux-media@vger.kernel.org
>  S:     Odd Fixes
>  F:     Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml
> +F:     arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
>  F:     drivers/media/i2c/imx728.c
> 
>  SONY MEMORYSTICK SUBSYSTEM
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index f71360f14f23..fcd8d11e5678 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo
>  # Boards with AM62Ax SoC
>  dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
>  dtb-$(CONFIG_ARCH_K3) += k3-am62a7-phyboard-lyra-rdk.dtb
> +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-fusion-2.dtbo

I don't see the overlay being applied.

> 
>  # Boards with AM62Px SoC
>  dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
> diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso b/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
> new file mode 100644
> index 000000000000..68e06d643bfd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
> @@ -0,0 +1,115 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * DT Overlay for Fusion 2 (FPD-Link IV) board on SK-AM62A
> + * https://www.ti.com/tool/J7EXPAXEVM/
> + *
> + * Copyright (C) 2024 D3 Embedded - https://www.d3embedded.com
> + */
> +
> + /dts-v1/;
> + /plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +&{/} {
> +       clk_fusion2_25M_fixed: fixed-clock-25M {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <25000000>;
> +       };
> +};
> +
> +&exp2 {
> +       p9-hog {
> +               /* P9 - CSI_RSTz */
> +               gpio-hog;
> +               gpios = <9 GPIO_ACTIVE_HIGH>;
> +               output-high;
> +               line-name = "CSI_RSTz";
> +       };
> +
> +       p19-hog {
> +               /* P19 -CSI_SEL2 */
> +               gpio-hog;
> +               gpios = <19 GPIO_ACTIVE_HIGH>;
> +               output-low;
> +               line-name = "CSI_SEL2";
> +       };
> +};
> +
> +&main_i2c2 {
> +       #address-cells = <1>;
> +       #size-cells = <0>;
> +       status = "okay";
> +
> +       i2c-switch@71 {
> +               compatible = "nxp,pca9543";
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               reg = <0x71>;

reg is always the second property. See DTS coding style.



Best regards,
Krzysztof

Re: [PATCH 3/4] arm64: dts: ti: k3-am62a7-sk: Add overlay for fusion 2 board

[Sebastian LaVine]

On Wed Feb 12, 2025 at 3:13 PM EST, Krzysztof Kozlowski wrote:
> On 12/02/2025 20:56, Sebastian LaVine wrote:
>>
>> ...
>>
>> +
>> +       i2c-switch@71 {
>> +               compatible = "nxp,pca9543";
>> +               #address-cells = <1>;
>> +               #size-cells = <0>;
>> +               reg = <0x71>;
>
> reg is always the second property. See DTS coding style.
>

Ack, will fix in v4.

--
Sebastian

Please be aware that this email includes email addresses outside of the organization.

Re: [PATCH 3/4] arm64: dts: ti: k3-am62a7-sk: Add overlay for fusion 2 board

[Nishanth Menon]

On 14:56-20250212, Sebastian LaVine wrote:
> Adds an overlay for the Fusion 2 (FPD-Link IV) board on SK-AM62A.
> 
> Signed-off-by: Sebastian LaVine <slavine@d3embedded.com>
> Mentored-by: Stuart Burtner <sburtner@d3embedded.com>
> ---
>  MAINTAINERS                                   |   1 +
>  arch/arm64/boot/dts/ti/Makefile               |   1 +
>  .../boot/dts/ti/k3-am62a7-sk-fusion-2.dtso    | 115 ++++++++++++++++++
>  3 files changed, 117 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 27fb3c1be732..bf6a48da0887 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -21890,6 +21890,7 @@ M:      Stuart Burtner <sburtner@d3embedded.com>
>  L:     linux-media@vger.kernel.org
>  S:     Odd Fixes
>  F:     Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml
> +F:     arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso

NAK. please do not send overlays from media tree. they should go via SoC
ARM tree.

>  F:     drivers/media/i2c/imx728.c
> 
>  SONY MEMORYSTICK SUBSYSTEM
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index f71360f14f23..fcd8d11e5678 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo
>  # Boards with AM62Ax SoC
>  dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
>  dtb-$(CONFIG_ARCH_K3) += k3-am62a7-phyboard-lyra-rdk.dtb
> +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-fusion-2.dtbo
> 
>  # Boards with AM62Px SoC
>  dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
> diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso b/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
> new file mode 100644
> index 000000000000..68e06d643bfd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
> @@ -0,0 +1,115 @@
> +// SPDX-License-Identifier: GPL-2.0

Would prefer GPL-2.0 OR MIT in line with rest of TI EVM licensing for
DT.

> +/*
> + * DT Overlay for Fusion 2 (FPD-Link IV) board on SK-AM62A
> + * https://www.ti.com/tool/J7EXPAXEVM/
> + *
> + * Copyright (C) 2024 D3 Embedded - https://www.d3embedded.com
> + */
> +
> + /dts-v1/;
> + /plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +

That said, the fusion-2 board interfaces with a bunch of evms as well.
wondering if we should re-organize to better reuse stuff.

> +&{/} {
> +       clk_fusion2_25M_fixed: fixed-clock-25M {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <25000000>;
> +       };
> +};
> +
> +&exp2 {
> +       p9-hog {
> +               /* P9 - CSI_RSTz */
> +               gpio-hog;
> +               gpios = <9 GPIO_ACTIVE_HIGH>;
> +               output-high;
> +               line-name = "CSI_RSTz";
> +       };
> +
> +       p19-hog {
> +               /* P19 -CSI_SEL2 */
> +               gpio-hog;
> +               gpios = <19 GPIO_ACTIVE_HIGH>;
> +               output-low;
> +               line-name = "CSI_SEL2";
> +       };
> +};
> +
> +&main_i2c2 {
> +       #address-cells = <1>;
> +       #size-cells = <0>;
> +       status = "okay";
> +
> +       i2c-switch@71 {
> +               compatible = "nxp,pca9543";
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               reg = <0x71>;
> +
> +               i2c@1 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <1>;
> +
> +                       deser@3d {
> +                               compatible = "ti,ds90ub9702-q1";
> +                               reg = <0x3d>;
> +
> +                               clock-names = "refclk";
> +                               clocks = <&clk_fusion2_25M_fixed>;
> +
> +                               i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>;
> +
> +                               ds90ub9702_0_ports: ports {
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +
> +                                       /* CSI-2 TX */
> +                                       port@4 {
> +                                               reg = <4>;
> +                                               ds90ub9702_0_csi_out: endpoint {
> +                                                       data-lanes = <1 2 3 4>;
> +                                                       clock-lanes = <0>;
> +                                                       link-frequencies = /bits/ 64 <800000000>;
> +                                                       remote-endpoint = <&csi2_phy0>;
> +                                               };
> +                                       };
> +                               };
> +
> +                               ds90ub9702_0_links: links {
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +                               };
> +                       };
> +               };
> +       };
> +};
> +
> +&cdns_csi2rx0 {
> +       ports {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               csi0_port0: port@0 {
> +                       reg = <0>;
> +                       status = "okay";
> +
> +                       csi2_phy0: endpoint {
> +                               remote-endpoint = <&ds90ub9702_0_csi_out>;
> +                               data-lanes = <1 2 3 4>;
> +                               clock-lanes = <0>;
> +                               link-frequencies = /bits/ 64 <800000000>;
> +                       };
> +               };
> +       };
> +};
> +
> +&ti_csi2rx0 {
> +       status = "okay";
> +};
> +
> +&dphy0 {
> +       status = "okay";
> +};
> --
> 2.34.1
> 
> Please be aware that this email includes email addresses outside of the organization.

Drop this. this is already a public mailing list :)

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH 3/4] arm64: dts: ti: k3-am62a7-sk: Add overlay for fusion 2 board

[Sebastian LaVine]

Hello Nishanth,

On Tue Feb 18, 2025 at 1:45 PM EST, Nishanth Menon wrote:
> On 14:56-20250212, Sebastian LaVine wrote:
>> Adds an overlay for the Fusion 2 (FPD-Link IV) board on SK-AM62A.
>>
>> Signed-off-by: Sebastian LaVine <slavine@d3embedded.com>
>> Mentored-by: Stuart Burtner <sburtner@d3embedded.com>
>> ---
>>  MAINTAINERS                                   |   1 +
>>  arch/arm64/boot/dts/ti/Makefile               |   1 +
>>  .../boot/dts/ti/k3-am62a7-sk-fusion-2.dtso    | 115 ++++++++++++++++++
>>  3 files changed, 117 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
>>
>> diff --git a/MAINTAINERS b/MAINTAINERS
>> index 27fb3c1be732..bf6a48da0887 100644
>> --- a/MAINTAINERS
>> +++ b/MAINTAINERS
>> @@ -21890,6 +21890,7 @@ M:      Stuart Burtner <sburtner@d3embedded.com>
>>  L:     linux-media@vger.kernel.org
>>  S:     Odd Fixes
>>  F:     Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml
>> +F:     arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
>
> NAK. please do not send overlays from media tree. they should go via SoC
> ARM tree.

Ack, will send as separate series in v4.

>>
>> ...
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso b/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
>> new file mode 100644
>> index 000000000000..68e06d643bfd
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
>> @@ -0,0 +1,115 @@
>> +// SPDX-License-Identifier: GPL-2.0
>
> Would prefer GPL-2.0 OR MIT in line with rest of TI EVM licensing for
> DT.
>

Ack, will fix in v4.

>>
>> ...
>>
>> --
>> 2.34.1
>>
>> Please be aware that this email includes email addresses outside of the organization.
>
> Drop this. this is already a public mailing list :)

I'll look into `b4 relay` for future patches to get around this.

Thanks,

--
Sebastian

Please be aware that this email includes email addresses outside of the organization.

Re: [PATCH 3/4] arm64: dts: ti: k3-am62a7-sk: Add overlay for fusion 2 board

[Vaishnav Achath]

Hi Sebastian,

On 13/02/25 01:26, Sebastian LaVine wrote:
> Adds an overlay for the Fusion 2 (FPD-Link IV) board on SK-AM62A.
> 

Were you able to test and get this working without additional patches on 
linux-next?

The multi-steam support for J721E-CSI2RX and CDNS-CSI2RX drivers are 
still WIP [1] and as per my understanding you will need those to get 
this overlay functional.

1 - 
https://lore.kernel.org/all/20240627-multistream-v2-0-6ae96c54c1c3@ti.com/

Thanks and Regards,
Vaishnav

> Signed-off-by: Sebastian LaVine <slavine@d3embedded.com>
> Mentored-by: Stuart Burtner <sburtner@d3embedded.com>
> ---
>   MAINTAINERS                                   |   1 +
>   arch/arm64/boot/dts/ti/Makefile               |   1 +
>   .../boot/dts/ti/k3-am62a7-sk-fusion-2.dtso    | 115 ++++++++++++++++++
>   3 files changed, 117 insertions(+)
>   create mode 100644 arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 27fb3c1be732..bf6a48da0887 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -21890,6 +21890,7 @@ M:      Stuart Burtner <sburtner@d3embedded.com>
>   L:     linux-media@vger.kernel.org
>   S:     Odd Fixes
>   F:     Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml
> +F:     arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
>   F:     drivers/media/i2c/imx728.c
> 
>   SONY MEMORYSTICK SUBSYSTEM
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index f71360f14f23..fcd8d11e5678 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -31,6 +31,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-am62-lp-sk-nand.dtbo
>   # Boards with AM62Ax SoC
>   dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk.dtb
>   dtb-$(CONFIG_ARCH_K3) += k3-am62a7-phyboard-lyra-rdk.dtb
> +dtb-$(CONFIG_ARCH_K3) += k3-am62a7-sk-fusion-2.dtbo
> 
>   # Boards with AM62Px SoC
>   dtb-$(CONFIG_ARCH_K3) += k3-am62p5-sk.dtb
> diff --git a/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso b/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
> new file mode 100644
> index 000000000000..68e06d643bfd
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
> @@ -0,0 +1,115 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * DT Overlay for Fusion 2 (FPD-Link IV) board on SK-AM62A
> + * https://www.ti.com/tool/J7EXPAXEVM/
> + *
> + * Copyright (C) 2024 D3 Embedded - https://www.d3embedded.com
> + */
> +
> + /dts-v1/;
> + /plugin/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +
> +&{/} {
> +       clk_fusion2_25M_fixed: fixed-clock-25M {
> +               compatible = "fixed-clock";
> +               #clock-cells = <0>;
> +               clock-frequency = <25000000>;
> +       };
> +};
> +
> +&exp2 {
> +       p9-hog {
> +               /* P9 - CSI_RSTz */
> +               gpio-hog;
> +               gpios = <9 GPIO_ACTIVE_HIGH>;
> +               output-high;
> +               line-name = "CSI_RSTz";
> +       };
> +
> +       p19-hog {
> +               /* P19 -CSI_SEL2 */
> +               gpio-hog;
> +               gpios = <19 GPIO_ACTIVE_HIGH>;
> +               output-low;
> +               line-name = "CSI_SEL2";
> +       };
> +};
> +
> +&main_i2c2 {
> +       #address-cells = <1>;
> +       #size-cells = <0>;
> +       status = "okay";
> +
> +       i2c-switch@71 {
> +               compatible = "nxp,pca9543";
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +               reg = <0x71>;
> +
> +               i2c@1 {
> +                       #address-cells = <1>;
> +                       #size-cells = <0>;
> +                       reg = <1>;
> +
> +                       deser@3d {
> +                               compatible = "ti,ds90ub9702-q1";
> +                               reg = <0x3d>;
> +
> +                               clock-names = "refclk";
> +                               clocks = <&clk_fusion2_25M_fixed>;
> +
> +                               i2c-alias-pool = <0x4a 0x4b 0x4c 0x4d 0x4e 0x4f>;
> +
> +                               ds90ub9702_0_ports: ports {
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +
> +                                       /* CSI-2 TX */
> +                                       port@4 {
> +                                               reg = <4>;
> +                                               ds90ub9702_0_csi_out: endpoint {
> +                                                       data-lanes = <1 2 3 4>;
> +                                                       clock-lanes = <0>;
> +                                                       link-frequencies = /bits/ 64 <800000000>;
> +                                                       remote-endpoint = <&csi2_phy0>;
> +                                               };
> +                                       };
> +                               };
> +
> +                               ds90ub9702_0_links: links {
> +                                       #address-cells = <1>;
> +                                       #size-cells = <0>;
> +                               };
> +                       };
> +               };
> +       };
> +};
> +
> +&cdns_csi2rx0 {
> +       ports {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               csi0_port0: port@0 {
> +                       reg = <0>;
> +                       status = "okay";
> +
> +                       csi2_phy0: endpoint {
> +                               remote-endpoint = <&ds90ub9702_0_csi_out>;
> +                               data-lanes = <1 2 3 4>;
> +                               clock-lanes = <0>;
> +                               link-frequencies = /bits/ 64 <800000000>;
> +                       };
> +               };
> +       };
> +};
> +
> +&ti_csi2rx0 {
> +       status = "okay";
> +};
> +
> +&dphy0 {
> +       status = "okay";
> +};
> --
> 2.34.1
> 
> Please be aware that this email includes email addresses outside of the organization.

Re: [PATCH 3/4] arm64: dts: ti: k3-am62a7-sk: Add overlay for fusion 2 board

[Sebastian LaVine]

On Tue Feb 18, 2025 at 2:07 PM EST, Vaishnav Achath wrote:
> Hi Sebastian,
>
> On 13/02/25 01:26, Sebastian LaVine wrote:
>> Adds an overlay for the Fusion 2 (FPD-Link IV) board on SK-AM62A.
>>
>
> Were you able to test and get this working without additional patches on
> linux-next?
>
> The multi-steam support for J721E-CSI2RX and CDNS-CSI2RX drivers are
> still WIP [1] and as per my understanding you will need those to get
> this overlay functional.
>
> 1 -
> https://lore.kernel.org/all/20240627-multistream-v2-0-6ae96c54c1c3@ti.com/

Thanks for this -- I'll hold off on the overlays for the next series
revision.

--

Sebastian

Please be aware that this email includes email addresses outside of the organization.

Re: [PATCH 3/4] arm64: dts: ti: k3-am62a7-sk: Add overlay for fusion 2 board

[Tomi Valkeinen]

Hi,

On 12/02/2025 21:56, Sebastian LaVine wrote:

> + * DT Overlay for Fusion 2 (FPD-Link IV) board on SK-AM62A
> + * https://www.ti.com/tool/J7EXPAXEVM/

The link doesn't work.

  Tomi

Re: [PATCH 3/4] arm64: dts: ti: k3-am62a7-sk: Add overlay for fusion 2 board

[Sebastian LaVine]

Hi Tomi,

On Wed Feb 19, 2025 at 4:31 AM EST, Tomi Valkeinen wrote:
> Hi,
>
> On 12/02/2025 21:56, Sebastian LaVine wrote:
>
>> + * DT Overlay for Fusion 2 (FPD-Link IV) board on SK-AM62A
>> + * https://www.ti.com/tool/J7EXPAXEVM/
>
> The link doesn't work.
>
>   Tomi

Thanks, I'll use the corrected link[0] in v4.

https://www.ti.com/tool/J7EXPA01EVM

--
Sebastian

Please be aware that this email includes email addresses outside of the organization.

[PATCH 4/4] arm64: dts: ti: Add overlays for IMX728 RCM

[Sebastian LaVine]

Adds overlays for the D3 IMX728 RCM.

Only a connection on port 0 is currently supported.

Signed-off-by: Sebastian LaVine <slavine@d3embedded.com>
Mentored-by: Stuart Burtner <sburtner@d3embedded.com>
---
 MAINTAINERS                                   |   1 +
 arch/arm64/boot/dts/ti/Makefile               |   3 +
 .../dts/ti/k3-fpdlink-imx728-rcm-0-0.dtso     | 108 ++++++++++++++++++
 3 files changed, 112 insertions(+)
 create mode 100644 arch/arm64/boot/dts/ti/k3-fpdlink-imx728-rcm-0-0.dtso

diff --git a/MAINTAINERS b/MAINTAINERS
index bf6a48da0887..f109b5dc8fa5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21891,6 +21891,7 @@ L:      linux-media@vger.kernel.org
 S:     Odd Fixes
 F:     Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml
 F:     arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
+F:     arch/arm64/boot/dts/ti/k3-fpdlink-imx728-rcm-0-0.dtso
 F:     drivers/media/i2c/imx728.c

 SONY MEMORYSTICK SUBSYSTEM
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index fcd8d11e5678..6c8bbea246f1 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -240,6 +240,9 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
        k3-j784s4-evm-quad-port-eth-exp1.dtb \
        k3-j784s4-evm-usxgmii-exp1-exp2.dtb

+# FPDLink Sensors
+dtb-$(CONFIG_ARCH_K3) += k3-fpdlink-imx728-rcm-0-0.dtbo
+
 # Enable support for device-tree overlays
 DTC_FLAGS_k3-am625-beagleplay += -@
 DTC_FLAGS_k3-am625-phyboard-lyra-rdk += -@
diff --git a/arch/arm64/boot/dts/ti/k3-fpdlink-imx728-rcm-0-0.dtso b/arch/arm64/boot/dts/ti/k3-fpdlink-imx728-rcm-0-0.dtso
new file mode 100644
index 000000000000..97631184ff65
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-fpdlink-imx728-rcm-0-0.dtso
@@ -0,0 +1,108 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * D3 IMX728 FPD-Link 4 Camera Module
+ *
+ * Copyright (c) 2024 Define Design Deploy Corp - https://www.d3embedded.com
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+
+&{/} {
+       clk_imx728_fixed_00: imx728-inck-00 {
+               compatible = "fixed-clock";
+               #clock-cells = <0>;
+               clock-frequency = <24000000>;
+       };
+};
+
+&ds90ub9702_0_ports {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       /* FPDLink RX 0 */
+       port@0 {
+               reg = <0>;
+               ub9702_fpd4_1_in: endpoint {
+                       remote-endpoint = <&ub971_1_out>;
+               };
+       };
+};
+
+&ds90ub9702_0_links {
+       #address-cells = <1>;
+       #size-cells = <0>;
+
+       link@0 {
+               reg = <0>;
+               i2c-alias = <0x44>;
+
+               ti,cdr-mode = <1>;
+               ti,rx-mode = <3>;
+
+               serializer: serializer {
+                       compatible = "ti,ds90ub971-q1";
+                       gpio-controller;
+                       #gpio-cells = <2>;
+
+                       #clock-cells = <0>;
+
+                       ports {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               port@0 {
+                                       reg = <0>;
+                                       ub971_1_in: endpoint {
+                                               data-lanes = <1 2 3 4>;
+                                               remote-endpoint = <&sensor_1_out>;
+                                       };
+                               };
+
+                               port@1 {
+                                       reg = <1>;
+
+                                       ub971_1_out: endpoint {
+                                               remote-endpoint = <&ub9702_fpd4_1_in>;
+                                       };
+                               };
+                       };
+
+                       i2c {
+                               #address-cells = <1>;
+                               #size-cells = <0>;
+
+                               sens_exp: gpio@70 {
+                                       compatible = "nxp,pca9538";
+                                       reg = <0x70>;
+                                       gpio-controller;
+                                       #gpio-cells = <2>;
+                                       gpio-line-names = "IMG_RESET", "IMG_ERR0",
+                                                         "IMG_ERR1", "IMG_GPI0",
+                                                         "IMG_GPI1", "NC",
+                                                         "NC", "NC";
+                               };
+
+                               sensor@1a {
+                                       compatible = "sony,imx728";
+                                       reg = <0x1a>;
+
+                                       clocks = <&clk_imx728_fixed_00>;
+                                       clock-names = "inck";
+
+                                       reset-gpios = <&sens_exp 0 GPIO_ACTIVE_LOW>;
+                                       error0-gpios = <&sens_exp 1 GPIO_ACTIVE_HIGH>;
+                                       error1-gpios = <&sens_exp 2 GPIO_ACTIVE_HIGH>;
+
+                                       port {
+                                               sensor_1_out: endpoint {
+                                                       remote-endpoint = <&ub971_1_in>;
+                                               };
+                                       };
+                               };
+                       };
+               };
+       };
+};
--
2.34.1

Please be aware that this email includes email addresses outside of the organization.

Re: [PATCH 4/4] arm64: dts: ti: Add overlays for IMX728 RCM

[Nishanth Menon]

On 14:56-20250212, Sebastian LaVine wrote:
> Adds overlays for the D3 IMX728 RCM.
> 
> Only a connection on port 0 is currently supported.
> 
> Signed-off-by: Sebastian LaVine <slavine@d3embedded.com>
> Mentored-by: Stuart Burtner <sburtner@d3embedded.com>
> ---
>  MAINTAINERS                                   |   1 +
>  arch/arm64/boot/dts/ti/Makefile               |   3 +
>  .../dts/ti/k3-fpdlink-imx728-rcm-0-0.dtso     | 108 ++++++++++++++++++
>  3 files changed, 112 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/ti/k3-fpdlink-imx728-rcm-0-0.dtso
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index bf6a48da0887..f109b5dc8fa5 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -21891,6 +21891,7 @@ L:      linux-media@vger.kernel.org
>  S:     Odd Fixes
>  F:     Documentation/devicetree/bindings/media/i2c/sony,imx728.yaml
>  F:     arch/arm64/boot/dts/ti/k3-am62a7-sk-fusion-2.dtso
> +F:     arch/arm64/boot/dts/ti/k3-fpdlink-imx728-rcm-0-0.dtso

Please route dts via SoC tree.

>  F:     drivers/media/i2c/imx728.c
> 
>  SONY MEMORYSTICK SUBSYSTEM
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index fcd8d11e5678..6c8bbea246f1 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -240,6 +240,9 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \
[...]

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH 0/4] media: i2c: Add driver for Sony IMX728

[Krzysztof Kozlowski]

On 12/02/2025 20:56, Sebastian LaVine wrote:
> This series adds a V4L2 sensor driver for the Sony IMX728, and related
> devicetree overlays.
> 
> v4l2-compliance 1.26.1-5142, 64 bits, 64-bit time_t
> v4l2-compliance SHA: 4aee01a02792 2023-12-12 21:40:38

Your Cc list is neither correct (incorrect my email) nor reasonable
size. You cc-ed several maintainers which are not responsible for these
files.

For next version or any resend:

Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC (and consider --no-git-fallback argument, so you will
not CC people just because they made one commit years ago). It might
happen, that command when run on an older kernel, gives you outdated
entries. Therefore please be sure you base your patches on recent Linux
kernel.

Tools like b4 or scripts/get_maintainer.pl provide you proper list of
people, so fix your workflow. Tools might also fail if you work on some
ancient tree (don't, instead use mainline) or work on fork of kernel
(don't, instead use mainline). Just use b4 and everything should be
fine, although remember about `b4 prep --auto-to-cc` if you added new
patches to the patchset.

Best regards,
Krzysztof

Re: [PATCH 0/4] media: i2c: Add driver for Sony IMX728

[Sebastian LaVine]

Hello Krzysztof,

On Wed Feb 12, 2025 at 3:04 PM EST, Krzysztof Kozlowski wrote:
> On 12/02/2025 20:56, Sebastian LaVine wrote:
>> This series adds a V4L2 sensor driver for the Sony IMX728, and related
>> devicetree overlays.
>>
>> v4l2-compliance 1.26.1-5142, 64 bits, 64-bit time_t
>> v4l2-compliance SHA: 4aee01a02792 2023-12-12 21:40:38
>
> Your Cc list is neither correct (incorrect my email) nor reasonable
> size. You cc-ed several maintainers which are not responsible for these
> files.
>
> For next version or any resend:
>
> Please use scripts/get_maintainers.pl to get a list of necessary people
> and lists to CC (and consider --no-git-fallback argument, so you will
> not CC people just because they made one commit years ago). It might
> happen, that command when run on an older kernel, gives you outdated
> entries. Therefore please be sure you base your patches on recent Linux
> kernel.

Apologies for the extra noise -- the list of folks I CC'd was obtained
using scripts/get_maintainers.pl, and the impression I got from the
documentation was that all of the people that are listed from that
command should be CC'd. I will be sure to prune the list more strictly
next time.

Thanks,
Sebastian
Please be aware that this email includes email addresses outside of the organization.

Re: [PATCH 0/4] media: i2c: Add driver for Sony IMX728

[Kieran Bingham]

Hi Sebastian,

Quoting Sebastian LaVine (2025-02-12 19:56:52)
<snip>
> 
> Total for device /dev/v4l-subdev4: 44, Succeeded: 44, Failed: 0, Warnings: 0
> 
> 
> This is a v3 of a series that was originally sent last summer[0].
> 
> [0]: https://lore.kernel.org/r/linux-media/20240628-imx728-driver-v2-0-80efa6774286@d3engineering.com/

This version of the driver was authored by "Spencer Hill
<shill@d3engineering.com>" who seems to no longer be credited. Is this
intentional?

Does his original Signed-off-by: tag need to be kept at least ? Or
perhaps Co-Authored-by: ?

--
Kieran


> 
> v2 -> v3:
> - Update maintainer
> - Update bindings example
> - Add devicetree overlays
> - The driver now supports SRGGB12_1X12, not SRGGB10_1X10
> - The driver now outputs at 3856x2176, not 2840x2160
> - Fixed exposure, again controls
> - Removed duplicate register writes (removed repeat HDR writes, etc)
> - Fixed imx728_wait_for_state use of the cci_* API
> - Re-added _imx728_set_routing (necessary for imx728_init_state)
> 
> Sebastian LaVine (4):
>   media: dt-bindings: Add Sony IMX728
>   media: i2c: Add driver for Sony IMX728
>   arm64: dts: ti: k3-am62a7-sk: Add overlay for fusion 2 board
>   arm64: dts: ti: Add overlays for IMX728 RCM

Re: [PATCH 0/4] media: i2c: Add driver for Sony IMX728

[Sebastian LaVine]

Hello Kieran,

On Thu Feb 13, 2025 at 5:40 AM EST, Kieran Bingham wrote:
> Hi Sebastian,
>
> Quoting Sebastian LaVine (2025-02-12 19:56:52)
> <snip>
>>
>> Total for device /dev/v4l-subdev4: 44, Succeeded: 44, Failed: 0, Warnings: 0
>>
>>
>> This is a v3 of a series that was originally sent last summer[0].
>>
>> [0]: https://lore.kernel.org/r/linux-media/20240628-imx728-driver-v2-0-80efa6774286@d3engineering.com/
>
> This version of the driver was authored by "Spencer Hill
> <shill@d3engineering.com>" who seems to no longer be credited. Is this
> intentional?
>
> Does his original Signed-off-by: tag need to be kept at least ? Or
> perhaps Co-Authored-by: ?
>

Yes, the original patch series was authored by Spencer -- I removed his
name as he is no longer with our company and therefore his email address
is no longer a valid way to contact him. I am not sure what the
convention is for this. I would be happy to re-add his name and former
email address to the Git trailers if this is desired.

Thank you,

--
Sebastian

Please be aware that this email includes email addresses outside of the organization.