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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac3efd8f37asm645336266b.179.2025.03.24.01.35.01 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 24 Mar 2025 01:35:01 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 24 Mar 2025 09:35:00 +0100 Message-Id: Cc: "Bjorn Andersson" , "Michael Turquette" , "Stephen Boyd" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Taniya Das" , "Konrad Dybcio" , <~postmarketos/upstreaming@lists.sr.ht>, , , , , Subject: Re: [PATCH 3/3] arm64: dts: qcom: sm6350: Add video clock controller From: "Luca Weiss" To: "Dmitry Baryshkov" X-Mailer: aerc 0.20.1-0-g2ecb8770224a References: <20250321-sm6350-videocc-v1-0-c5ce1f1483ee@fairphone.com> <20250321-sm6350-videocc-v1-3-c5ce1f1483ee@fairphone.com> In-Reply-To: On Fri Mar 21, 2025 at 5:23 PM CET, Dmitry Baryshkov wrote: > On 21/03/2025 18:15, Luca Weiss wrote: >> Hi Dmitry, >>=20 >> On Fri Mar 21, 2025 at 4:56 PM CET, Dmitry Baryshkov wrote: >>> On Fri, Mar 21, 2025 at 03:45:01PM +0100, Luca Weiss wrote: >>>> Add a node for the videocc found on the SM6350 SoC. >>>> >>>> Signed-off-by: Luca Weiss >>>> --- >>>> arch/arm64/boot/dts/qcom/sm6350.dtsi | 14 ++++++++++++++ >>>> 1 file changed, 14 insertions(+) >>>> >>>> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dt= s/qcom/sm6350.dtsi >>>> index 00ad1d09a19558d9e2bc61f1a81a36d466adc88e..ab7118b4f8f8cea56a3957= e9df67ee1cd74820a6 100644 >>>> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi >>>> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi >>>> @@ -1952,6 +1952,20 @@ usb_1_dwc3_ss_out: endpoint { >>>> }; >>>> }; >>>> =20 >>>> + videocc: clock-controller@aaf0000 { >>>> + compatible =3D "qcom,sm6350-videocc"; >>>> + reg =3D <0 0x0aaf0000 0 0x10000>; >>> >>> 0x0, please. >>=20 >> There's currently 80 cases of 0 and 20 of 0x0 in this file, is 0x0 >> the preferred way nowadays? >>=20 >> If so, shall I also change 0 to 0x0 for reg in a separate patch? > > I'd say, yes, please, if Bjorn / Konrad do not object. Sure, I'll just send a patch as part of v2, there's no explicit dependency of the series on it, so it can also just be NACKed and ignored if so desired. Regards Luca > >>=20 >> Regards >> Luca >>=20 >>> >>>> + clocks =3D <&gcc GCC_VIDEO_AHB_CLK>, >>>> + <&rpmhcc RPMH_CXO_CLK>, >>>> + <&sleep_clk>; >>>> + clock-names =3D "iface", >>>> + "bi_tcxo", >>>> + "sleep_clk"; >>>> + #clock-cells =3D <1>; >>>> + #reset-cells =3D <1>; >>>> + #power-domain-cells =3D <1>; >>>> + }; >>>> + >>>> cci0: cci@ac4a000 { >>>> compatible =3D "qcom,sm6350-cci", "qcom,msm8996-cci"; >>>> reg =3D <0 0x0ac4a000 0 0x1000>; >>>> >>>> --=20 >>>> 2.49.0 >>>> >>=20