* [PATCH v3] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree
@ 2025-03-14 18:56 Thomas Bonnefille
2025-03-14 19:01 ` Wolfram Sang
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: Thomas Bonnefille @ 2025-03-14 18:56 UTC (permalink / raw)
To: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: Thomas Petazzoni, Miquèl Raynal, linux-renesas-soc,
devicetree, linux-kernel, Clément Léger,
Thomas Bonnefille
From: Clément Léger <clement.leger@bootlin.com>
The EB board (Expansion board) supports both RZ/N1D and RZ-N1S. Since this
configuration targets only the RZ/N1D, it is named r9a06g032-rzn1d400-eb.
It adds support for the 2 additional switch ports (port C and D) that are
available on that board.
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
[Thomas moved the dts to the renesas directory and declared the leds in
each phy]
Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
---
This short series adds support for the RZ/N1 Expansion Board. This board
is a carrier board on which a daughter board (either RZ/N1D or RZ/N1S)
can be plugged. The device-tree that is added by this series enables the
use to the 2 external switch ports that are present on this board.
---
V3:
- Drop bindings commit as it was applied to master
- Move Makefile modification to arch/arm/boot/dts/renesas/Makefile
- Declare LEDs in PHY.
- Use the driver default LED configuration as there was no reason to
use a different one.
V2:
- Add "renesas,rzn1d400-db" in list of compatibles for EB board
- Replace '_' with '-' in eth pins node name
- Split some long lines in dts
---
arch/arm/boot/dts/renesas/Makefile | 1 +
.../arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts | 120 +++++++++++++++++++++
2 files changed, 121 insertions(+)
diff --git a/arch/arm/boot/dts/renesas/Makefile b/arch/arm/boot/dts/renesas/Makefile
index 833a02447ecf7a02bd2efe70fae15213ede9a6de..947c7fe0280337a3aa6e9a0257f406694892239c 100644
--- a/arch/arm/boot/dts/renesas/Makefile
+++ b/arch/arm/boot/dts/renesas/Makefile
@@ -30,4 +30,5 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
r8a7794-alt.dtb \
r8a7794-silk.dtb \
r9a06g032-rzn1d400-db.dtb \
+ r9a06g032-rzn1d400-eb.dtb \
sh73a0-kzm9g.dtb
diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
new file mode 100644
index 0000000000000000000000000000000000000000..20478941170bade197afb5cc9b3d694bd9a30951
--- /dev/null
+++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Device Tree Source for the RZN1D-EB Board
+ *
+ * Copyright (C) 2023 Schneider-Electric
+ *
+ */
+
+#include "r9a06g032-rzn1d400-db.dts"
+
+/ {
+ model = "RZN1D-EB Board";
+ compatible = "renesas,rzn1d400-eb", "renesas,rzn1d400-db",
+ "renesas,r9a06g032";
+};
+
+&mii_conv2 {
+ renesas,miic-input = <MIIC_SWITCH_PORTD>;
+ status = "okay";
+};
+
+&mii_conv3 {
+ renesas,miic-input = <MIIC_SWITCH_PORTC>;
+ status = "okay";
+};
+
+&pinctrl{
+ pins_eth1: pins-eth1 {
+ pinmux = <RZN1_PINMUX(12, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(13, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(14, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(15, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(16, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(17, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(18, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(19, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(20, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(21, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(22, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(23, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ pins_eth2: pins-eth2 {
+ pinmux = <RZN1_PINMUX(24, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(25, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(26, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(27, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(28, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(29, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(30, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(31, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(32, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(33, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(34, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
+ <RZN1_PINMUX(35, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
+ drive-strength = <6>;
+ bias-disable;
+ };
+};
+
+&switch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pins_eth1>, <&pins_eth2>, <&pins_eth3>, <&pins_eth4>,
+ <&pins_mdio1>;
+
+ mdio {
+ /* CN15 and CN16 switches must be configured in MDIO2 mode */
+ switch0phy1: ethernet-phy@1 {
+ reg = <1>;
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ };
+ led@1 {
+ reg = <1>;
+ };
+ led@2 {
+ reg = <2>;
+ };
+ };
+ };
+
+ switch0phy10: ethernet-phy@10 {
+ reg = <10>;
+ leds {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0>;
+ };
+ led@1 {
+ reg = <1>;
+ };
+ led@2 {
+ reg = <2>;
+ };
+ };
+ };
+ };
+};
+
+&switch_port2 {
+ label = "lan2";
+ phy-mode = "rgmii-id";
+ phy-handle = <&switch0phy10>;
+ status = "okay";
+};
+
+&switch_port3 {
+ label = "lan3";
+ phy-mode = "rgmii-id";
+ phy-handle = <&switch0phy1>;
+ status = "okay";
+};
---
base-commit: 9c5968db9e625019a0ee5226c7eebef5519d366a
change-id: 20250127-rzn1d400-eb-3fc1479a13e6
Best regards,
--
Thomas Bonnefille <thomas.bonnefille@bootlin.com>
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v3] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree
2025-03-14 18:56 [PATCH v3] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree Thomas Bonnefille
@ 2025-03-14 19:01 ` Wolfram Sang
2025-03-17 8:55 ` Thomas Bonnefille
2025-03-19 12:04 ` Wolfram Sang
2025-03-17 8:52 ` Thomas Bonnefille
` (2 subsequent siblings)
3 siblings, 2 replies; 11+ messages in thread
From: Wolfram Sang @ 2025-03-14 19:01 UTC (permalink / raw)
To: Thomas Bonnefille
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thomas Petazzoni, Miquèl Raynal,
linux-renesas-soc, devicetree, linux-kernel,
Clément Léger
[-- Attachment #1: Type: text/plain, Size: 681 bytes --]
On Fri, Mar 14, 2025 at 07:56:29PM +0100, Thomas Bonnefille wrote:
> From: Clément Léger <clement.leger@bootlin.com>
>
> The EB board (Expansion board) supports both RZ/N1D and RZ-N1S. Since this
> configuration targets only the RZ/N1D, it is named r9a06g032-rzn1d400-eb.
> It adds support for the 2 additional switch ports (port C and D) that are
> available on that board.
>
> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
>
> [Thomas moved the dts to the renesas directory and declared the leds in
> each phy]
>
> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Oh, cool! I will definitely test it next week. Thanks a lot!
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree
2025-03-14 18:56 [PATCH v3] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree Thomas Bonnefille
2025-03-14 19:01 ` Wolfram Sang
@ 2025-03-17 8:52 ` Thomas Bonnefille
2025-04-08 6:23 ` Wolfram Sang
2025-03-18 8:38 ` Miquel Raynal
2025-03-24 14:27 ` Wolfram Sang
3 siblings, 1 reply; 11+ messages in thread
From: Thomas Bonnefille @ 2025-03-17 8:52 UTC (permalink / raw)
To: Thomas Bonnefille, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: Thomas Petazzoni, Miquèl Raynal, linux-renesas-soc,
devicetree, linux-kernel, Clément Léger
Hello,
Erratum, there are some trailing whitespaces hiding in this file, it
seems like I had some checkpatch problems.
I'll send a v4 soon.
On Fri Mar 14, 2025 at 7:56 PM CET, Thomas Bonnefille wrote:
> From: Clément Léger <clement.leger@bootlin.com>
>
> The EB board (Expansion board) supports both RZ/N1D and RZ-N1S. Since this
> configuration targets only the RZ/N1D, it is named r9a06g032-rzn1d400-eb.
> It adds support for the 2 additional switch ports (port C and D) that are
> available on that board.
>
> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
>
> [Thomas moved the dts to the renesas directory and declared the leds in
> each phy]
>
> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
> ---
> This short series adds support for the RZ/N1 Expansion Board. This board
> is a carrier board on which a daughter board (either RZ/N1D or RZ/N1S)
> can be plugged. The device-tree that is added by this series enables the
> use to the 2 external switch ports that are present on this board.
> ---
> V3:
> - Drop bindings commit as it was applied to master
> - Move Makefile modification to arch/arm/boot/dts/renesas/Makefile
> - Declare LEDs in PHY.
> - Use the driver default LED configuration as there was no reason to
> use a different one.
>
> V2:
> - Add "renesas,rzn1d400-db" in list of compatibles for EB board
> - Replace '_' with '-' in eth pins node name
> - Split some long lines in dts
> ---
> arch/arm/boot/dts/renesas/Makefile | 1 +
> .../arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts | 120 +++++++++++++++++++++
> 2 files changed, 121 insertions(+)
>
> diff --git a/arch/arm/boot/dts/renesas/Makefile b/arch/arm/boot/dts/renesas/Makefile
> index 833a02447ecf7a02bd2efe70fae15213ede9a6de..947c7fe0280337a3aa6e9a0257f406694892239c 100644
> --- a/arch/arm/boot/dts/renesas/Makefile
> +++ b/arch/arm/boot/dts/renesas/Makefile
> @@ -30,4 +30,5 @@ dtb-$(CONFIG_ARCH_RENESAS) += \
> r8a7794-alt.dtb \
> r8a7794-silk.dtb \
> r9a06g032-rzn1d400-db.dtb \
> + r9a06g032-rzn1d400-eb.dtb \
> sh73a0-kzm9g.dtb
> diff --git a/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
> new file mode 100644
> index 0000000000000000000000000000000000000000..20478941170bade197afb5cc9b3d694bd9a30951
> --- /dev/null
> +++ b/arch/arm/boot/dts/renesas/r9a06g032-rzn1d400-eb.dts
> @@ -0,0 +1,120 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Device Tree Source for the RZN1D-EB Board
> + *
> + * Copyright (C) 2023 Schneider-Electric
> + *
> + */
> +
> +#include "r9a06g032-rzn1d400-db.dts"
> +
> +/ {
> + model = "RZN1D-EB Board";
> + compatible = "renesas,rzn1d400-eb", "renesas,rzn1d400-db",
> + "renesas,r9a06g032";
> +};
> +
> +&mii_conv2 {
> + renesas,miic-input = <MIIC_SWITCH_PORTD>;
> + status = "okay";
> +};
> +
> +&mii_conv3 {
> + renesas,miic-input = <MIIC_SWITCH_PORTC>;
> + status = "okay";
> +};
> +
> +&pinctrl{
> + pins_eth1: pins-eth1 {
> + pinmux = <RZN1_PINMUX(12, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(13, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(14, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(15, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(16, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(17, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(18, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(19, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(20, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(21, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(22, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(23, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
> + drive-strength = <6>;
> + bias-disable;
> + };
> +
> + pins_eth2: pins-eth2 {
> + pinmux = <RZN1_PINMUX(24, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(25, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(26, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(27, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(28, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(29, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(30, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(31, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(32, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(33, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(34, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>,
> + <RZN1_PINMUX(35, RZN1_FUNC_CLK_ETH_MII_RGMII_RMII)>;
> + drive-strength = <6>;
> + bias-disable;
> + };
> +};
> +
> +&switch {
> + pinctrl-names = "default";
> + pinctrl-0 = <&pins_eth1>, <&pins_eth2>, <&pins_eth3>, <&pins_eth4>,
> + <&pins_mdio1>;
> +
> + mdio {
> + /* CN15 and CN16 switches must be configured in MDIO2 mode */
> + switch0phy1: ethernet-phy@1 {
> + reg = <1>;
> + leds {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + led@0 {
> + reg = <0>;
> + };
> + led@1 {
> + reg = <1>;
> + };
> + led@2 {
> + reg = <2>;
> + };
> + };
> + };
> +
> + switch0phy10: ethernet-phy@10 {
> + reg = <10>;
> + leds {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + led@0 {
> + reg = <0>;
> + };
> + led@1 {
> + reg = <1>;
> + };
> + led@2 {
> + reg = <2>;
> + };
> + };
> + };
> + };
> +};
> +
> +&switch_port2 {
> + label = "lan2";
> + phy-mode = "rgmii-id";
> + phy-handle = <&switch0phy10>;
> + status = "okay";
> +};
> +
> +&switch_port3 {
> + label = "lan3";
> + phy-mode = "rgmii-id";
> + phy-handle = <&switch0phy1>;
> + status = "okay";
> +};
>
> ---
> base-commit: 9c5968db9e625019a0ee5226c7eebef5519d366a
> change-id: 20250127-rzn1d400-eb-3fc1479a13e6
>
> Best regards,
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree
2025-03-14 19:01 ` Wolfram Sang
@ 2025-03-17 8:55 ` Thomas Bonnefille
2025-03-19 12:04 ` Wolfram Sang
1 sibling, 0 replies; 11+ messages in thread
From: Thomas Bonnefille @ 2025-03-17 8:55 UTC (permalink / raw)
To: Wolfram Sang
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thomas Petazzoni, Miquèl Raynal,
linux-renesas-soc, devicetree, linux-kernel,
Clément Léger
On Fri Mar 14, 2025 at 8:01 PM CET, Wolfram Sang wrote:
> On Fri, Mar 14, 2025 at 07:56:29PM +0100, Thomas Bonnefille wrote:
>> From: Clément Léger <clement.leger@bootlin.com>
>>
>> The EB board (Expansion board) supports both RZ/N1D and RZ-N1S. Since this
>> configuration targets only the RZ/N1D, it is named r9a06g032-rzn1d400-eb.
>> It adds support for the 2 additional switch ports (port C and D) that are
>> available on that board.
>>
>> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
>>
>> [Thomas moved the dts to the renesas directory and declared the leds in
>> each phy]
>>
>> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
>
> Oh, cool! I will definitely test it next week. Thanks a lot!
Hello, thank you very much, I would be really interested to know if the
LEDS on the ethernet port work on the board, as I didn't have the EB but
a similar product with the same SoC.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree
2025-03-14 18:56 [PATCH v3] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree Thomas Bonnefille
2025-03-14 19:01 ` Wolfram Sang
2025-03-17 8:52 ` Thomas Bonnefille
@ 2025-03-18 8:38 ` Miquel Raynal
2025-03-24 14:27 ` Wolfram Sang
3 siblings, 0 replies; 11+ messages in thread
From: Miquel Raynal @ 2025-03-18 8:38 UTC (permalink / raw)
To: Thomas Bonnefille
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thomas Petazzoni, linux-renesas-soc, devicetree,
linux-kernel, Clément Léger
On 14/03/2025 at 19:56:29 +01, Thomas Bonnefille <thomas.bonnefille@bootlin.com> wrote:
> From: Clément Léger <clement.leger@bootlin.com>
>
> The EB board (Expansion board) supports both RZ/N1D and RZ-N1S. Since this
> configuration targets only the RZ/N1D, it is named r9a06g032-rzn1d400-eb.
> It adds support for the 2 additional switch ports (port C and D) that are
> available on that board.
>
> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
>
> [Thomas moved the dts to the renesas directory and declared the leds in
> each phy]
While you do a new iteration, I'd suggest rewording this to:
Signed-off-by: Clément Léger <clement.leger@bootlin.com>
[Thomas: move the DTS to the Renesas directory, declare the PHY LEDs]
Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Cheers,
Miquèl
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree
2025-03-14 19:01 ` Wolfram Sang
2025-03-17 8:55 ` Thomas Bonnefille
@ 2025-03-19 12:04 ` Wolfram Sang
1 sibling, 0 replies; 11+ messages in thread
From: Wolfram Sang @ 2025-03-19 12:04 UTC (permalink / raw)
To: Thomas Bonnefille, Geert Uytterhoeven, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Thomas Petazzoni,
Miquèl Raynal, linux-renesas-soc, devicetree, linux-kernel,
Clément Léger
[-- Attachment #1: Type: text/plain, Size: 255 bytes --]
> Oh, cool! I will definitely test it next week. Thanks a lot!
The network architecture of this board is a mystery to me. Even before
your patch, I couldn't get network to work. Same with your patch
attached. I will try again next week with some help.
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree
2025-03-14 18:56 [PATCH v3] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree Thomas Bonnefille
` (2 preceding siblings ...)
2025-03-18 8:38 ` Miquel Raynal
@ 2025-03-24 14:27 ` Wolfram Sang
2025-03-24 14:48 ` Thomas Bonnefille
3 siblings, 1 reply; 11+ messages in thread
From: Wolfram Sang @ 2025-03-24 14:27 UTC (permalink / raw)
To: Thomas Bonnefille
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thomas Petazzoni, Miquèl Raynal,
linux-renesas-soc, devicetree, linux-kernel,
Clément Léger
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On Fri, Mar 14, 2025 at 07:56:29PM +0100, Thomas Bonnefille wrote:
> From: Clément Léger <clement.leger@bootlin.com>
>
> The EB board (Expansion board) supports both RZ/N1D and RZ-N1S. Since this
> configuration targets only the RZ/N1D, it is named r9a06g032-rzn1d400-eb.
> It adds support for the 2 additional switch ports (port C and D) that are
> available on that board.
>
> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
>
> [Thomas moved the dts to the renesas directory and declared the leds in
> each phy]
>
> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
Niklas and I made it and could run all 4 ports of the switch. Leds work,
too. So, with the whitespace issue fixed.
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Thank you for picking up this patch again!
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree
2025-03-24 14:27 ` Wolfram Sang
@ 2025-03-24 14:48 ` Thomas Bonnefille
0 siblings, 0 replies; 11+ messages in thread
From: Thomas Bonnefille @ 2025-03-24 14:48 UTC (permalink / raw)
To: Wolfram Sang
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thomas Petazzoni, Miquèl Raynal,
linux-renesas-soc, devicetree, linux-kernel,
Clément Léger
On Mon Mar 24, 2025 at 3:27 PM CET, Wolfram Sang wrote:
> On Fri, Mar 14, 2025 at 07:56:29PM +0100, Thomas Bonnefille wrote:
>> From: Clément Léger <clement.leger@bootlin.com>
>>
>> The EB board (Expansion board) supports both RZ/N1D and RZ-N1S. Since this
>> configuration targets only the RZ/N1D, it is named r9a06g032-rzn1d400-eb.
>> It adds support for the 2 additional switch ports (port C and D) that are
>> available on that board.
>>
>> Signed-off-by: Clément Léger <clement.leger@bootlin.com>
>>
>> [Thomas moved the dts to the renesas directory and declared the leds in
>> each phy]
>>
>> Signed-off-by: Thomas Bonnefille <thomas.bonnefille@bootlin.com>
>
> Niklas and I made it and could run all 4 ports of the switch. Leds work,
> too. So, with the whitespace issue fixed.
>
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> Tested-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
>
> Thank you for picking up this patch again!
Thank you very much for testing it !
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree
2025-03-17 8:52 ` Thomas Bonnefille
@ 2025-04-08 6:23 ` Wolfram Sang
2025-04-08 6:47 ` Geert Uytterhoeven
0 siblings, 1 reply; 11+ messages in thread
From: Wolfram Sang @ 2025-04-08 6:23 UTC (permalink / raw)
To: Thomas Bonnefille
Cc: Geert Uytterhoeven, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Thomas Petazzoni, Miquèl Raynal,
linux-renesas-soc, devicetree, linux-kernel,
Clément Léger
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> I'll send a v4 soon.
Please do with the minor review comments addressed. I have some patches
depending on it. Which means that I am using this DTS regularly now and
it works great.
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree
2025-04-08 6:23 ` Wolfram Sang
@ 2025-04-08 6:47 ` Geert Uytterhoeven
2025-04-08 8:03 ` Wolfram Sang
0 siblings, 1 reply; 11+ messages in thread
From: Geert Uytterhoeven @ 2025-04-08 6:47 UTC (permalink / raw)
To: Wolfram Sang
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Thomas Petazzoni, Miquèl Raynal, linux-renesas-soc,
devicetree, linux-kernel, Clément Léger
Hi Wolfram,
On Tue, 8 Apr 2025 at 08:23, Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> > I'll send a v4 soon.
>
> Please do with the minor review comments addressed. I have some patches
> depending on it. Which means that I am using this DTS regularly now and
> it works great.
v4 was posted on March 24th?
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v3] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree
2025-04-08 6:47 ` Geert Uytterhoeven
@ 2025-04-08 8:03 ` Wolfram Sang
0 siblings, 0 replies; 11+ messages in thread
From: Wolfram Sang @ 2025-04-08 8:03 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Magnus Damm, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Thomas Petazzoni, Miquèl Raynal, linux-renesas-soc,
devicetree, linux-kernel, Clément Léger
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> > Please do with the minor review comments addressed. I have some patches
> > depending on it. Which means that I am using this DTS regularly now and
> > it works great.
>
> v4 was posted on March 24th?
Mea culpa, I overlooked it in the list. I am sorry.
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^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2025-04-08 8:03 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-03-14 18:56 [PATCH v3] ARM: dts: r9a06g032: add r9a06g032-rzn1d400-eb board device-tree Thomas Bonnefille
2025-03-14 19:01 ` Wolfram Sang
2025-03-17 8:55 ` Thomas Bonnefille
2025-03-19 12:04 ` Wolfram Sang
2025-03-17 8:52 ` Thomas Bonnefille
2025-04-08 6:23 ` Wolfram Sang
2025-04-08 6:47 ` Geert Uytterhoeven
2025-04-08 8:03 ` Wolfram Sang
2025-03-18 8:38 ` Miquel Raynal
2025-03-24 14:27 ` Wolfram Sang
2025-03-24 14:48 ` Thomas Bonnefille
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