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Tue, 27 May 2025 08:59:01 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 27 May 2025 16:59:00 +0100 Message-Id: Subject: Re: [PATCH v3 08/12] arm64: dts: qcom: sm4250: add description of soundwire and dmic pins From: "Alexey Klimov" To: "Konrad Dybcio" , "Srinivas Kandagatla" , "Mark Brown" , Cc: "Liam Girdwood" , "Rob Herring" , "Krzysztof Kozlowski" , "Krzysztof Kozlowski" , "Conor Dooley" , "Bjorn Andersson" , "Dmitry Baryshkov" , "Konrad Dybcio" , "Jaroslav Kysela" , "Takashi Iwai" , , , , X-Mailer: aerc 0.20.0 References: <20250522-rb2_audio_v3-v3-0-9eeb08cab9dc@linaro.org> <20250522-rb2_audio_v3-v3-8-9eeb08cab9dc@linaro.org> In-Reply-To: On Thu May 22, 2025 at 7:12 PM BST, Konrad Dybcio wrote: > On 5/22/25 7:40 PM, Alexey Klimov wrote: >> Adds data and clock pins description (their active state) of >> soundwire masters and onboard DMIC. >>=20 >> Cc: Srinivas Kandagatla >> Signed-off-by: Alexey Klimov >> --- >> arch/arm64/boot/dts/qcom/sm4250.dtsi | 62 +++++++++++++++++++++++++++++= +++++++ >> 1 file changed, 62 insertions(+) >>=20 >> diff --git a/arch/arm64/boot/dts/qcom/sm4250.dtsi b/arch/arm64/boot/dts/= qcom/sm4250.dtsi >> index cd8c8e59976e5dc4b48d0e14566cf142895711d5..723391ba9aa21d84ba2dda23= 932c20bd048fbe80 100644 >> --- a/arch/arm64/boot/dts/qcom/sm4250.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm4250.dtsi >> @@ -37,10 +37,36 @@ &cpu7 { >> compatible =3D "qcom,kryo240"; >> }; >> =20 >> +&swr0 { >> + pinctrl-0 =3D <&lpass_tx_swr_active>; >> + pinctrl-names =3D "default"; >> +}; >> + >> +&swr1 { >> + pinctrl-0 =3D <&lpass_rx_swr_active>; >> + pinctrl-names =3D "default"; >> +}; >> + >> &lpass_tlmm { >> compatible =3D "qcom,sm4250-lpass-lpi-pinctrl"; >> gpio-ranges =3D <&lpass_tlmm 0 0 27>; >> =20 >> + lpass_dmic01_active: lpass-dmic01-active-state { >> + clk-pins { >> + pins =3D "gpio6"; >> + function =3D "dmic01_clk"; >> + drive-strength =3D <8>; >> + output-high; >> + }; >> + >> + data-pins { >> + pins =3D "gpio7"; >> + function =3D "dmic01_data"; >> + drive-strength =3D <8>; >> + input-enable; >> + }; > > Other SoCs put these in the common dtsi which seems to be sm4250.dtsi in this case unless I am missing something. Thanks, Alexey