[PATCH v2 0/9] drivers: gpio: and the QIXIS FPGA GPIO controller

[PATCH v2 0/9] drivers: gpio: and the QIXIS FPGA GPIO controller

[Ioana Ciornei]

This patch set adds support for the GPIO controllers on the QIXIS FPGAs
found on some Layerscape boards such as LX2160ARDB and LS1046AQDS. At
the same time it describes the SFP+ cages found on these boards, which
are the users of those GPIO lines.

Before actually adding the GPIO driver, patches #2 and #3 add and
describe a new compatible string - fsl,lx2160ardb-fpga - which would be
used for the QIXIS FPGA found on the LX2160ARDB board. As opposed to the
other compatible strings found in fsl,fpga-qixis-i2c.yaml, the
fsl,lx2160ardb-fpga imposes a unit address for its child devices. This
will be used in the next patches when the gpio controller node will
define its unit address as the address of its underlying register offset
inside the FPGA. This requirement is described in the yaml file and it
only affects the newly added compatible.

Moving on to the GPIO subsystem, patch #4 is extending the gpio-regmap
with the fixed_direction_output bitmap which could be used by user
drivers to transmit directly the fixed direction of all the GPIO lines.

Even though this patch set touches multiple subsytems, each with their
own tree, I submit everything at once so that we can have a clear
picture on the overall intention. The hope is that each subsystem can
pick up the related patches since there is no compile time dependency
between them.

Please note that CHECK_DTBS will fail without the following fixup patch.
https://lore.kernel.org/all/20250912165916.3098215-1-ioana.ciornei@nxp.com/

Changes in v2:
- 1/9: Used the newly added trivial-gpio.yaml file
- 1/9: Removed redundant "bindings" from commit title
- 1/9: Added only one compatible string for the gpio controllers on
  LX2160ARDB since both registers have the same layout.
- 2/9: Enforce a unit address on the child gpios nodes (remove the ?)
- 2/9: Enforce the use of unit addresses by having #address-size and
  #size-cells only for the newly added fsl,lx2160ardb-fpga compatible
- 4/9: Add the fixed_direction_output bitmap to the gpio_regmap_config
- 5/9: Use the newly added .fixed_direction_output bitmap
  representing the fixed direction of the GPIO lines.
- 6/9: Use the same compatible string for both GPIO controller nodes.

Ioana Ciornei (9):
  dt-bindings: gpio: add QIXIS FPGA based GPIO controller
  dt-bindings: fsl,fpga-qixis-i2c: extend support to also cover the
    LX2160ARDB FPGA
  mfd: simple-mfd-i2c: add compatible string for LX2160ARDB
  gpio: regmap: add the .fixed_direction_output configuration parameter
  drivers: gpio: add QIXIS FPGA GPIO controller
  arm64: dts: lx2160a-rdb: describe the QIXIS FPGA and two child GPIO
    controllers
  arm64: dts: ls1046a-qds: describe the FPGA based GPIO controller
  arm64: dts: lx2160a-rdb: fully describe the two SFP+ cages
  arm64: dts: ls1046a-qds: describe the two on-board SFP+ cages

 .../bindings/board/fsl,fpga-qixis-i2c.yaml    |  47 +++++++
 .../bindings/gpio/trivial-gpio.yaml           |   2 +
 .../boot/dts/freescale/fsl-ls1046a-qds.dts    |  52 ++++++++
 .../boot/dts/freescale/fsl-lx2160a-rdb.dts    |  78 +++++++++++
 drivers/gpio/Kconfig                          |   9 ++
 drivers/gpio/Makefile                         |   1 +
 drivers/gpio/gpio-qixis-fpga.c                | 123 ++++++++++++++++++
 drivers/gpio/gpio-regmap.c                    |  12 ++
 drivers/mfd/simple-mfd-i2c.c                  |   1 +
 include/linux/gpio/regmap.h                   |   2 +
 10 files changed, 327 insertions(+)
 create mode 100644 drivers/gpio/gpio-qixis-fpga.c

-- 
2.25.1

[PATCH v2 1/9] dt-bindings: gpio: add QIXIS FPGA based GPIO controller

[Ioana Ciornei]

Add a device tree binding for the QIXIS FPGA based GPIO controller.
Depending on the board, the QIXIS FPGA exposes registers which act as a
GPIO controller, each with 8 GPIO lines of fixed direction.

Since each QIXIS FPGA layout has its particularities, add a separate
compatible string for each board/GPIO register combination supported.

Since these GPIO controllers are trivial, make use of the newly added
trivial-gpio.yaml file instead of creating an entirely new one.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- Used the newly added trivial-gpio.yaml file
- Removed redundant "bindings" from commit title
- Added only one compatible string for the gpio controllers on
  LX2160ARDB since both registers have the same layout.

 Documentation/devicetree/bindings/gpio/trivial-gpio.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml b/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml
index c994177de940..3f4bbd57fc52 100644
--- a/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml
+++ b/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml
@@ -22,6 +22,8 @@ properties:
           - cznic,moxtet-gpio
           - dlg,slg7xl45106
           - fcs,fxl6408
+          - fsl,ls1046aqds-fpga-gpio-stat-pres2
+          - fsl,lx2160ardb-fpga-gpio-sfp
           - gateworks,pld-gpio
           - ibm,ppc4xx-gpio
           - loongson,ls1x-gpio
-- 
2.25.1

[PATCH v2 2/9] dt-bindings: fsl,fpga-qixis-i2c: extend support to also cover the LX2160ARDB FPGA

[Ioana Ciornei]

Extend the list of supported compatible strings with fsl,lx2160ardb-fpga.

Since the register map exposed by the LX2160ARDB's FPGA also contains
two GPIO controllers, accept the necessary GPIO pattern property.
At the same time, add the #address-cells and #size-cells properties as
valid ones so that the child nodes of the fsl,lx2160ardb-fpga node are
addressable.

This is needed because when defining child devices such as the GPIO
controller described in the added example, the child device needs a the
reg property to properly identify its register location.
Impose this restriction for the new compatible through an if-statement.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- Enforce a unit address on the child gpios nodes (remove the ?)
- Enforce the use of unit addresses by having #address-size and
  #size-cells only for the newly added fsl,lx2160ardb-fpga compatible

 .../bindings/board/fsl,fpga-qixis-i2c.yaml    | 47 +++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml b/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
index 28b37772fb65..da21d0defa04 100644
--- a/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
+++ b/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
@@ -22,6 +22,13 @@ properties:
               - fsl,lx2160aqds-fpga
           - const: fsl,fpga-qixis-i2c
           - const: simple-mfd
+      - const: fsl,lx2160ardb-fpga
+
+  "#address-cells":
+    const: 1
+
+  "#size-cells":
+    const: 0
 
   interrupts:
     maxItems: 1
@@ -32,10 +39,26 @@ properties:
   mux-controller:
     $ref: /schemas/mux/reg-mux.yaml
 
+patternProperties:
+  "^gpio@[0-9a-f]+$":
+    $ref: /schemas/gpio/trivial-gpio.yaml
+
 required:
   - compatible
   - reg
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - fsl,lx2160ardb-fpga
+    then:
+      required:
+        - "#address-cells"
+        - "#size-cells"
+
 additionalProperties: false
 
 examples:
@@ -68,3 +91,27 @@ examples:
         };
     };
 
+  - |
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        board-control@66 {
+            compatible = "fsl,lx2160ardb-fpga";
+            reg = <0x66>;
+            #address-cells = <1>;
+            #size-cells = <0>;
+
+            gpio@19 {
+                compatible = "fsl,lx2160ardb-fpga-gpio-sfp";
+                reg = <0x19>;
+                gpio-controller;
+                #gpio-cells = <2>;
+                gpio-line-names =
+                    "SFP2_TX_EN", "",
+                    "", "",
+                    "SFP2_RX_LOS", "SFP2_TX_FAULT",
+                    "", "SFP2_MOD_ABS";
+            };
+        };
+    };
-- 
2.25.1

[PATCH v2 3/9] mfd: simple-mfd-i2c: add compatible string for LX2160ARDB

[Ioana Ciornei]

Extend the list of supported devices with the QIXIS FPGA found on the
LX2160ARDB board.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- none

 drivers/mfd/simple-mfd-i2c.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mfd/simple-mfd-i2c.c b/drivers/mfd/simple-mfd-i2c.c
index 63ac26388860..6fbe85437d8d 100644
--- a/drivers/mfd/simple-mfd-i2c.c
+++ b/drivers/mfd/simple-mfd-i2c.c
@@ -115,6 +115,7 @@ static const struct of_device_id simple_mfd_i2c_of_match[] = {
 	{ .compatible = "maxim,max5970", .data = &maxim_max5970},
 	{ .compatible = "maxim,max5978", .data = &maxim_max5970},
 	{ .compatible = "maxim,max77705-battery", .data = &maxim_mon_max77705},
+	{ .compatible = "fsl,lx2160ardb-fpga" },
 	{ .compatible = "fsl,lx2160aqds-fpga" },
 	{ .compatible = "fsl,ls1028aqds-fpga" },
 	{ .compatible = "spacemit,p1", .data = &spacemit_p1, },
-- 
2.25.1

[PATCH v2 4/9] gpio: regmap: add the .fixed_direction_output configuration parameter

[Ioana Ciornei]

There are GPIO controllers such as the one present in the LX2160ARDB
QIXIS FPGA which have fixed-direction input and output GPIO lines mixed
together in a single register. This cannot be modeled using the
gpio-regmap as-is since there is no way to present the true direction of
a GPIO line.

In order to make this use case possible, add a new configuration
parameter - fixed_direction_output - into the gpio_regmap_config
structure. This will enable user drivers to provide a bitmap that
represents the fixed direction of the GPIO lines.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- Add the fixed_direction_output bitmap to the gpio_regmap_config

 drivers/gpio/gpio-regmap.c  | 12 ++++++++++++
 include/linux/gpio/regmap.h |  2 ++
 2 files changed, 14 insertions(+)

diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c
index e8a32dfebdcb..2489768686d3 100644
--- a/drivers/gpio/gpio-regmap.c
+++ b/drivers/gpio/gpio-regmap.c
@@ -31,6 +31,7 @@ struct gpio_regmap {
 	unsigned int reg_clr_base;
 	unsigned int reg_dir_in_base;
 	unsigned int reg_dir_out_base;
+	unsigned long *fixed_direction_output;
 
 	int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base,
 			      unsigned int offset, unsigned int *reg,
@@ -129,6 +130,16 @@ static int gpio_regmap_get_direction(struct gpio_chip *chip,
 	unsigned int base, val, reg, mask;
 	int invert, ret;
 
+	if (offset >= chip->ngpio)
+		return -EINVAL;
+
+	if (gpio->fixed_direction_output) {
+		if (test_bit(offset, gpio->fixed_direction_output))
+			return GPIO_LINE_DIRECTION_OUT;
+		else
+			return GPIO_LINE_DIRECTION_IN;
+	}
+
 	if (gpio->reg_dat_base && !gpio->reg_set_base)
 		return GPIO_LINE_DIRECTION_IN;
 	if (gpio->reg_set_base && !gpio->reg_dat_base)
@@ -247,6 +258,7 @@ struct gpio_regmap *gpio_regmap_register(const struct gpio_regmap_config *config
 	gpio->reg_clr_base = config->reg_clr_base;
 	gpio->reg_dir_in_base = config->reg_dir_in_base;
 	gpio->reg_dir_out_base = config->reg_dir_out_base;
+	gpio->fixed_direction_output = config->fixed_direction_output;
 
 	chip = &gpio->gpio_chip;
 	chip->parent = config->parent;
diff --git a/include/linux/gpio/regmap.h b/include/linux/gpio/regmap.h
index c722c67668c6..34c143aca42d 100644
--- a/include/linux/gpio/regmap.h
+++ b/include/linux/gpio/regmap.h
@@ -78,6 +78,8 @@ struct gpio_regmap_config {
 	int ngpio_per_reg;
 	struct irq_domain *irq_domain;
 
+	unsigned long *fixed_direction_output;
+
 	int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base,
 			      unsigned int offset, unsigned int *reg,
 			      unsigned int *mask);
-- 
2.25.1

[PATCH v2 5/9] drivers: gpio: add QIXIS FPGA GPIO controller

[Ioana Ciornei]

Add support for the GPIO controller found on some QIXIS FPGAs in
Layerscape boards such as LX2160ARDB and LS1046AQDS. This driver is
using gpio-regmap.

A GPIO controller has a maximum of 8 lines (all found in the same
register). Even within the same controller, the GPIO lines' direction is
fixed, which mean that both input and output lines are found in the same
register. This is why the driver also passed to gpio-regmap the newly
added .fixed_direction_output bitmap to represent the true direction of
the lines.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- Use the newly added .fixed_direction_output bitmap representing
  the fixed direction of the GPIO lines.

 drivers/gpio/Kconfig           |   9 +++
 drivers/gpio/Makefile          |   1 +
 drivers/gpio/gpio-qixis-fpga.c | 123 +++++++++++++++++++++++++++++++++
 3 files changed, 133 insertions(+)
 create mode 100644 drivers/gpio/gpio-qixis-fpga.c

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 886bef9106da..4ca5890007ff 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -1951,6 +1951,15 @@ config GPIO_LATCH
 	  Say yes here to enable a driver for GPIO multiplexers based on latches
 	  connected to other GPIOs.
 
+config GPIO_QIXIS_FPGA
+	tristate "NXP QIXIS FPGA GPIO support"
+	depends on MFD_SIMPLE_MFD_I2C || COMPILE_TEST
+	select GPIO_REGMAP
+	help
+	  This enables support for the GPIOs found in the QIXIS FPGA which is
+	  integrated on some NXP Layerscape boards such as LX2160ARDB and
+	  LS1046AQDS.
+
 config GPIO_MOCKUP
 	tristate "GPIO Testing Driver (DEPRECATED)"
 	select IRQ_SIM
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 379f55e9ed1e..373b1f169558 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -144,6 +144,7 @@ obj-$(CONFIG_GPIO_PL061)		+= gpio-pl061.o
 obj-$(CONFIG_GPIO_PMIC_EIC_SPRD)	+= gpio-pmic-eic-sprd.o
 obj-$(CONFIG_GPIO_POLARFIRE_SOC)	+= gpio-mpfs.o
 obj-$(CONFIG_GPIO_PXA)			+= gpio-pxa.o
+obj-$(CONFIG_GPIO_QIXIS_FPGA)		+= gpio-qixis-fpga.o
 obj-$(CONFIG_GPIO_RASPBERRYPI_EXP)	+= gpio-raspberrypi-exp.o
 obj-$(CONFIG_GPIO_RC5T583)		+= gpio-rc5t583.o
 obj-$(CONFIG_GPIO_RCAR)			+= gpio-rcar.o
diff --git a/drivers/gpio/gpio-qixis-fpga.c b/drivers/gpio/gpio-qixis-fpga.c
new file mode 100644
index 000000000000..23219a634f73
--- /dev/null
+++ b/drivers/gpio/gpio-qixis-fpga.c
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Layerscape GPIO QIXIS FPGA driver
+ *
+ * Copyright 2025 NXP
+ */
+
+#include <linux/device.h>
+#include <linux/gpio/driver.h>
+#include <linux/gpio/regmap.h>
+#include <linux/kernel.h>
+#include <linux/mod_devicetable.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+
+enum qixis_cpld_gpio_type {
+	LX2160ARDB_GPIO_SFP = 0,
+	LS1046AQDS_GPIO_STAT_PRES2,
+};
+
+struct qixis_cpld_gpio_config {
+	enum qixis_cpld_gpio_type type;
+	u64 output_lines;
+};
+
+static struct qixis_cpld_gpio_config lx2160ardb_sfp_cfg = {
+	.type = LX2160ARDB_GPIO_SFP,
+	.output_lines = BIT(0),
+};
+
+static struct qixis_cpld_gpio_config ls1046aqds_stat_pres2_cfg = {
+	.type = LS1046AQDS_GPIO_STAT_PRES2,
+	.output_lines = 0x0,
+};
+
+static const struct regmap_config regmap_config_8r_8v = {
+	.reg_bits = 8,
+	.val_bits = 8,
+};
+
+static int qixis_cpld_gpio_probe(struct platform_device *pdev)
+{
+	const struct qixis_cpld_gpio_config *cfg;
+	struct gpio_regmap_config config = {0};
+	struct regmap *regmap;
+	void __iomem *reg;
+	u32 base;
+	int ret;
+
+	if (!pdev->dev.parent)
+		return -ENODEV;
+
+	cfg = device_get_match_data(&pdev->dev);
+	if (!cfg)
+		return -ENODEV;
+
+	ret = device_property_read_u32(&pdev->dev, "reg", &base);
+	if (ret)
+		return ret;
+
+	regmap = dev_get_regmap(pdev->dev.parent, NULL);
+	if (!regmap) {
+		/* In case there is no regmap configured by the parent device,
+		 * create our own.
+		 */
+		reg = devm_platform_ioremap_resource(pdev, 0);
+		if (!reg)
+			return -ENODEV;
+
+		regmap = devm_regmap_init_mmio(&pdev->dev, reg, &regmap_config_8r_8v);
+		if (!regmap)
+			return -ENODEV;
+
+		/* In this case, the offset of our register is 0 inside the
+		 * regmap area that we just created.
+		 */
+		base = 0;
+	}
+
+	config.drvdata = (void *)cfg;
+	config.regmap = regmap;
+	config.parent = &pdev->dev;
+	config.ngpio_per_reg = 8;
+	config.ngpio = 8;
+	config.fixed_direction_output = bitmap_alloc(8, GFP_KERNEL);
+	if (!config.fixed_direction_output)
+		return -ENOMEM;
+	bitmap_from_u64(config.fixed_direction_output, cfg->output_lines);
+
+	switch (cfg->type) {
+	case LX2160ARDB_GPIO_SFP:
+	case LS1046AQDS_GPIO_STAT_PRES2:
+		config.reg_dat_base = GPIO_REGMAP_ADDR(base);
+		config.reg_set_base = GPIO_REGMAP_ADDR(base);
+		break;
+	}
+
+	return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(&pdev->dev, &config));
+}
+
+static const struct of_device_id qixis_cpld_gpio_of_match[] = {
+	{
+		.compatible = "fsl,lx2160ardb-fpga-gpio-sfp",
+		.data = &lx2160ardb_sfp_cfg,
+	},
+	{
+		.compatible = "fsl,ls1046aqds-fpga-gpio-stat-pres2",
+		.data = &ls1046aqds_stat_pres2_cfg,
+	},
+
+	{}
+};
+MODULE_DEVICE_TABLE(of, qixis_cpld_gpio_of_match);
+
+static struct platform_driver qixis_cpld_gpio_driver = {
+	.probe = qixis_cpld_gpio_probe,
+	.driver = {
+		.name = "gpio-qixis-cpld",
+		.of_match_table = qixis_cpld_gpio_of_match,
+	},
+};
+module_platform_driver(qixis_cpld_gpio_driver);
-- 
2.25.1

[PATCH v2 6/9] arm64: dts: lx2160a-rdb: describe the QIXIS FPGA and two child GPIO controllers

[Ioana Ciornei]

Describe the FPGA present on the LX2160ARDB board as a simple-mfd I2C
device. The FPGA presents registers that deal with power-on-reset
timing, muxing, SFP cage monitoring and control etc.

Also add the two GPIO controllers responsible for monitoring and
controlling the SFP+ cages used for MAC5 and MAC6.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- Use the same compatible string for both GPIO controller nodes.

 .../boot/dts/freescale/fsl-lx2160a-rdb.dts    | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 0c44b3cbef77..4ede1295f29d 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -170,6 +170,37 @@ mt35xu512aba1: flash@1 {
 &i2c0 {
 	status = "okay";
 
+	cpld@66 {
+		compatible = "fsl,lx2160ardb-fpga";
+		reg = <0x66>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		sfp2_csr: gpio@19 {
+			compatible = "fsl,lx2160ardb-fpga-gpio-sfp";
+			reg = <0x19>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-line-names =
+				"SFP2_TX_EN", "",
+				"", "",
+				"SFP2_RX_LOS", "SFP2_TX_FAULT",
+				"", "SFP2_MOD_ABS";
+		};
+
+		sfp3_csr: gpio@1a {
+			compatible = "fsl,lx2160ardb-fpga-gpio-sfp";
+			reg = <0x1a>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-line-names =
+				"SFP3_TX_EN", "",
+				"", "",
+				"SFP3_RX_LOS", "SFP3_TX_FAULT",
+				"", "SFP3_MOD_ABS";
+		};
+	};
+
 	i2c-mux@77 {
 		compatible = "nxp,pca9547";
 		reg = <0x77>;
-- 
2.25.1

[PATCH v2 7/9] arm64: dts: ls1046a-qds: describe the FPGA based GPIO controller

[Ioana Ciornei]

The QIXIS FPGA node is extended so that it describes the GPIO controller
responsible for all the status presence lines on both SFP+ cages as well
as the IO SLOTs present on the board.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- none

 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
index 736722b58e77..64133e63da96 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
@@ -166,8 +166,20 @@ nand@1,0 {
 
 	fpga: board-control@2,0 {
 		compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-mfd";
+		#address-cells = <1>;
+		#size-cells = <1>;
 		reg = <0x2 0x0 0x0000100>;
 		ranges = <0 2 0 0x100>;
+
+		stat_pres2: gpio-stat-pres2@c {
+			compatible = "fsl,ls1046aqds-fpga-gpio-stat-pres2";
+			reg = <0xc 1>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			gpio-line-names =
+				"SLOT1", "SLOT2", "SLOT3", "SLOT4", "SLOT5", "SLOT6",
+				"SFP1_MOD_DEF", "SFP2_MOD_DEF";
+		};
 	};
 };
 
-- 
2.25.1

[PATCH v2 8/9] arm64: dts: lx2160a-rdb: fully describe the two SFP+ cages

[Ioana Ciornei]

Describe the two SFP+ cages found on the LX2160ARDB board with their
respective I2C buses and GPIO lines.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- none

 .../boot/dts/freescale/fsl-lx2160a-rdb.dts    | 47 +++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
index 4ede1295f29d..62329a93a67a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
@@ -31,6 +31,28 @@ sb_3v3: regulator-sb3v3 {
 		regulator-boot-on;
 		regulator-always-on;
 	};
+
+	sfp2: sfp-2 {
+		compatible = "sff,sfp";
+		i2c-bus = <&sfp2_i2c>;
+		maximum-power-milliwatt = <2000>;
+		/* Leave commented out if using DPMAC_LINK_TYPE_FIXED mode */
+		/* tx-disable-gpios = <&sfp2_csr 0 GPIO_ACTIVE_HIGH>; */
+		los-gpios = <&sfp2_csr 4 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpios = <&sfp2_csr 5 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sfp2_csr 7 GPIO_ACTIVE_LOW>;
+	};
+
+	sfp3: sfp-3 {
+		compatible = "sff,sfp";
+		i2c-bus = <&sfp3_i2c>;
+		maximum-power-milliwatt = <2000>;
+		/* Leave commented out if using DPMAC_LINK_TYPE_FIXED mode */
+		/* tx-disable-gpios = <&sfp3_csr 0 GPIO_ACTIVE_HIGH>; */
+		los-gpios = <&sfp3_csr 4 GPIO_ACTIVE_HIGH>;
+		tx-fault-gpios = <&sfp3_csr 5 GPIO_ACTIVE_HIGH>;
+		mod-def0-gpios = <&sfp3_csr 7 GPIO_ACTIVE_LOW>;
+	};
 };
 
 &crypto {
@@ -236,6 +258,31 @@ temperature-sensor@4d {
 				vcc-supply = <&sb_3v3>;
 			};
 		};
+
+		i2c@7 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x7>;
+
+			i2c-mux@75 {
+				compatible = "nxp,pca9547";
+				reg = <0x75>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				sfp2_i2c: i2c@4 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x4>;
+				};
+
+				sfp3_i2c: i2c@5 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x5>;
+				};
+			};
+		};
 	};
 };
 
-- 
2.25.1

[PATCH v2 9/9] arm64: dts: ls1046a-qds: describe the two on-board SFP+ cages

[Ioana Ciornei]

Describe the two SFP+ cages present on the LS1046AQDS board and their
associated I2C buses and GPIO lines.

Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
---
Changes in v2:
- none

 .../boot/dts/freescale/fsl-ls1046a-qds.dts    | 40 +++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
index 64133e63da96..c188977a901e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
@@ -42,6 +42,21 @@ aliases {
 	chosen {
 		stdout-path = "serial0:115200n8";
 	};
+
+	sfp1: sfp-1 {
+		compatible = "sff,sfp";
+		i2c-bus = <&sfp1_i2c>;
+		maximum-power-milliwatt = <2000>;
+		mod-def0-gpios = <&stat_pres2 6 GPIO_ACTIVE_LOW>;
+	};
+
+	sfp2: sfp-2 {
+		compatible = "sff,sfp";
+		i2c-bus = <&sfp2_i2c>;
+		maximum-power-milliwatt = <2000>;
+		mod-def0-gpios = <&stat_pres2 7 GPIO_ACTIVE_LOW>;
+	};
+
 };
 
 &dspi {
@@ -139,6 +154,31 @@ temp-sensor@4c {
 				reg = <0x4c>;
 			};
 		};
+
+		i2c@7 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x7>;
+
+			i2c-mux@76 {
+				compatible = "nxp,pca9547";
+				reg = <0x76>;
+				#address-cells = <1>;
+				#size-cells = <0>;
+
+				sfp1_i2c: i2c@6 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x6>;
+				};
+
+				sfp2_i2c: i2c@7 {
+					#address-cells = <1>;
+					#size-cells = <0>;
+					reg = <0x7>;
+				};
+			};
+		};
 	};
 };
 
-- 
2.25.1

Re: [PATCH v2 4/9] gpio: regmap: add the .fixed_direction_output configuration parameter

[Michael Walle]

[-- Attachment #1: Type: text/plain, Size: 3505 bytes --]

Hi Ioana,

On Mon Sep 15, 2025 at 2:23 PM CEST, Ioana Ciornei wrote:
> There are GPIO controllers such as the one present in the LX2160ARDB
> QIXIS FPGA which have fixed-direction input and output GPIO lines mixed
> together in a single register. This cannot be modeled using the
> gpio-regmap as-is since there is no way to present the true direction of
> a GPIO line.
>
> In order to make this use case possible, add a new configuration
> parameter - fixed_direction_output - into the gpio_regmap_config
> structure. This will enable user drivers to provide a bitmap that
> represents the fixed direction of the GPIO lines.

I wonder about the ownership of that allocated memory in the config
structure (and btw, I guess you leak the memory in your driver) and
if it's not better and more error proof to allocate and copy the
bitmap in gpio-regmap too (and maybe use devm_bitmap_alloc()) and
leave it to the caller to handle the passed bitmap. I.e. it could
also be on the stack.

Otherwise, this looks good.

> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> ---
> Changes in v2:
> - Add the fixed_direction_output bitmap to the gpio_regmap_config
>
>  drivers/gpio/gpio-regmap.c  | 12 ++++++++++++
>  include/linux/gpio/regmap.h |  2 ++
>  2 files changed, 14 insertions(+)
>
> diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c
> index e8a32dfebdcb..2489768686d3 100644
> --- a/drivers/gpio/gpio-regmap.c
> +++ b/drivers/gpio/gpio-regmap.c
> @@ -31,6 +31,7 @@ struct gpio_regmap {
>  	unsigned int reg_clr_base;
>  	unsigned int reg_dir_in_base;
>  	unsigned int reg_dir_out_base;
> +	unsigned long *fixed_direction_output;
>  
>  	int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base,
>  			      unsigned int offset, unsigned int *reg,
> @@ -129,6 +130,16 @@ static int gpio_regmap_get_direction(struct gpio_chip *chip,
>  	unsigned int base, val, reg, mask;
>  	int invert, ret;
>  
> +	if (offset >= chip->ngpio)
> +		return -EINVAL;

Not sure this can happen. I tried to look into gpiolib.c but
couldn't find anything obvious that it can't happen. Maybe Linus or
Bartosz can comment on that.

> +
> +	if (gpio->fixed_direction_output) {
> +		if (test_bit(offset, gpio->fixed_direction_output))
> +			return GPIO_LINE_DIRECTION_OUT;
> +		else
> +			return GPIO_LINE_DIRECTION_IN;
> +	}
> +
>  	if (gpio->reg_dat_base && !gpio->reg_set_base)
>  		return GPIO_LINE_DIRECTION_IN;
>  	if (gpio->reg_set_base && !gpio->reg_dat_base)
> @@ -247,6 +258,7 @@ struct gpio_regmap *gpio_regmap_register(const struct gpio_regmap_config *config
>  	gpio->reg_clr_base = config->reg_clr_base;
>  	gpio->reg_dir_in_base = config->reg_dir_in_base;
>  	gpio->reg_dir_out_base = config->reg_dir_out_base;
> +	gpio->fixed_direction_output = config->fixed_direction_output;
>  
>  	chip = &gpio->gpio_chip;
>  	chip->parent = config->parent;
> diff --git a/include/linux/gpio/regmap.h b/include/linux/gpio/regmap.h
> index c722c67668c6..34c143aca42d 100644
> --- a/include/linux/gpio/regmap.h
> +++ b/include/linux/gpio/regmap.h
> @@ -78,6 +78,8 @@ struct gpio_regmap_config {
>  	int ngpio_per_reg;
>  	struct irq_domain *irq_domain;
>  
> +	unsigned long *fixed_direction_output;

Please add some documentation.

-michael

> +
>  	int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base,
>  			      unsigned int offset, unsigned int *reg,
>  			      unsigned int *mask);


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Re: [PATCH v2 4/9] gpio: regmap: add the .fixed_direction_output configuration parameter

[Ioana Ciornei]

On Mon, Sep 15, 2025 at 02:45:58PM +0200, Michael Walle wrote:
> Hi Ioana,
> 
> On Mon Sep 15, 2025 at 2:23 PM CEST, Ioana Ciornei wrote:
> > There are GPIO controllers such as the one present in the LX2160ARDB
> > QIXIS FPGA which have fixed-direction input and output GPIO lines mixed
> > together in a single register. This cannot be modeled using the
> > gpio-regmap as-is since there is no way to present the true direction of
> > a GPIO line.
> >
> > In order to make this use case possible, add a new configuration
> > parameter - fixed_direction_output - into the gpio_regmap_config
> > structure. This will enable user drivers to provide a bitmap that
> > represents the fixed direction of the GPIO lines.
> 
> I wonder about the ownership of that allocated memory in the config
> structure (and btw, I guess you leak the memory in your driver)

Yes, I missed that memory leak. Sorry.

> and
> if it's not better and more error proof to allocate and copy the
> bitmap in gpio-regmap too (and maybe use devm_bitmap_alloc()) and
> leave it to the caller to handle the passed bitmap. I.e. it could
> also be on the stack.

So you are suggesting gpio-regmap to allocate the bitmap using
devm_bitmap_alloc() and base its size on config->ngpio, then copy into
it the bitmap passed by the caller, right?  Yes, that does seem more
error proof in terms of memory handling. Will change it in the next
version.

> 
> Otherwise, this looks good.
> 
> > Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> > ---
> > Changes in v2:
> > - Add the fixed_direction_output bitmap to the gpio_regmap_config
> >
> >  drivers/gpio/gpio-regmap.c  | 12 ++++++++++++
> >  include/linux/gpio/regmap.h |  2 ++
> >  2 files changed, 14 insertions(+)
> >
> > diff --git a/drivers/gpio/gpio-regmap.c b/drivers/gpio/gpio-regmap.c
> > index e8a32dfebdcb..2489768686d3 100644
> > --- a/drivers/gpio/gpio-regmap.c
> > +++ b/drivers/gpio/gpio-regmap.c
> > @@ -31,6 +31,7 @@ struct gpio_regmap {
> >  	unsigned int reg_clr_base;
> >  	unsigned int reg_dir_in_base;
> >  	unsigned int reg_dir_out_base;
> > +	unsigned long *fixed_direction_output;
> >  
> >  	int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base,
> >  			      unsigned int offset, unsigned int *reg,
> > @@ -129,6 +130,16 @@ static int gpio_regmap_get_direction(struct gpio_chip *chip,
> >  	unsigned int base, val, reg, mask;
> >  	int invert, ret;
> >  
> > +	if (offset >= chip->ngpio)
> > +		return -EINVAL;
> 
> Not sure this can happen. I tried to look into gpiolib.c but
> couldn't find anything obvious that it can't happen. Maybe Linus or
> Bartosz can comment on that.
> 
> > +
> > +	if (gpio->fixed_direction_output) {
> > +		if (test_bit(offset, gpio->fixed_direction_output))
> > +			return GPIO_LINE_DIRECTION_OUT;
> > +		else
> > +			return GPIO_LINE_DIRECTION_IN;
> > +	}
> > +
> >  	if (gpio->reg_dat_base && !gpio->reg_set_base)
> >  		return GPIO_LINE_DIRECTION_IN;
> >  	if (gpio->reg_set_base && !gpio->reg_dat_base)
> > @@ -247,6 +258,7 @@ struct gpio_regmap *gpio_regmap_register(const struct gpio_regmap_config *config
> >  	gpio->reg_clr_base = config->reg_clr_base;
> >  	gpio->reg_dir_in_base = config->reg_dir_in_base;
> >  	gpio->reg_dir_out_base = config->reg_dir_out_base;
> > +	gpio->fixed_direction_output = config->fixed_direction_output;
> >  
> >  	chip = &gpio->gpio_chip;
> >  	chip->parent = config->parent;
> > diff --git a/include/linux/gpio/regmap.h b/include/linux/gpio/regmap.h
> > index c722c67668c6..34c143aca42d 100644
> > --- a/include/linux/gpio/regmap.h
> > +++ b/include/linux/gpio/regmap.h
> > @@ -78,6 +78,8 @@ struct gpio_regmap_config {
> >  	int ngpio_per_reg;
> >  	struct irq_domain *irq_domain;
> >  
> > +	unsigned long *fixed_direction_output;
> 
> Please add some documentation.

Ok, sure.

Ioana

Re: [PATCH v2 4/9] gpio: regmap: add the .fixed_direction_output configuration parameter

[Michael Walle]

[-- Attachment #1: Type: text/plain, Size: 336 bytes --]

Hi Ioana,

> So you are suggesting gpio-regmap to allocate the bitmap using
> devm_bitmap_alloc() and base its size on config->ngpio, then copy into
> it the bitmap passed by the caller, right?  Yes, that does seem more
> error proof in terms of memory handling. Will change it in the next
> version.

Yes exactly.

-michael

[-- Attachment #2: signature.asc --]
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Re: [PATCH v2 2/9] dt-bindings: fsl,fpga-qixis-i2c: extend support to also cover the LX2160ARDB FPGA

[Rob Herring (Arm)]

On Mon, 15 Sep 2025 15:23:47 +0300, Ioana Ciornei wrote:
> Extend the list of supported compatible strings with fsl,lx2160ardb-fpga.
> 
> Since the register map exposed by the LX2160ARDB's FPGA also contains
> two GPIO controllers, accept the necessary GPIO pattern property.
> At the same time, add the #address-cells and #size-cells properties as
> valid ones so that the child nodes of the fsl,lx2160ardb-fpga node are
> addressable.
> 
> This is needed because when defining child devices such as the GPIO
> controller described in the added example, the child device needs a the
> reg property to properly identify its register location.
> Impose this restriction for the new compatible through an if-statement.
> 
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> ---
> Changes in v2:
> - Enforce a unit address on the child gpios nodes (remove the ?)
> - Enforce the use of unit addresses by having #address-size and
>   #size-cells only for the newly added fsl,lx2160ardb-fpga compatible
> 
>  .../bindings/board/fsl,fpga-qixis-i2c.yaml    | 47 +++++++++++++++++++
>  1 file changed, 47 insertions(+)
> 

My bot found errors running 'make dt_binding_check' on your patch:

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.example.dtb: board-control@66 (fsl,lx2160ardb-fpga): gpio@19: {'compatible': ['fsl,lx2160ardb-fpga-gpio-sfp'], 'reg': [[25]], 'gpio-controller': True, '#gpio-cells': 2, 'gpio-line-names': ['SFP2_TX_EN', '', '', '', 'SFP2_RX_LOS', 'SFP2_TX_FAULT', '', 'SFP2_MOD_ABS']} should not be valid under {'description': "Can't find referenced schema: http://devicetree.org/schemas/gpio/trivial-gpio.yaml#"}
	from schema $id: http://devicetree.org/schemas/board/fsl,fpga-qixis-i2c.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20250915122354.217720-3-ioana.ciornei@nxp.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH v2 2/9] dt-bindings: fsl,fpga-qixis-i2c: extend support to also cover the LX2160ARDB FPGA

[Rob Herring]

On Mon, Sep 15, 2025 at 03:23:47PM +0300, Ioana Ciornei wrote:
> Extend the list of supported compatible strings with fsl,lx2160ardb-fpga.
> 
> Since the register map exposed by the LX2160ARDB's FPGA also contains
> two GPIO controllers, accept the necessary GPIO pattern property.
> At the same time, add the #address-cells and #size-cells properties as
> valid ones so that the child nodes of the fsl,lx2160ardb-fpga node are
> addressable.
> 
> This is needed because when defining child devices such as the GPIO
> controller described in the added example, the child device needs a the
> reg property to properly identify its register location.
> Impose this restriction for the new compatible through an if-statement.
> 
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> ---
> Changes in v2:
> - Enforce a unit address on the child gpios nodes (remove the ?)
> - Enforce the use of unit addresses by having #address-size and
>   #size-cells only for the newly added fsl,lx2160ardb-fpga compatible
> 
>  .../bindings/board/fsl,fpga-qixis-i2c.yaml    | 47 +++++++++++++++++++
>  1 file changed, 47 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml b/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
> index 28b37772fb65..da21d0defa04 100644
> --- a/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
> +++ b/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
> @@ -22,6 +22,13 @@ properties:
>                - fsl,lx2160aqds-fpga
>            - const: fsl,fpga-qixis-i2c
>            - const: simple-mfd
> +      - const: fsl,lx2160ardb-fpga
> +
> +  "#address-cells":
> +    const: 1
> +
> +  "#size-cells":
> +    const: 0
>  
>    interrupts:
>      maxItems: 1
> @@ -32,10 +39,26 @@ properties:
>    mux-controller:
>      $ref: /schemas/mux/reg-mux.yaml
>  
> +patternProperties:
> +  "^gpio@[0-9a-f]+$":
> +    $ref: /schemas/gpio/trivial-gpio.yaml

This results in this schema being applied twice and more 
importantly allows any compatible listed in it to be allowed here. So I 
would drop the $ref and do this instead:

       additionalProperties: true

       properties:
         compatible:
           contains:
             enum:
               - fsl,lx2160ardb-fpga-gpio-sfp
               ...


> +
>  required:
>    - compatible
>    - reg
>  
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - fsl,lx2160ardb-fpga
> +    then:
> +      required:
> +        - "#address-cells"
> +        - "#size-cells"
> +
>  additionalProperties: false
>  
>  examples:
> @@ -68,3 +91,27 @@ examples:
>          };
>      };
>  
> +  - |
> +    i2c {
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +
> +        board-control@66 {
> +            compatible = "fsl,lx2160ardb-fpga";
> +            reg = <0x66>;
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            gpio@19 {
> +                compatible = "fsl,lx2160ardb-fpga-gpio-sfp";
> +                reg = <0x19>;
> +                gpio-controller;
> +                #gpio-cells = <2>;
> +                gpio-line-names =
> +                    "SFP2_TX_EN", "",
> +                    "", "",
> +                    "SFP2_RX_LOS", "SFP2_TX_FAULT",
> +                    "", "SFP2_MOD_ABS";
> +            };
> +        };
> +    };
> -- 
> 2.25.1
> 

Re: [PATCH v2 1/9] dt-bindings: gpio: add QIXIS FPGA based GPIO controller

[Rob Herring]

On Mon, Sep 15, 2025 at 03:23:46PM +0300, Ioana Ciornei wrote:
> Add a device tree binding for the QIXIS FPGA based GPIO controller.
> Depending on the board, the QIXIS FPGA exposes registers which act as a
> GPIO controller, each with 8 GPIO lines of fixed direction.
> 
> Since each QIXIS FPGA layout has its particularities, add a separate
> compatible string for each board/GPIO register combination supported.
> 
> Since these GPIO controllers are trivial, make use of the newly added
> trivial-gpio.yaml file instead of creating an entirely new one.
> 
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> ---
> Changes in v2:
> - Used the newly added trivial-gpio.yaml file
> - Removed redundant "bindings" from commit title
> - Added only one compatible string for the gpio controllers on
>   LX2160ARDB since both registers have the same layout.
> 
>  Documentation/devicetree/bindings/gpio/trivial-gpio.yaml | 2 ++
>  1 file changed, 2 insertions(+)

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v2 4/9] gpio: regmap: add the .fixed_direction_output configuration parameter

[Bartosz Golaszewski]

On Mon, 15 Sep 2025 14:45:58 +0200, Michael Walle <mwalle@kernel.org> said:
> Hi Ioana,
>
> On Mon Sep 15, 2025 at 2:23 PM CEST, Ioana Ciornei wrote:
>> There are GPIO controllers such as the one present in the LX2160ARDB
>> QIXIS FPGA which have fixed-direction input and output GPIO lines mixed
>> together in a single register. This cannot be modeled using the
>> gpio-regmap as-is since there is no way to present the true direction of
>> a GPIO line.
>>
>> In order to make this use case possible, add a new configuration
>> parameter - fixed_direction_output - into the gpio_regmap_config
>> structure. This will enable user drivers to provide a bitmap that
>> represents the fixed direction of the GPIO lines.
>
> I wonder about the ownership of that allocated memory in the config
> structure (and btw, I guess you leak the memory in your driver) and
> if it's not better and more error proof to allocate and copy the
> bitmap in gpio-regmap too (and maybe use devm_bitmap_alloc()) and
> leave it to the caller to handle the passed bitmap. I.e. it could
> also be on the stack.
>

I was under the impression that whatever is in the config structure for GPIO
regmap init function is only required to stay alive until that call returns?

If so, then yes, a deep copy of everything from this structure is required.

> Otherwise, this looks good.
>

[snip]

>>
>> +	if (offset >= chip->ngpio)
>> +		return -EINVAL;
>
> Not sure this can happen. I tried to look into gpiolib.c but
> couldn't find anything obvious that it can't happen. Maybe Linus or
> Bartosz can comment on that.
>

Indeed, this is handed by GPIO core, please drop it.

[snip]

Bartosz

Re: [PATCH v2 2/9] dt-bindings: fsl,fpga-qixis-i2c: extend support to also cover the LX2160ARDB FPGA

[Ioana Ciornei]

On Mon, Sep 15, 2025 at 03:27:42PM -0500, Rob Herring wrote:
> On Mon, Sep 15, 2025 at 03:23:47PM +0300, Ioana Ciornei wrote:
> > Extend the list of supported compatible strings with fsl,lx2160ardb-fpga.
> > 
> > Since the register map exposed by the LX2160ARDB's FPGA also contains
> > two GPIO controllers, accept the necessary GPIO pattern property.
> > At the same time, add the #address-cells and #size-cells properties as
> > valid ones so that the child nodes of the fsl,lx2160ardb-fpga node are
> > addressable.
> > 
> > This is needed because when defining child devices such as the GPIO
> > controller described in the added example, the child device needs a the
> > reg property to properly identify its register location.
> > Impose this restriction for the new compatible through an if-statement.
> > 
> > Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> > ---
> > Changes in v2:
> > - Enforce a unit address on the child gpios nodes (remove the ?)
> > - Enforce the use of unit addresses by having #address-size and
> >   #size-cells only for the newly added fsl,lx2160ardb-fpga compatible
> > 
> >  .../bindings/board/fsl,fpga-qixis-i2c.yaml    | 47 +++++++++++++++++++
> >  1 file changed, 47 insertions(+)
> > 
> > diff --git a/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml b/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
> > index 28b37772fb65..da21d0defa04 100644
> > --- a/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
> > +++ b/Documentation/devicetree/bindings/board/fsl,fpga-qixis-i2c.yaml
> > @@ -22,6 +22,13 @@ properties:
> >                - fsl,lx2160aqds-fpga
> >            - const: fsl,fpga-qixis-i2c
> >            - const: simple-mfd
> > +      - const: fsl,lx2160ardb-fpga
> > +
> > +  "#address-cells":
> > +    const: 1
> > +
> > +  "#size-cells":
> > +    const: 0
> >  
> >    interrupts:
> >      maxItems: 1
> > @@ -32,10 +39,26 @@ properties:
> >    mux-controller:
> >      $ref: /schemas/mux/reg-mux.yaml
> >  
> > +patternProperties:
> > +  "^gpio@[0-9a-f]+$":
> > +    $ref: /schemas/gpio/trivial-gpio.yaml
> 
> This results in this schema being applied twice and more 
> importantly allows any compatible listed in it to be allowed here. So I 
> would drop the $ref and do this instead:
> 
>        additionalProperties: true
> 
>        properties:
>          compatible:
>            contains:
>              enum:
>                - fsl,lx2160ardb-fpga-gpio-sfp
>                ...

Ok, sure. Will do this instead.

I just realized that I didn't update the fsl,fpga-qixis.yaml which
covers the LS1046AQDS board. I will use the same approach there as well
for the gpio@ pattern property.

Thanks!
Ioana

Re: [PATCH v2 1/9] dt-bindings: gpio: add QIXIS FPGA based GPIO controller

[Frank Li]

On Mon, Sep 15, 2025 at 03:23:46PM +0300, Ioana Ciornei wrote:
> Add a device tree binding for the QIXIS FPGA based GPIO controller.
> Depending on the board, the QIXIS FPGA exposes registers which act as a
> GPIO controller, each with 8 GPIO lines of fixed direction.
>
> Since each QIXIS FPGA layout has its particularities, add a separate
> compatible string for each board/GPIO register combination supported.
>
> Since these GPIO controllers are trivial, make use of the newly added
> trivial-gpio.yaml file instead of creating an entirely new one.
>
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> ---
> Changes in v2:
> - Used the newly added trivial-gpio.yaml file
> - Removed redundant "bindings" from commit title
> - Added only one compatible string for the gpio controllers on
>   LX2160ARDB since both registers have the same layout.
>
>  Documentation/devicetree/bindings/gpio/trivial-gpio.yaml | 2 ++
>  1 file changed, 2 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml b/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml
> index c994177de940..3f4bbd57fc52 100644
> --- a/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml
> +++ b/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml
> @@ -22,6 +22,8 @@ properties:
>            - cznic,moxtet-gpio
>            - dlg,slg7xl45106
>            - fcs,fxl6408
> +          - fsl,ls1046aqds-fpga-gpio-stat-pres2
> +          - fsl,lx2160ardb-fpga-gpio-sfp
>            - gateworks,pld-gpio
>            - ibm,ppc4xx-gpio
>            - loongson,ls1x-gpio
> --
> 2.25.1
>

Re: [PATCH v2 2/9] dt-bindings: fsl,fpga-qixis-i2c: extend support to also cover the LX2160ARDB FPGA

[Frank Li]

On Mon, Sep 15, 2025 at 03:23:47PM +0300, Ioana Ciornei wrote:

subject:
dt-bindings: fsl,fpga-qixis-i2c: add support for LX2160ARDB FPGA

> Extend the list of supported compatible strings with fsl,lx2160ardb-fpga.
>
> Since the register map exposed by the LX2160ARDB's FPGA also contains
> two GPIO controllers, accept the necessary GPIO pattern property.
> At the same time, add the #address-cells and #size-cells properties as
> valid ones so that the child nodes of the fsl,lx2160ardb-fpga node are
> addressable.
>
> This is needed because when defining child devices such as the GPIO
> controller described in the added example, the child device needs a the
> reg property to properly identify its register location.

These are neccesary because reg of child gpio controller nodes is in I2C
device's address space.

need empty line here.

> Impose this restriction for the new compatible through an if-statement.
>
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> ---
> Changes in v2:
> - Enforce a unit address on the child gpios nodes (remove the ?)
> - Enforce the use of unit addresses by having #address-size and
>   #size-cells only for the newly added fsl,lx2160ardb-fpga compatible
>
>  .../bindings/board/fsl,fpga-qixis-i2c.yaml    | 47 +++++++++++++++++++
>  1 file changed, 47 insertions(+)
>
...

>
> +allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - fsl,lx2160ardb-fpga
> +    then:
> +      required:
> +        - "#address-cells"
> +        - "#size-cells"
> +
       else:
         properties:
           '#address-cells': false
           'size-cells': false

Frank
>  additionalProperties: false
>
>  examples:
> @@ -68,3 +91,27 @@ examples:
>          };
>      };
>
> +  - |
> +    i2c {
> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +
> +        board-control@66 {
> +            compatible = "fsl,lx2160ardb-fpga";
> +            reg = <0x66>;
> +            #address-cells = <1>;
> +            #size-cells = <0>;
> +
> +            gpio@19 {
> +                compatible = "fsl,lx2160ardb-fpga-gpio-sfp";
> +                reg = <0x19>;
> +                gpio-controller;
> +                #gpio-cells = <2>;
> +                gpio-line-names =
> +                    "SFP2_TX_EN", "",
> +                    "", "",
> +                    "SFP2_RX_LOS", "SFP2_TX_FAULT",
> +                    "", "SFP2_MOD_ABS";
> +            };
> +        };
> +    };
> --
> 2.25.1
>

Re: [PATCH v2 3/9] mfd: simple-mfd-i2c: add compatible string for LX2160ARDB

[Frank Li]

On Mon, Sep 15, 2025 at 03:23:48PM +0300, Ioana Ciornei wrote:
> Extend the list of supported devices with the QIXIS FPGA found on the
> LX2160ARDB board.
>
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> ---
> Changes in v2:
> - none
>
>  drivers/mfd/simple-mfd-i2c.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mfd/simple-mfd-i2c.c b/drivers/mfd/simple-mfd-i2c.c
> index 63ac26388860..6fbe85437d8d 100644
> --- a/drivers/mfd/simple-mfd-i2c.c
> +++ b/drivers/mfd/simple-mfd-i2c.c
> @@ -115,6 +115,7 @@ static const struct of_device_id simple_mfd_i2c_of_match[] = {
>  	{ .compatible = "maxim,max5970", .data = &maxim_max5970},
>  	{ .compatible = "maxim,max5978", .data = &maxim_max5970},
>  	{ .compatible = "maxim,max77705-battery", .data = &maxim_mon_max77705},
> +	{ .compatible = "fsl,lx2160ardb-fpga" },

driver data is the same as fsl,lx2160aqds-fpga.

why not fallback to fsl,lx2160aqds-fpga in dts file ?

Frank

>  	{ .compatible = "fsl,lx2160aqds-fpga" },
>  	{ .compatible = "fsl,ls1028aqds-fpga" },
>  	{ .compatible = "spacemit,p1", .data = &spacemit_p1, },
> --
> 2.25.1
>

Re: [PATCH v2 5/9] drivers: gpio: add QIXIS FPGA GPIO controller

[Frank Li]

On Mon, Sep 15, 2025 at 03:23:50PM +0300, Ioana Ciornei wrote:
> Add support for the GPIO controller found on some QIXIS FPGAs in
> Layerscape boards such as LX2160ARDB and LS1046AQDS. This driver is
> using gpio-regmap.
>
> A GPIO controller has a maximum of 8 lines (all found in the same
> register). Even within the same controller, the GPIO lines' direction is
> fixed, which mean that both input and output lines are found in the same
> register. This is why the driver also passed to gpio-regmap the newly
> added .fixed_direction_output bitmap to represent the true direction of
> the lines.
>
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> ---
> Changes in v2:
> - Use the newly added .fixed_direction_output bitmap representing
>   the fixed direction of the GPIO lines.
>
>  drivers/gpio/Kconfig           |   9 +++
>  drivers/gpio/Makefile          |   1 +
>  drivers/gpio/gpio-qixis-fpga.c | 123 +++++++++++++++++++++++++++++++++
>  3 files changed, 133 insertions(+)
>  create mode 100644 drivers/gpio/gpio-qixis-fpga.c
>
> diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> index 886bef9106da..4ca5890007ff 100644
> --- a/drivers/gpio/Kconfig
> +++ b/drivers/gpio/Kconfig
> @@ -1951,6 +1951,15 @@ config GPIO_LATCH
>  	  Say yes here to enable a driver for GPIO multiplexers based on latches
>  	  connected to other GPIOs.
>
> +config GPIO_QIXIS_FPGA
> +	tristate "NXP QIXIS FPGA GPIO support"
> +	depends on MFD_SIMPLE_MFD_I2C || COMPILE_TEST
> +	select GPIO_REGMAP
> +	help
> +	  This enables support for the GPIOs found in the QIXIS FPGA which is
> +	  integrated on some NXP Layerscape boards such as LX2160ARDB and
> +	  LS1046AQDS.
> +
>  config GPIO_MOCKUP
>  	tristate "GPIO Testing Driver (DEPRECATED)"
>  	select IRQ_SIM
> diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> index 379f55e9ed1e..373b1f169558 100644
> --- a/drivers/gpio/Makefile
> +++ b/drivers/gpio/Makefile
> @@ -144,6 +144,7 @@ obj-$(CONFIG_GPIO_PL061)		+= gpio-pl061.o
>  obj-$(CONFIG_GPIO_PMIC_EIC_SPRD)	+= gpio-pmic-eic-sprd.o
>  obj-$(CONFIG_GPIO_POLARFIRE_SOC)	+= gpio-mpfs.o
>  obj-$(CONFIG_GPIO_PXA)			+= gpio-pxa.o
> +obj-$(CONFIG_GPIO_QIXIS_FPGA)		+= gpio-qixis-fpga.o
>  obj-$(CONFIG_GPIO_RASPBERRYPI_EXP)	+= gpio-raspberrypi-exp.o
>  obj-$(CONFIG_GPIO_RC5T583)		+= gpio-rc5t583.o
>  obj-$(CONFIG_GPIO_RCAR)			+= gpio-rcar.o
> diff --git a/drivers/gpio/gpio-qixis-fpga.c b/drivers/gpio/gpio-qixis-fpga.c
> new file mode 100644
> index 000000000000..23219a634f73
> --- /dev/null
> +++ b/drivers/gpio/gpio-qixis-fpga.c
> @@ -0,0 +1,123 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Layerscape GPIO QIXIS FPGA driver
> + *
> + * Copyright 2025 NXP
> + */
> +
> +#include <linux/device.h>
> +#include <linux/gpio/driver.h>
> +#include <linux/gpio/regmap.h>
> +#include <linux/kernel.h>
> +#include <linux/mod_devicetable.h>
> +#include <linux/module.h>
> +#include <linux/platform_device.h>
> +#include <linux/regmap.h>
> +
> +enum qixis_cpld_gpio_type {
> +	LX2160ARDB_GPIO_SFP = 0,
> +	LS1046AQDS_GPIO_STAT_PRES2,
> +};

needn't type at all.

> +
> +struct qixis_cpld_gpio_config {
> +	enum qixis_cpld_gpio_type type;
> +	u64 output_lines;
> +};
> +
> +static struct qixis_cpld_gpio_config lx2160ardb_sfp_cfg = {
> +	.type = LX2160ARDB_GPIO_SFP,
> +	.output_lines = BIT(0),
> +};
> +
> +static struct qixis_cpld_gpio_config ls1046aqds_stat_pres2_cfg = {
> +	.type = LS1046AQDS_GPIO_STAT_PRES2,
> +	.output_lines = 0x0,
> +};
> +
> +static const struct regmap_config regmap_config_8r_8v = {
> +	.reg_bits = 8,
> +	.val_bits = 8,
> +};
> +
> +static int qixis_cpld_gpio_probe(struct platform_device *pdev)
> +{
> +	const struct qixis_cpld_gpio_config *cfg;
> +	struct gpio_regmap_config config = {0};
> +	struct regmap *regmap;
> +	void __iomem *reg;
> +	u32 base;
> +	int ret;
> +
> +	if (!pdev->dev.parent)
> +		return -ENODEV;
> +
> +	cfg = device_get_match_data(&pdev->dev);
> +	if (!cfg)
> +		return -ENODEV;

Needn't this check.

> +
> +	ret = device_property_read_u32(&pdev->dev, "reg", &base);
> +	if (ret)
> +		return ret;
> +
> +	regmap = dev_get_regmap(pdev->dev.parent, NULL);
> +	if (!regmap) {
> +		/* In case there is no regmap configured by the parent device,
> +		 * create our own.
> +		 */

/* Use MMIO space */

> +		reg = devm_platform_ioremap_resource(pdev, 0);
> +		if (!reg)
> +			return -ENODEV;
> +
> +		regmap = devm_regmap_init_mmio(&pdev->dev, reg, &regmap_config_8r_8v);
> +		if (!regmap)
> +			return -ENODEV;
> +
> +		/* In this case, the offset of our register is 0 inside the
> +		 * regmap area that we just created.
> +		 */
> +		base = 0;
> +	}
> +
> +	config.drvdata = (void *)cfg;
> +	config.regmap = regmap;
> +	config.parent = &pdev->dev;
> +	config.ngpio_per_reg = 8;
> +	config.ngpio = 8;
> +	config.fixed_direction_output = bitmap_alloc(8, GFP_KERNEL);
> +	if (!config.fixed_direction_output)
> +		return -ENOMEM;
> +	bitmap_from_u64(config.fixed_direction_output, cfg->output_lines);
> +
> +	switch (cfg->type) {
> +	case LX2160ARDB_GPIO_SFP:
> +	case LS1046AQDS_GPIO_STAT_PRES2:
> +		config.reg_dat_base = GPIO_REGMAP_ADDR(base);
> +		config.reg_set_base = GPIO_REGMAP_ADDR(base);


only two compatibles string in qixis_cpld_gpio_of_match. so it can set
unconditional.

Frank
> +		break;
> +	}
> +
> +	return PTR_ERR_OR_ZERO(devm_gpio_regmap_register(&pdev->dev, &config));
> +}
> +
> +static const struct of_device_id qixis_cpld_gpio_of_match[] = {
> +	{
> +		.compatible = "fsl,lx2160ardb-fpga-gpio-sfp",
> +		.data = &lx2160ardb_sfp_cfg,
> +	},
> +	{
> +		.compatible = "fsl,ls1046aqds-fpga-gpio-stat-pres2",
> +		.data = &ls1046aqds_stat_pres2_cfg,
> +	},
> +
> +	{}
> +};
> +MODULE_DEVICE_TABLE(of, qixis_cpld_gpio_of_match);
> +
> +static struct platform_driver qixis_cpld_gpio_driver = {
> +	.probe = qixis_cpld_gpio_probe,
> +	.driver = {
> +		.name = "gpio-qixis-cpld",
> +		.of_match_table = qixis_cpld_gpio_of_match,
> +	},
> +};
> +module_platform_driver(qixis_cpld_gpio_driver);
> --
> 2.25.1
>

Re: [PATCH v2 6/9] arm64: dts: lx2160a-rdb: describe the QIXIS FPGA and two child GPIO controllers

[Frank Li]

On Mon, Sep 15, 2025 at 03:23:51PM +0300, Ioana Ciornei wrote:
> Describe the FPGA present on the LX2160ARDB board as a simple-mfd I2C
> device. The FPGA presents registers that deal with power-on-reset
> timing, muxing, SFP cage monitoring and control etc.
>
> Also add the two GPIO controllers responsible for monitoring and
> controlling the SFP+ cages used for MAC5 and MAC6.
>
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> ---
> Changes in v2:
> - Use the same compatible string for both GPIO controller nodes.
>
>  .../boot/dts/freescale/fsl-lx2160a-rdb.dts    | 31 +++++++++++++++++++
>  1 file changed, 31 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> index 0c44b3cbef77..4ede1295f29d 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> @@ -170,6 +170,37 @@ mt35xu512aba1: flash@1 {
>  &i2c0 {
>  	status = "okay";
>
> +	cpld@66 {
> +		compatible = "fsl,lx2160ardb-fpga";
> +		reg = <0x66>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		sfp2_csr: gpio@19 {
> +			compatible = "fsl,lx2160ardb-fpga-gpio-sfp";
> +			reg = <0x19>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-line-names =
> +				"SFP2_TX_EN", "",
> +				"", "",
> +				"SFP2_RX_LOS", "SFP2_TX_FAULT",
> +				"", "SFP2_MOD_ABS";
> +		};
> +
> +		sfp3_csr: gpio@1a {
> +			compatible = "fsl,lx2160ardb-fpga-gpio-sfp";
> +			reg = <0x1a>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-line-names =
> +				"SFP3_TX_EN", "",
> +				"", "",
> +				"SFP3_RX_LOS", "SFP3_TX_FAULT",
> +				"", "SFP3_MOD_ABS";
> +		};
> +	};
> +
>  	i2c-mux@77 {
>  		compatible = "nxp,pca9547";
>  		reg = <0x77>;
> --
> 2.25.1
>

Re: [PATCH v2 7/9] arm64: dts: ls1046a-qds: describe the FPGA based GPIO controller

[Frank Li]

On Mon, Sep 15, 2025 at 03:23:52PM +0300, Ioana Ciornei wrote:
> The QIXIS FPGA node is extended so that it describes the GPIO controller
> responsible for all the status presence lines on both SFP+ cages as well
> as the IO SLOTs present on the board.
>
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> ---
> Changes in v2:
> - none
>
>  arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
> index 736722b58e77..64133e63da96 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
> @@ -166,8 +166,20 @@ nand@1,0 {
>
>  	fpga: board-control@2,0 {
>  		compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-mfd";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
>  		reg = <0x2 0x0 0x0000100>;
>  		ranges = <0 2 0 0x100>;
> +
> +		stat_pres2: gpio-stat-pres2@c {
> +			compatible = "fsl,ls1046aqds-fpga-gpio-stat-pres2";
> +			reg = <0xc 1>;
> +			gpio-controller;
> +			#gpio-cells = <2>;
> +			gpio-line-names =
> +				"SLOT1", "SLOT2", "SLOT3", "SLOT4", "SLOT5", "SLOT6",
> +				"SFP1_MOD_DEF", "SFP2_MOD_DEF";
> +		};
>  	};
>  };
>
> --
> 2.25.1
>

Re: [PATCH v2 8/9] arm64: dts: lx2160a-rdb: fully describe the two SFP+ cages

[Frank Li]

On Mon, Sep 15, 2025 at 03:23:53PM +0300, Ioana Ciornei wrote:
> Describe the two SFP+ cages found on the LX2160ARDB board with their
> respective I2C buses and GPIO lines.
>
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> ---
> Changes in v2:
> - none
>
>  .../boot/dts/freescale/fsl-lx2160a-rdb.dts    | 47 +++++++++++++++++++
>  1 file changed, 47 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> index 4ede1295f29d..62329a93a67a 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> @@ -31,6 +31,28 @@ sb_3v3: regulator-sb3v3 {
>  		regulator-boot-on;
>  		regulator-always-on;
>  	};
> +
> +	sfp2: sfp-2 {
> +		compatible = "sff,sfp";
> +		i2c-bus = <&sfp2_i2c>;
> +		maximum-power-milliwatt = <2000>;
> +		/* Leave commented out if using DPMAC_LINK_TYPE_FIXED mode */
> +		/* tx-disable-gpios = <&sfp2_csr 0 GPIO_ACTIVE_HIGH>; */
> +		los-gpios = <&sfp2_csr 4 GPIO_ACTIVE_HIGH>;
> +		tx-fault-gpios = <&sfp2_csr 5 GPIO_ACTIVE_HIGH>;
> +		mod-def0-gpios = <&sfp2_csr 7 GPIO_ACTIVE_LOW>;
> +	};
> +
> +	sfp3: sfp-3 {
> +		compatible = "sff,sfp";
> +		i2c-bus = <&sfp3_i2c>;
> +		maximum-power-milliwatt = <2000>;
> +		/* Leave commented out if using DPMAC_LINK_TYPE_FIXED mode */
> +		/* tx-disable-gpios = <&sfp3_csr 0 GPIO_ACTIVE_HIGH>; */
> +		los-gpios = <&sfp3_csr 4 GPIO_ACTIVE_HIGH>;
> +		tx-fault-gpios = <&sfp3_csr 5 GPIO_ACTIVE_HIGH>;
> +		mod-def0-gpios = <&sfp3_csr 7 GPIO_ACTIVE_LOW>;
> +	};
>  };
>
>  &crypto {
> @@ -236,6 +258,31 @@ temperature-sensor@4d {
>  				vcc-supply = <&sb_3v3>;
>  			};
>  		};
> +
> +		i2c@7 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x7>;

reg should be first property.

> +
> +			i2c-mux@75 {
> +				compatible = "nxp,pca9547";
> +				reg = <0x75>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				sfp2_i2c: i2c@4 {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <0x4>;

the same here.

Frank
> +				};
> +
> +				sfp3_i2c: i2c@5 {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <0x5>;
> +				};
> +			};
> +		};
>  	};
>  };
>
> --
> 2.25.1
>

Re: [PATCH v2 9/9] arm64: dts: ls1046a-qds: describe the two on-board SFP+ cages

[Frank Li]

On Mon, Sep 15, 2025 at 03:23:54PM +0300, Ioana Ciornei wrote:
> Describe the two SFP+ cages present on the LS1046AQDS board and their
> associated I2C buses and GPIO lines.
>
> Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> ---
> Changes in v2:
> - none
>
>  .../boot/dts/freescale/fsl-ls1046a-qds.dts    | 40 +++++++++++++++++++
>  1 file changed, 40 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
> index 64133e63da96..c188977a901e 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
> @@ -42,6 +42,21 @@ aliases {
>  	chosen {
>  		stdout-path = "serial0:115200n8";
>  	};
> +
> +	sfp1: sfp-1 {
> +		compatible = "sff,sfp";
> +		i2c-bus = <&sfp1_i2c>;
> +		maximum-power-milliwatt = <2000>;
> +		mod-def0-gpios = <&stat_pres2 6 GPIO_ACTIVE_LOW>;
> +	};
> +
> +	sfp2: sfp-2 {
> +		compatible = "sff,sfp";
> +		i2c-bus = <&sfp2_i2c>;
> +		maximum-power-milliwatt = <2000>;
> +		mod-def0-gpios = <&stat_pres2 7 GPIO_ACTIVE_LOW>;
> +	};
> +
>  };
>
>  &dspi {
> @@ -139,6 +154,31 @@ temp-sensor@4c {
>  				reg = <0x4c>;
>  			};
>  		};
> +
> +		i2c@7 {
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x7>;

reg should be before #address-cells

Frank
> +
> +			i2c-mux@76 {
> +				compatible = "nxp,pca9547";
> +				reg = <0x76>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				sfp1_i2c: i2c@6 {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <0x6>;
> +				};
> +
> +				sfp2_i2c: i2c@7 {
> +					#address-cells = <1>;
> +					#size-cells = <0>;
> +					reg = <0x7>;
> +				};
> +			};
> +		};
>  	};
>  };
>
> --
> 2.25.1
>

Re: [PATCH v2 2/9] dt-bindings: fsl,fpga-qixis-i2c: extend support to also cover the LX2160ARDB FPGA

[Ioana Ciornei]

On Tue, Sep 16, 2025 at 12:18:10PM -0400, Frank Li wrote:
> On Mon, Sep 15, 2025 at 03:23:47PM +0300, Ioana Ciornei wrote:
> 
> subject:
> dt-bindings: fsl,fpga-qixis-i2c: add support for LX2160ARDB FPGA
> 
> > Extend the list of supported compatible strings with fsl,lx2160ardb-fpga.
> >
> > Since the register map exposed by the LX2160ARDB's FPGA also contains
> > two GPIO controllers, accept the necessary GPIO pattern property.
> > At the same time, add the #address-cells and #size-cells properties as
> > valid ones so that the child nodes of the fsl,lx2160ardb-fpga node are
> > addressable.
> >
> > This is needed because when defining child devices such as the GPIO
> > controller described in the added example, the child device needs a the
> > reg property to properly identify its register location.
> 
> These are neccesary because reg of child gpio controller nodes is in I2C
> device's address space.

Will incorporate the remark in this paragraph.

> 
> need empty line here.

Ok.

> 
> > Impose this restriction for the new compatible through an if-statement.
> >
> > Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> > ---
> > Changes in v2:
> > - Enforce a unit address on the child gpios nodes (remove the ?)
> > - Enforce the use of unit addresses by having #address-size and
> >   #size-cells only for the newly added fsl,lx2160ardb-fpga compatible
> >
> >  .../bindings/board/fsl,fpga-qixis-i2c.yaml    | 47 +++++++++++++++++++
> >  1 file changed, 47 insertions(+)
> >
> ...
> 
> >
> > +allOf:
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - fsl,lx2160ardb-fpga
> > +    then:
> > +      required:
> > +        - "#address-cells"
> > +        - "#size-cells"
> > +
>        else:
>          properties:
>            '#address-cells': false
>            'size-cells': false

So that we also catch the cases in which address-cells/size-cells
shoudn't be used. Will do.

Thanks,
Ioana

Re: [PATCH v2 3/9] mfd: simple-mfd-i2c: add compatible string for LX2160ARDB

[Ioana Ciornei]

On Tue, Sep 16, 2025 at 12:20:24PM -0400, Frank Li wrote:
> On Mon, Sep 15, 2025 at 03:23:48PM +0300, Ioana Ciornei wrote:
> > Extend the list of supported devices with the QIXIS FPGA found on the
> > LX2160ARDB board.
> >
> > Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> > ---
> > Changes in v2:
> > - none
> >
> >  drivers/mfd/simple-mfd-i2c.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/drivers/mfd/simple-mfd-i2c.c b/drivers/mfd/simple-mfd-i2c.c
> > index 63ac26388860..6fbe85437d8d 100644
> > --- a/drivers/mfd/simple-mfd-i2c.c
> > +++ b/drivers/mfd/simple-mfd-i2c.c
> > @@ -115,6 +115,7 @@ static const struct of_device_id simple_mfd_i2c_of_match[] = {
> >  	{ .compatible = "maxim,max5970", .data = &maxim_max5970},
> >  	{ .compatible = "maxim,max5978", .data = &maxim_max5970},
> >  	{ .compatible = "maxim,max77705-battery", .data = &maxim_mon_max77705},
> > +	{ .compatible = "fsl,lx2160ardb-fpga" },
> 
> driver data is the same as fsl,lx2160aqds-fpga.
> 
> why not fallback to fsl,lx2160aqds-fpga in dts file ?
> 

The register layout of the FPGA is different between the RDB and QDS
boards. Even though there is no difference in terms of the
simple-mfd-i2c driver, I still want to have the ability to differentiate
between them. Also, the if/then added in patch 2/9 would not be
possible.

Re: [PATCH v2 5/9] drivers: gpio: add QIXIS FPGA GPIO controller

[Ioana Ciornei]

On Tue, Sep 16, 2025 at 12:39:02PM -0400, Frank Li wrote:
> On Mon, Sep 15, 2025 at 03:23:50PM +0300, Ioana Ciornei wrote:
> > Add support for the GPIO controller found on some QIXIS FPGAs in
> > Layerscape boards such as LX2160ARDB and LS1046AQDS. This driver is
> > using gpio-regmap.
> >
> > A GPIO controller has a maximum of 8 lines (all found in the same
> > register). Even within the same controller, the GPIO lines' direction is
> > fixed, which mean that both input and output lines are found in the same
> > register. This is why the driver also passed to gpio-regmap the newly
> > added .fixed_direction_output bitmap to represent the true direction of
> > the lines.
> >
> > Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> > ---
> > Changes in v2:
> > - Use the newly added .fixed_direction_output bitmap representing
> >   the fixed direction of the GPIO lines.
> >
> >  drivers/gpio/Kconfig           |   9 +++
> >  drivers/gpio/Makefile          |   1 +
> >  drivers/gpio/gpio-qixis-fpga.c | 123 +++++++++++++++++++++++++++++++++
> >  3 files changed, 133 insertions(+)
> >  create mode 100644 drivers/gpio/gpio-qixis-fpga.c
> >
> > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
> > index 886bef9106da..4ca5890007ff 100644
> > --- a/drivers/gpio/Kconfig
> > +++ b/drivers/gpio/Kconfig
> > @@ -1951,6 +1951,15 @@ config GPIO_LATCH
> >  	  Say yes here to enable a driver for GPIO multiplexers based on latches
> >  	  connected to other GPIOs.
> >
> > +config GPIO_QIXIS_FPGA
> > +	tristate "NXP QIXIS FPGA GPIO support"
> > +	depends on MFD_SIMPLE_MFD_I2C || COMPILE_TEST
> > +	select GPIO_REGMAP
> > +	help
> > +	  This enables support for the GPIOs found in the QIXIS FPGA which is
> > +	  integrated on some NXP Layerscape boards such as LX2160ARDB and
> > +	  LS1046AQDS.
> > +
> >  config GPIO_MOCKUP
> >  	tristate "GPIO Testing Driver (DEPRECATED)"
> >  	select IRQ_SIM
> > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
> > index 379f55e9ed1e..373b1f169558 100644
> > --- a/drivers/gpio/Makefile
> > +++ b/drivers/gpio/Makefile
> > @@ -144,6 +144,7 @@ obj-$(CONFIG_GPIO_PL061)		+= gpio-pl061.o
> >  obj-$(CONFIG_GPIO_PMIC_EIC_SPRD)	+= gpio-pmic-eic-sprd.o
> >  obj-$(CONFIG_GPIO_POLARFIRE_SOC)	+= gpio-mpfs.o
> >  obj-$(CONFIG_GPIO_PXA)			+= gpio-pxa.o
> > +obj-$(CONFIG_GPIO_QIXIS_FPGA)		+= gpio-qixis-fpga.o
> >  obj-$(CONFIG_GPIO_RASPBERRYPI_EXP)	+= gpio-raspberrypi-exp.o
> >  obj-$(CONFIG_GPIO_RC5T583)		+= gpio-rc5t583.o
> >  obj-$(CONFIG_GPIO_RCAR)			+= gpio-rcar.o
> > diff --git a/drivers/gpio/gpio-qixis-fpga.c b/drivers/gpio/gpio-qixis-fpga.c
> > new file mode 100644
> > index 000000000000..23219a634f73
> > --- /dev/null
> > +++ b/drivers/gpio/gpio-qixis-fpga.c
> > @@ -0,0 +1,123 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Layerscape GPIO QIXIS FPGA driver
> > + *
> > + * Copyright 2025 NXP
> > + */
> > +
> > +#include <linux/device.h>
> > +#include <linux/gpio/driver.h>
> > +#include <linux/gpio/regmap.h>
> > +#include <linux/kernel.h>
> > +#include <linux/mod_devicetable.h>
> > +#include <linux/module.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/regmap.h>
> > +
> > +enum qixis_cpld_gpio_type {
> > +	LX2160ARDB_GPIO_SFP = 0,
> > +	LS1046AQDS_GPIO_STAT_PRES2,
> > +};
> 
> needn't type at all.
> 

True, I can just pass the u64 bitmap directly as data. Will try.

[snip]

> > +	if (!pdev->dev.parent)
> > +		return -ENODEV;
> > +
> > +	cfg = device_get_match_data(&pdev->dev);
> > +	if (!cfg)
> > +		return -ENODEV;
> 
> Needn't this check.

Ok.

> 
> > +
> > +	ret = device_property_read_u32(&pdev->dev, "reg", &base);
> > +	if (ret)
> > +		return ret;
> > +
> > +	regmap = dev_get_regmap(pdev->dev.parent, NULL);
> > +	if (!regmap) {
> > +		/* In case there is no regmap configured by the parent device,
> > +		 * create our own.
> > +		 */
> 
> /* Use MMIO space */

Ok.


[snip]

> +		config.reg_set_base = GPIO_REGMAP_ADDR(base);
> 
> 
> only two compatibles string in qixis_cpld_gpio_of_match. so it can set
> unconditional.
> 

Fair point. Will change.

Ioana

Re: [PATCH v2 8/9] arm64: dts: lx2160a-rdb: fully describe the two SFP+ cages

[Ioana Ciornei]

On Tue, Sep 16, 2025 at 12:46:26PM -0400, Frank Li wrote:
> On Mon, Sep 15, 2025 at 03:23:53PM +0300, Ioana Ciornei wrote:
> > Describe the two SFP+ cages found on the LX2160ARDB board with their
> > respective I2C buses and GPIO lines.
> >
> > Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
> > ---
> > Changes in v2:
> > - none
> >
> >  .../boot/dts/freescale/fsl-lx2160a-rdb.dts    | 47 +++++++++++++++++++
> >  1 file changed, 47 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > index 4ede1295f29d..62329a93a67a 100644
> > --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts
> > @@ -31,6 +31,28 @@ sb_3v3: regulator-sb3v3 {
> >  		regulator-boot-on;
> >  		regulator-always-on;
> >  	};
> > +
> > +	sfp2: sfp-2 {
> > +		compatible = "sff,sfp";
> > +		i2c-bus = <&sfp2_i2c>;
> > +		maximum-power-milliwatt = <2000>;
> > +		/* Leave commented out if using DPMAC_LINK_TYPE_FIXED mode */
> > +		/* tx-disable-gpios = <&sfp2_csr 0 GPIO_ACTIVE_HIGH>; */
> > +		los-gpios = <&sfp2_csr 4 GPIO_ACTIVE_HIGH>;
> > +		tx-fault-gpios = <&sfp2_csr 5 GPIO_ACTIVE_HIGH>;
> > +		mod-def0-gpios = <&sfp2_csr 7 GPIO_ACTIVE_LOW>;
> > +	};
> > +
> > +	sfp3: sfp-3 {
> > +		compatible = "sff,sfp";
> > +		i2c-bus = <&sfp3_i2c>;
> > +		maximum-power-milliwatt = <2000>;
> > +		/* Leave commented out if using DPMAC_LINK_TYPE_FIXED mode */
> > +		/* tx-disable-gpios = <&sfp3_csr 0 GPIO_ACTIVE_HIGH>; */
> > +		los-gpios = <&sfp3_csr 4 GPIO_ACTIVE_HIGH>;
> > +		tx-fault-gpios = <&sfp3_csr 5 GPIO_ACTIVE_HIGH>;
> > +		mod-def0-gpios = <&sfp3_csr 7 GPIO_ACTIVE_LOW>;
> > +	};
> >  };
> >
> >  &crypto {
> > @@ -236,6 +258,31 @@ temperature-sensor@4d {
> >  				vcc-supply = <&sb_3v3>;
> >  			};
> >  		};
> > +
> > +		i2c@7 {
> > +			#address-cells = <1>;
> > +			#size-cells = <0>;
> > +			reg = <0x7>;
> 
> reg should be first property.
> 

Ok. Will change all occurrences.

Ioana

Re: [PATCH v2 5/9] drivers: gpio: add QIXIS FPGA GPIO controller

[Bartosz Golaszewski]

On Wed, 17 Sep 2025 09:40:37 +0200, Ioana Ciornei <ioana.ciornei@nxp.com> said:
> On Tue, Sep 16, 2025 at 12:39:02PM -0400, Frank Li wrote:
>> On Mon, Sep 15, 2025 at 03:23:50PM +0300, Ioana Ciornei wrote:
>> > Add support for the GPIO controller found on some QIXIS FPGAs in
>> > Layerscape boards such as LX2160ARDB and LS1046AQDS. This driver is
>> > using gpio-regmap.
>> >
>> > A GPIO controller has a maximum of 8 lines (all found in the same
>> > register). Even within the same controller, the GPIO lines' direction is
>> > fixed, which mean that both input and output lines are found in the same
>> > register. This is why the driver also passed to gpio-regmap the newly
>> > added .fixed_direction_output bitmap to represent the true direction of
>> > the lines.
>> >
>> > Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
>> > ---
>> > Changes in v2:
>> > - Use the newly added .fixed_direction_output bitmap representing
>> >   the fixed direction of the GPIO lines.
>> >
>> >  drivers/gpio/Kconfig           |   9 +++
>> >  drivers/gpio/Makefile          |   1 +
>> >  drivers/gpio/gpio-qixis-fpga.c | 123 +++++++++++++++++++++++++++++++++
>> >  3 files changed, 133 insertions(+)
>> >  create mode 100644 drivers/gpio/gpio-qixis-fpga.c
>> >
>> > diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
>> > index 886bef9106da..4ca5890007ff 100644
>> > --- a/drivers/gpio/Kconfig
>> > +++ b/drivers/gpio/Kconfig
>> > @@ -1951,6 +1951,15 @@ config GPIO_LATCH
>> >  	  Say yes here to enable a driver for GPIO multiplexers based on latches
>> >  	  connected to other GPIOs.
>> >
>> > +config GPIO_QIXIS_FPGA
>> > +	tristate "NXP QIXIS FPGA GPIO support"
>> > +	depends on MFD_SIMPLE_MFD_I2C || COMPILE_TEST
>> > +	select GPIO_REGMAP
>> > +	help
>> > +	  This enables support for the GPIOs found in the QIXIS FPGA which is
>> > +	  integrated on some NXP Layerscape boards such as LX2160ARDB and
>> > +	  LS1046AQDS.
>> > +
>> >  config GPIO_MOCKUP
>> >  	tristate "GPIO Testing Driver (DEPRECATED)"
>> >  	select IRQ_SIM
>> > diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
>> > index 379f55e9ed1e..373b1f169558 100644
>> > --- a/drivers/gpio/Makefile
>> > +++ b/drivers/gpio/Makefile
>> > @@ -144,6 +144,7 @@ obj-$(CONFIG_GPIO_PL061)		+= gpio-pl061.o
>> >  obj-$(CONFIG_GPIO_PMIC_EIC_SPRD)	+= gpio-pmic-eic-sprd.o
>> >  obj-$(CONFIG_GPIO_POLARFIRE_SOC)	+= gpio-mpfs.o
>> >  obj-$(CONFIG_GPIO_PXA)			+= gpio-pxa.o
>> > +obj-$(CONFIG_GPIO_QIXIS_FPGA)		+= gpio-qixis-fpga.o
>> >  obj-$(CONFIG_GPIO_RASPBERRYPI_EXP)	+= gpio-raspberrypi-exp.o
>> >  obj-$(CONFIG_GPIO_RC5T583)		+= gpio-rc5t583.o
>> >  obj-$(CONFIG_GPIO_RCAR)			+= gpio-rcar.o
>> > diff --git a/drivers/gpio/gpio-qixis-fpga.c b/drivers/gpio/gpio-qixis-fpga.c
>> > new file mode 100644
>> > index 000000000000..23219a634f73
>> > --- /dev/null
>> > +++ b/drivers/gpio/gpio-qixis-fpga.c
>> > @@ -0,0 +1,123 @@
>> > +// SPDX-License-Identifier: GPL-2.0-only
>> > +/*
>> > + * Layerscape GPIO QIXIS FPGA driver
>> > + *
>> > + * Copyright 2025 NXP
>> > + */
>> > +
>> > +#include <linux/device.h>
>> > +#include <linux/gpio/driver.h>
>> > +#include <linux/gpio/regmap.h>
>> > +#include <linux/kernel.h>
>> > +#include <linux/mod_devicetable.h>
>> > +#include <linux/module.h>
>> > +#include <linux/platform_device.h>
>> > +#include <linux/regmap.h>
>> > +
>> > +enum qixis_cpld_gpio_type {
>> > +	LX2160ARDB_GPIO_SFP = 0,
>> > +	LS1046AQDS_GPIO_STAT_PRES2,
>> > +};
>>
>> needn't type at all.
>>
>
> True, I can just pass the u64 bitmap directly as data. Will try.
>
> [snip]
>
>> > +	if (!pdev->dev.parent)
>> > +		return -ENODEV;
>> > +
>> > +	cfg = device_get_match_data(&pdev->dev);
>> > +	if (!cfg)
>> > +		return -ENODEV;
>>
>> Needn't this check.
>
> Ok.
>
>>
>> > +
>> > +	ret = device_property_read_u32(&pdev->dev, "reg", &base);
>> > +	if (ret)
>> > +		return ret;
>> > +
>> > +	regmap = dev_get_regmap(pdev->dev.parent, NULL);
>> > +	if (!regmap) {
>> > +		/* In case there is no regmap configured by the parent device,
>> > +		 * create our own.
>> > +		 */
>>
>> /* Use MMIO space */
>
> Ok.
>
>
> [snip]
>
>> +		config.reg_set_base = GPIO_REGMAP_ADDR(base);
>>
>>
>> only two compatibles string in qixis_cpld_gpio_of_match. so it can set
>> unconditional.
>>
>
> Fair point. Will change.
>
> Ioana
>

When sending the next revision please change the title to: "gpio: foo: ...",
IOW: drop the drivers prefix.

Bartosz