From: Randolph Sapp <rs@ti.com>
To: Kevin Hilman <khilman@kernel.org>,
Michael Walle <mwalle@kernel.org>,
Frank Binns <frank.binns@imgtec.com>,
Matt Coster <matt.coster@imgtec.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>, Nishanth Menon <nm@ti.com>,
"Vignesh Raghavendra" <vigneshr@ti.com>,
Tero Kristo <kristo@kernel.org>,
"Santosh Shilimkar" <ssantosh@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>
Cc: Andrew Davis <afd@ti.com>, <dri-devel@lists.freedesktop.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-clk@vger.kernel.org>
Subject: Re: [PATCH 2/3] clk: keystone: don't cache clock rate
Date: Wed, 24 Sep 2025 21:26:17 -0500 [thread overview]
Message-ID: <DD1IXJDTBQ72.2XIEIIN0YA713@ti.com> (raw)
In-Reply-To: <7hv7lhp0e8.fsf@baylibre.com>
On Wed Sep 17, 2025 at 10:24 AM CDT, Kevin Hilman wrote:
> Michael Walle <mwalle@kernel.org> writes:
>
>> The TISCI firmware will return 0 if the clock or consumer is not
>> enabled although there is a stored value in the firmware. IOW a call to
>> set rate will work but at get rate will always return 0 if the clock is
>> disabled.
>> The clk framework will try to cache the clock rate when it's requested
>> by a consumer. If the clock or consumer is not enabled at that point,
>> the cached value is 0, which is wrong.
>
> Hmm, it also seems wrong to me that the clock framework would cache a
> clock rate when it's disabled. On platforms with clocks that may have
> shared management (eg. TISCI or other platforms using SCMI) it's
> entirely possible that when Linux has disabled a clock, some other
> entity may have changed it.
>
> Could another solution here be to have the clk framework only cache when
> clocks are enabled?
So I looked into that. There are still about 34 clock operations that are
functionally uncached, but it does seem more logical than treating everything as
uncached.
Side note, why would someone even want to read the rate of an unprepared clock?
I dumped some debug info for all the clocks tripping this new uncached path.
Seems weird that it's even happening this often. Even weirder that it's
apparently happening 3 times to cpu0's core clock on the board I'm currently
testing.
Some devices it only happens once, others get it two or three times. Most of
them seem to be obvious - someone trying to read a rate before the clock was
prepared as part of a probe sequence. One seemed to be happening directly after
a clk_prepare_enable call that completed successfully. Not sure how that could
happen.
>> Thus, disable the cache altogether.
>>
>> Signed-off-by: Michael Walle <mwalle@kernel.org>
>> ---
>> I guess to make it work correctly with the caching of the linux
>> subsystem a new flag to query the real clock rate is needed. That
>> way, one could also query the default value without having to turn
>> the clock and consumer on first. That can be retrofitted later and
>> the driver could query the firmware capabilities.
>>
>> Regarding a Fixes: tag. I didn't include one because it might have a
>> slight performance impact because the firmware has to be queried
>> every time now and it doesn't have been a problem for now. OTOH I've
>> enabled tracing during boot and there were just a handful
>> clock_{get/set}_rate() calls.
>
> The performance hit is not just about boot time, it's for *every*
> [get|set]_rate call. Since TISCI is relatively slow (involves RPC,
> mailbox, etc. to remote core), this may have a performance impact
> elsewhere too. That being said, I'm hoping it's unlikely that
> [get|set]_rate calls are in the fast path.
>
> All of that being said, I think the impacts of this patch are pretty
> minimal, so I don't have any real objections.
>
> Reviewed-by: Kevin Hilman <khilman@baylibre.com>
>
>> ---
>> drivers/clk/keystone/sci-clk.c | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/drivers/clk/keystone/sci-clk.c b/drivers/clk/keystone/sci-clk.c
>> index c5894fc9395e..d73858b5ca7a 100644
>> --- a/drivers/clk/keystone/sci-clk.c
>> +++ b/drivers/clk/keystone/sci-clk.c
>> @@ -333,6 +333,14 @@ static int _sci_clk_build(struct sci_clk_provider *provider,
>>
>> init.ops = &sci_clk_ops;
>> init.num_parents = sci_clk->num_parents;
>> +
>> + /*
>> + * A clock rate query to the SCI firmware will return 0 if either the
>> + * clock itself is disabled or the attached device/consumer is disabled.
>> + * This makes it inherently unsuitable for the caching of the clk
>> + * framework.
>> + */
>> + init.flags = CLK_GET_RATE_NOCACHE;
>> sci_clk->hw.init = &init;
>>
>> ret = devm_clk_hw_register(provider->dev, &sci_clk->hw);
>> --
>> 2.39.5
next prev parent reply other threads:[~2025-09-25 2:26 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-15 14:34 [PATCH 0/3] drm/imagination: add AM62P/AM67A/J722S support Michael Walle
2025-09-15 14:34 ` [PATCH 1/3] dt-bindings: gpu: img: Add AM62P SoC specific compatible Michael Walle
2025-09-15 17:19 ` Conor Dooley
2025-09-15 14:34 ` [PATCH 2/3] clk: keystone: don't cache clock rate Michael Walle
2025-09-17 15:24 ` Kevin Hilman
2025-09-18 9:48 ` Michael Walle
2025-09-18 18:03 ` Dhruva Gole
2025-09-19 7:10 ` Michael Walle
2025-09-23 9:07 ` Maxime Ripard
2025-09-25 2:26 ` Randolph Sapp [this message]
2025-09-25 11:43 ` Maxime Ripard
2025-09-25 18:32 ` Randolph Sapp
2025-09-19 18:50 ` Randolph Sapp
2025-09-22 7:23 ` Michael Walle
2025-09-15 14:34 ` [PATCH 3/3] arm64: dts: ti: add GPU node Michael Walle
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