From: Randolph Sapp <rs@ti.com>
To: Maxime Ripard <mripard@kernel.org>, Randolph Sapp <rs@ti.com>
Cc: Kevin Hilman <khilman@kernel.org>,
Michael Walle <mwalle@kernel.org>,
Frank Binns <frank.binns@imgtec.com>,
Matt Coster <matt.coster@imgtec.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Thomas Zimmermann <tzimmermann@suse.de>,
David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, "Nishanth Menon" <nm@ti.com>,
Vignesh Raghavendra <vigneshr@ti.com>,
Tero Kristo <kristo@kernel.org>,
Santosh Shilimkar <ssantosh@kernel.org>,
"Michael Turquette" <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Andrew Davis <afd@ti.com>,
<dri-devel@lists.freedesktop.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-clk@vger.kernel.org>
Subject: Re: [PATCH 2/3] clk: keystone: don't cache clock rate
Date: Thu, 25 Sep 2025 13:32:37 -0500 [thread overview]
Message-ID: <DD23HER39PNM.O17TMFNNWD37@ti.com> (raw)
In-Reply-To: <20250925-elephant-of-absolute-prowess-a97fcd@penduick>
On Thu Sep 25, 2025 at 6:43 AM CDT, Maxime Ripard wrote:
> On Wed, Sep 24, 2025 at 09:26:17PM -0500, Randolph Sapp wrote:
>> On Wed Sep 17, 2025 at 10:24 AM CDT, Kevin Hilman wrote:
>> > Michael Walle <mwalle@kernel.org> writes:
>> >
>> >> The TISCI firmware will return 0 if the clock or consumer is not
>> >> enabled although there is a stored value in the firmware. IOW a call to
>> >> set rate will work but at get rate will always return 0 if the clock is
>> >> disabled.
>> >> The clk framework will try to cache the clock rate when it's requested
>> >> by a consumer. If the clock or consumer is not enabled at that point,
>> >> the cached value is 0, which is wrong.
>> >
>> > Hmm, it also seems wrong to me that the clock framework would cache a
>> > clock rate when it's disabled. On platforms with clocks that may have
>> > shared management (eg. TISCI or other platforms using SCMI) it's
>> > entirely possible that when Linux has disabled a clock, some other
>> > entity may have changed it.
>> >
>> > Could another solution here be to have the clk framework only cache when
>> > clocks are enabled?
>>
>> So I looked into that. There are still about 34 clock operations that are
>> functionally uncached, but it does seem more logical than treating everything as
>> uncached.
>>
>> Side note, why would someone even want to read the rate of an unprepared clock?
>> I dumped some debug info for all the clocks tripping this new uncached path.
>> Seems weird that it's even happening this often. Even weirder that it's
>> apparently happening 3 times to cpu0's core clock on the board I'm currently
>> testing.
>
> The short, unsatisfying, answer is that the API explicitly allowed it so far.
>
> It's also somewhat natural when you have a functional rate to set it up
> before enabling it and the logic driven by it so that you would avoid a
> rate change, or something like a cycle where you would enable, shut
> down, reparent, enable the clock again.
>
> In such a case, we would either need the cache, or to read the rate, to
> know if we have to change the clock rate in the first place.
>
> Maxime
Thanks Maxime. I'll take this as a hint to stop digging for the moment. Right
now, treating unprepared clocks as untrusted / uncached makes sense and
shouldn't be too much of a performance issue.
- Randolph
next prev parent reply other threads:[~2025-09-25 18:33 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-15 14:34 [PATCH 0/3] drm/imagination: add AM62P/AM67A/J722S support Michael Walle
2025-09-15 14:34 ` [PATCH 1/3] dt-bindings: gpu: img: Add AM62P SoC specific compatible Michael Walle
2025-09-15 17:19 ` Conor Dooley
2025-09-15 14:34 ` [PATCH 2/3] clk: keystone: don't cache clock rate Michael Walle
2025-09-17 15:24 ` Kevin Hilman
2025-09-18 9:48 ` Michael Walle
2025-09-18 18:03 ` Dhruva Gole
2025-09-19 7:10 ` Michael Walle
2025-09-23 9:07 ` Maxime Ripard
2025-09-25 2:26 ` Randolph Sapp
2025-09-25 11:43 ` Maxime Ripard
2025-09-25 18:32 ` Randolph Sapp [this message]
2025-09-19 18:50 ` Randolph Sapp
2025-09-22 7:23 ` Michael Walle
2025-09-15 14:34 ` [PATCH 3/3] arm64: dts: ti: add GPU node Michael Walle
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=DD23HER39PNM.O17TMFNNWD37@ti.com \
--to=rs@ti.com \
--cc=afd@ti.com \
--cc=airlied@gmail.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=dri-devel@lists.freedesktop.org \
--cc=frank.binns@imgtec.com \
--cc=khilman@kernel.org \
--cc=kristo@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=maarten.lankhorst@linux.intel.com \
--cc=matt.coster@imgtec.com \
--cc=mripard@kernel.org \
--cc=mturquette@baylibre.com \
--cc=mwalle@kernel.org \
--cc=nm@ti.com \
--cc=robh@kernel.org \
--cc=sboyd@kernel.org \
--cc=simona@ffwll.ch \
--cc=ssantosh@kernel.org \
--cc=tzimmermann@suse.de \
--cc=vigneshr@ti.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).