devicetree.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: "Luca Ceresoli" <luca.ceresoli@bootlin.com>
To: "Svyatoslav Ryhel" <clamor95@gmail.com>
Cc: "Mikko Perttunen" <mperttunen@nvidia.com>,
	"David Airlie" <airlied@gmail.com>,
	"Simona Vetter" <simona@ffwll.ch>,
	"Maarten Lankhorst" <maarten.lankhorst@linux.intel.com>,
	"Maxime Ripard" <mripard@kernel.org>,
	"Thomas Zimmermann" <tzimmermann@suse.de>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Thierry Reding" <thierry.reding@gmail.com>,
	"Jonathan Hunter" <jonathanh@nvidia.com>,
	"Sowjanya Komatineni" <skomatineni@nvidia.com>,
	"Prashant Gaikwad" <pgaikwad@nvidia.com>,
	"Michael Turquette" <mturquette@baylibre.com>,
	"Stephen Boyd" <sboyd@kernel.org>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	"Mauro Carvalho Chehab" <mchehab@kernel.org>,
	"Greg Kroah-Hartman" <gregkh@linuxfoundation.org>,
	"Jonas Schwöbel" <jonasschwoebel@yahoo.de>,
	"Dmitry Osipenko" <digetx@gmail.com>,
	"Charan Pedumuru" <charan.pedumuru@gmail.com>,
	"Diogo Ivo" <diogo.ivo@tecnico.ulisboa.pt>,
	"Aaron Kling" <webgeek1234@gmail.com>,
	"Arnd Bergmann" <arnd@arndb.de>,
	dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org,
	linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-media@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-gpio@vger.kernel.org, linux-staging@lists.linux.dev
Subject: Re: [PATCH v3 15/22] staging: media: tegra-video: tegra20: simplify format align calculations
Date: Tue, 07 Oct 2025 21:37:39 +0200	[thread overview]
Message-ID: <DDCCDQMTQG55.1K25Y3U0JE15Q@bootlin.com> (raw)
In-Reply-To: <CAPVz0n3EB-tw0af+O4acmbvXNHkH62t5v3r3O0nedLs_XJ39PA@mail.gmail.com>

Hello Svyatoslav,

On Tue Oct 7, 2025 at 6:02 PM CEST, Svyatoslav Ryhel wrote:
> пн, 6 жовт. 2025 р. о 21:55 Luca Ceresoli <luca.ceresoli@bootlin.com> пише:
>>
>> Hello Svyatoslav,
>>
>> On Thu Oct 2, 2025 at 8:20 AM CEST, Svyatoslav Ryhel wrote:
>> >> > > > 12 represents amount of bits used per pixel, 8 for Y plane, 2 for U
>> >> > > > plane and 2 for V plane, total is 12. "but explainable with a comment
>> >> > > > and improve-able later" why then we cannot use 12 with a comment? this
>> >> > > > is all arbitrary. Downstream is not wrong from this perspective, you
>> >> > > > don't take into account that YUV420 is planar and it uses 3 planes a
>> >> > > > whole Y plane and 1/4 of U and V which in total results in wigth + 2 *
>> >> > > > 1/4 width which is width * 3/2
>> >> > >
>> >> > > Yes -- but AIUI, the only thing the bpp value is used for the bytesperline calculation. When we add the special case for planar formats, which doesn't use the bpp value, then the value 12 is never used anywhere. We should at least have a comment saying it is unused. (At that point, we could just hardcode the bpp values in the fmt_align function -- but I don't mind either way.)
>> >> > >
>> >> > https://ffmpeg.org/pipermail/ffmpeg-user/2023-June/056488.html
>> >>
>> >> I understand very well that for YUV420, each pixel has 12 bits of color information. But how many bits of color information each pixel has is not useful in the context of this driver. The number of bytes per line is not related to how many bits of color information each pixel has for planar formats.
>> >
>> > No, it has direct impact. This is how buffer size / image size is
>> > calculated since we place each plane consecutive. And bytes per line
>> > is used specifically in image size calculation. This is common part
>> > with non-planar formats. Then since Tegra provides a dedicated
>> > channels/buffers for each plane, configuration of planar format
>> > includes an additional step with calculation for each plane.
>>
>> Sorry, I haven't followed the discussion in detail, but I tested you series
>> on Tegra20 VIP and capture does not work, with a SIGSEGV in
>> gstreamer. Bisecting pointed to this as the first commit where the issue
>> happens.
>>
>> I compared the input and output values of tegra20_fmt_align() at this
>> commit and at the previous one, and this is the result:
>>
>>                        before this patch     with this patch
>>   At function entry:
>>   bpp                        1                     12
>>   pix->width                 640                   640
>>   pix->height                480                   480
>>
>>   On return:
>>   pix->bytesperline          640                   960
>>   pix->sizeimage             460800                460800
>>
>> I hope these info will help.
>
> Which command did you use? I have tested with ffmpeg and
> yuv422/yuv420p and it worked perfectly fine.

I have a simple testing script that runs these commands, with
VNODE="/dev/video0":

v4l2-ctl -d ${VNODE} --set-ctrl horizontal_flip=1 --set-ctrl vertical_flip=1

gst-launch-1.0 -ve v4l2src device=${VNODE} num-buffers=500 \
  ! video/x-raw,width=640,height=480,framerate=50/1,format=I420 \
  ! videorate drop-only=true skip-to-first=true \
  ! video/x-raw,framerate=50/4 \
  ! queue \
  ! avenc_mpeg4 \
  ! mp4mux \
  ! filesink location=/tmp/grab.mp4

Luca

--
Luca Ceresoli, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

  reply	other threads:[~2025-10-07 19:38 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-25 15:16 [PATCH v3 00/22] tegra-video: add CSI support for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 01/22] clk: tegra: set CSUS as vi_sensor's gate for Tegra20, Tegra30 and Tegra114 Svyatoslav Ryhel
2025-10-01  4:02   ` Mikko Perttunen
2025-09-25 15:16 ` [PATCH v3 02/22] dt-bindings: clock: tegra30: Add IDs for CSI pad clocks Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 03/22] clk: tegra30: add CSI pad clock gates Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 04/22] dt-bindings: display: tegra: document Tegra30 VI and VIP Svyatoslav Ryhel
2025-10-02  1:19   ` Rob Herring (Arm)
2025-09-25 15:16 ` [PATCH v3 05/22] staging: media: tegra-video: expand VI and VIP support to Tegra30 Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 06/22] staging: media: tegra-video: vi: adjust get_selection op check Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 07/22] staging: media: tegra-video: vi: add flip controls only if no source controls are provided Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 08/22] staging: media: tegra-video: csi: move CSI helpers to header Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 09/22] gpu: host1x: convert MIPI to use operation function pointers Svyatoslav Ryhel
2025-10-01  4:18   ` Mikko Perttunen
2025-09-25 15:16 ` [PATCH v3 10/22] staging: media: tegra-video: vi: improve logic of source requesting Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 11/22] staging: media: tegra-video: csi: move avdd-dsi-csi-supply from VI to CSI Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 12/22] arm64: tegra: move avdd-dsi-csi-supply into CSI node Svyatoslav Ryhel
2025-10-01  4:27   ` Mikko Perttunen
2025-09-25 15:16 ` [PATCH v3 13/22] staging: media: tegra-video: tegra20: set correct maximum width and height Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 14/22] staging: media: tegra-video: tegra20: add support for second output of VI Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 15/22] staging: media: tegra-video: tegra20: simplify format align calculations Svyatoslav Ryhel
2025-10-01  4:38   ` Mikko Perttunen
2025-10-01  5:07     ` Svyatoslav Ryhel
2025-10-01  5:35       ` Svyatoslav Ryhel
2025-10-01  7:51         ` Mikko Perttunen
2025-10-01  7:59           ` Svyatoslav Ryhel
2025-10-02  4:00             ` Mikko Perttunen
2025-10-02  5:41               ` Svyatoslav Ryhel
2025-10-02  6:12                 ` Mikko Perttunen
2025-10-02  6:20                   ` Svyatoslav Ryhel
2025-10-06 18:54                     ` Luca Ceresoli
2025-10-07 16:02                       ` Svyatoslav Ryhel
2025-10-07 19:37                         ` Luca Ceresoli [this message]
2025-10-08  5:44                           ` Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 16/22] staging: media: tegra-video: tegra20: set VI HW revision Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 17/22] staging: media: tegra-video: tegra20: increase maximum VI clock frequency Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 18/22] staging: media: tegra-video: tegra20: expand format support with RAW8/10 and YUV422 1X16 Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 19/22] staging: media: tegra-video: tegra20: adjust luma buffer stride Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 20/22] dt-bindings: display: tegra: document Tegra20 and Tegra30 CSI Svyatoslav Ryhel
2025-10-02  1:52   ` Rob Herring
2025-10-02  5:14     ` Svyatoslav Ryhel
2025-10-06 20:31       ` Rob Herring
2025-10-07  5:13         ` Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 21/22] ARM: tegra: add CSI nodes for Tegra20 and Tegra30 Svyatoslav Ryhel
2025-09-25 15:16 ` [PATCH v3 22/22] staging: media: tegra-video: add CSI support " Svyatoslav Ryhel
2025-10-01  5:04   ` Mikko Perttunen
2025-10-01  5:15     ` Svyatoslav Ryhel
2025-10-01  6:38       ` Mikko Perttunen
2025-10-01 15:23         ` Svyatoslav Ryhel
2025-10-02  4:03           ` Mikko Perttunen
2025-10-02 17:49     ` Svyatoslav Ryhel

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=DDCCDQMTQG55.1K25Y3U0JE15Q@bootlin.com \
    --to=luca.ceresoli@bootlin.com \
    --cc=airlied@gmail.com \
    --cc=arnd@arndb.de \
    --cc=charan.pedumuru@gmail.com \
    --cc=clamor95@gmail.com \
    --cc=conor+dt@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=digetx@gmail.com \
    --cc=diogo.ivo@tecnico.ulisboa.pt \
    --cc=dri-devel@lists.freedesktop.org \
    --cc=gregkh@linuxfoundation.org \
    --cc=jonasschwoebel@yahoo.de \
    --cc=jonathanh@nvidia.com \
    --cc=krzk+dt@kernel.org \
    --cc=linus.walleij@linaro.org \
    --cc=linux-clk@vger.kernel.org \
    --cc=linux-gpio@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-media@vger.kernel.org \
    --cc=linux-staging@lists.linux.dev \
    --cc=linux-tegra@vger.kernel.org \
    --cc=maarten.lankhorst@linux.intel.com \
    --cc=mchehab@kernel.org \
    --cc=mperttunen@nvidia.com \
    --cc=mripard@kernel.org \
    --cc=mturquette@baylibre.com \
    --cc=pgaikwad@nvidia.com \
    --cc=robh@kernel.org \
    --cc=sboyd@kernel.org \
    --cc=simona@ffwll.ch \
    --cc=skomatineni@nvidia.com \
    --cc=thierry.reding@gmail.com \
    --cc=tzimmermann@suse.de \
    --cc=webgeek1234@gmail.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).