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[144.178.202.139]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-63a5c134062sm18799571a12.36.2025.10.17.07.05.49 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 17 Oct 2025 07:05:49 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Fri, 17 Oct 2025 16:05:48 +0200 Message-Id: Cc: "Bjorn Andersson" , "Rob Herring" , "Krzysztof Kozlowski" , "Jagadeesh Kona" , "Bryan O'Donoghue" , "Michael Turquette" , "Stephen Boyd" , "Conor Dooley" , , , Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8550: Additionally manage MXC power domain in camcc From: "Luca Weiss" To: "Taniya Das" , "Luca Weiss" , "Dmitry Baryshkov" , "Vladimir Zapolskiy" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20250303225521.1780611-1-vladimir.zapolskiy@linaro.org> <20250303225521.1780611-3-vladimir.zapolskiy@linaro.org> <3210a484-b9c3-4399-bee1-9f5bbc90034c@linaro.org> In-Reply-To: Hi Taniya, On Thu Mar 13, 2025 at 12:57 PM CET, Taniya Das wrote: > > > On 3/13/2025 1:22 PM, Luca Weiss wrote: >> Hi Taniya, >>=20 >> On Thu Mar 13, 2025 at 5:39 AM CET, Taniya Das wrote: >>> >>> >>> On 3/4/2025 2:10 PM, Dmitry Baryshkov wrote: >>>> On Tue, 4 Mar 2025 at 09:37, Vladimir Zapolskiy >>>> wrote: >>>>> >>>>> On 3/4/25 01:53, Dmitry Baryshkov wrote: >>>>>> On Tue, Mar 04, 2025 at 12:55:21AM +0200, Vladimir Zapolskiy wrote: >>>>>>> SM8550 Camera Clock Controller shall enable both MXC and MMCX power >>>>>>> domains. >>>>>> >>>>>> Are those really required to access the registers of the cammcc? Or = is >>>>>> one of those (MXC?) required to setup PLLs? Also, is this applicable >>>>>> only to sm8550 or to other similar clock controllers? >>>>> >>>>> Due to the described problem I experience a fatal CPU stall on SM8550= -QRD, >>>>> not on any SM8450 or SM8650 powered board for instance, however it do= es >>>>> not exclude an option that the problem has to be fixed for other cloc= k >>>>> controllers, but it's Qualcomm to confirm any other touched platforms= , >>>> >>>> Please work with Taniya to identify used power domains. >>>> >>> >>> CAMCC requires both MMCX and MXC to be functional. >>=20 >> Could you check whether any clock controllers on SM6350/SM7225 (Bitra) >> need multiple power domains, or in general which clock controller uses >> which power domain. >>=20 >> That SoC has camcc, dispcc, gcc, gpucc, npucc and videocc. >>=20 >> That'd be highly appreciated since I've been hitting weird issues there >> that could be explained by some missing power domains. >>=20 > > Hi Luca, > > The targets you mentioned does not have any have multiple rail > dependency, but could you share the weird issues with respect to clock > controller I can take a look. Coming back to this, I've taken a shot at camera on SM6350 (Fairphone 4) again, but again hitting some clock issues. For reference, I am testing with following change: https://lore.kernel.org/linux-arm-msm/20250911011218.861322-3-vladimir.zapo= lskiy@linaro.org/ Trying to enable CAMCC_MCLK1_CLK - wired up to the IMX576 camera sensor on this phone - results in following error. [ 3.140232] ------------[ cut here ]------------ [ 3.141264] camcc_mclk1_clk status stuck at 'off' [ 3.141276] WARNING: CPU: 6 PID: 12 at drivers/clk/qcom/clk-branch.c:87 = clk_branch_toggle+0x170/0x190 Checking the driver against downstream driver, it looks like the RCGs should be using clk_rcg2_shared_ops because of enable_safe_config in downstream, but changing that doesn't really improve the situation, but it does change the error message to this: [ 2.933254] ------------[ cut here ]------------ [ 2.933961] camcc_mclk1_clk_src: rcg didn't update its configuration. [ 2.933970] WARNING: CPU: 7 PID: 12 at drivers/clk/qcom/clk-rcg2.c:136 u= pdate_config+0xd4/0xe4 I've also noticed that some camcc drivers take in GCC_CAMERA_AHB_CLK as iface clk, could something like this be missing on sm6350? I'd appreciate any help or tips for resolving this. Regards Luca > >> Regards >> Luca >>=20 >>> >>>>> for instance x1e80100-camcc has it resolved right at the beginning. >>>>> >>>>> To my understanding here 'required-opps' shall also be generalized, s= o >>>>> the done copy from x1e80100-camcc was improper, and the latter dt-bin= ding >>>>> should be fixed. >>>> >>>> Yes >>>> >>> >>> required-opps is not mandatory for MXC as we ensure that MxC would neve= r >>> hit retention. >>> >>> https://lore.kernel.org/r/20240625-avoid_mxc_retention-v2-1-af9c2f549a5= f@quicinc.com >>> >>> >>>> >>>> >>=20