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[2001:1c00:3b8a:ea00:4b34:6694:d9bd:5210]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-b65eb035bafsm1045122866b.42.2025.10.21.03.07.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 21 Oct 2025 03:07:20 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 21 Oct 2025 12:07:19 +0200 Message-Id: To: "Bryan O'Donoghue" , "Konrad Dybcio" , "Luca Weiss" , "Taniya Das" , "Dmitry Baryshkov" , "Vladimir Zapolskiy" Cc: "Bjorn Andersson" , "Rob Herring" , "Krzysztof Kozlowski" , "Jagadeesh Kona" , "Michael Turquette" , "Stephen Boyd" , "Conor Dooley" , , , Subject: Re: [PATCH 2/2] arm64: dts: qcom: sm8550: Additionally manage MXC power domain in camcc From: "Luca Weiss" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20250303225521.1780611-1-vladimir.zapolskiy@linaro.org> <20250303225521.1780611-3-vladimir.zapolskiy@linaro.org> <3210a484-b9c3-4399-bee1-9f5bbc90034c@linaro.org> <85bf3468-24bf-4f14-afcd-28878ad84dc9@oss.qualcomm.com> In-Reply-To: On Mon Oct 20, 2025 at 3:00 PM CEST, Bryan O'Donoghue wrote: > On 20/10/2025 13:21, Konrad Dybcio wrote: >> On 10/17/25 4:05 PM, Luca Weiss wrote: >>> Hi Taniya, >>> >>> On Thu Mar 13, 2025 at 12:57 PM CET, Taniya Das wrote: >>>> >>>> >>>> On 3/13/2025 1:22 PM, Luca Weiss wrote: >>>>> Hi Taniya, >>>>> >>>>> On Thu Mar 13, 2025 at 5:39 AM CET, Taniya Das wrote: >>>>>> >>>>>> >>>>>> On 3/4/2025 2:10 PM, Dmitry Baryshkov wrote: >>>>>>> On Tue, 4 Mar 2025 at 09:37, Vladimir Zapolskiy >>>>>>> wrote: >>>>>>>> >>>>>>>> On 3/4/25 01:53, Dmitry Baryshkov wrote: >>>>>>>>> On Tue, Mar 04, 2025 at 12:55:21AM +0200, Vladimir Zapolskiy wrot= e: >>>>>>>>>> SM8550 Camera Clock Controller shall enable both MXC and MMCX po= wer >>>>>>>>>> domains. >>>>>>>>> >>>>>>>>> Are those really required to access the registers of the cammcc? = Or is >>>>>>>>> one of those (MXC?) required to setup PLLs? Also, is this applica= ble >>>>>>>>> only to sm8550 or to other similar clock controllers? >>>>>>>> >>>>>>>> Due to the described problem I experience a fatal CPU stall on SM8= 550-QRD, >>>>>>>> not on any SM8450 or SM8650 powered board for instance, however it= does >>>>>>>> not exclude an option that the problem has to be fixed for other c= lock >>>>>>>> controllers, but it's Qualcomm to confirm any other touched platfo= rms, >>>>>>> >>>>>>> Please work with Taniya to identify used power domains. >>>>>>> >>>>>> >>>>>> CAMCC requires both MMCX and MXC to be functional. >>>>> >>>>> Could you check whether any clock controllers on SM6350/SM7225 (Bitra= ) >>>>> need multiple power domains, or in general which clock controller use= s >>>>> which power domain. >>>>> >>>>> That SoC has camcc, dispcc, gcc, gpucc, npucc and videocc. >>>>> >>>>> That'd be highly appreciated since I've been hitting weird issues the= re >>>>> that could be explained by some missing power domains. >>>>> >>>> >>>> Hi Luca, >>>> >>>> The targets you mentioned does not have any have multiple rail >>>> dependency, but could you share the weird issues with respect to clock >>>> controller I can take a look. >>> >>> Coming back to this, I've taken a shot at camera on SM6350 (Fairphone 4= ) >>> again, but again hitting some clock issues. >>> >>> For reference, I am testing with following change: >>> https://lore.kernel.org/linux-arm-msm/20250911011218.861322-3-vladimir.= zapolskiy@linaro.org/ >>> >>> Trying to enable CAMCC_MCLK1_CLK - wired up to the IMX576 camera sensor >>> on this phone - results in following error. >>> >>> [ 3.140232] ------------[ cut here ]------------ >>> [ 3.141264] camcc_mclk1_clk status stuck at 'off' >>> [ 3.141276] WARNING: CPU: 6 PID: 12 at drivers/clk/qcom/clk-branch.c= :87 clk_branch_toggle+0x170/0x190 >>> >>> Checking the driver against downstream driver, it looks like the RCGs >>> should be using clk_rcg2_shared_ops because of enable_safe_config in >>> downstream, but changing that doesn't really improve the situation, but >>> it does change the error message to this: >>> >>> [ 2.933254] ------------[ cut here ]------------ >>> [ 2.933961] camcc_mclk1_clk_src: rcg didn't update its configuration= . >>> [ 2.933970] WARNING: CPU: 7 PID: 12 at drivers/clk/qcom/clk-rcg2.c:1= 36 update_config+0xd4/0xe4 >>> >>> I've also noticed that some camcc drivers take in GCC_CAMERA_AHB_CLK as >>> iface clk, could something like this be missing on sm6350? >>> >>> I'd appreciate any help or tips for resolving this. >>=20 >> Is CAMCC_PLL2 online? >>=20 >> Konrad > > Usually if you can't switch on a clock its because a power-domain is off= =20 > or a GDSC is off. > > I'd guess one of the power-domains is missing. > > Looks... > > @Luca Is this actually right ? > > camcc: clock-controller@ad00000 { > compatible =3D "qcom,sm6350-camcc"; > reg =3D <0x0 0x0ad00000 0x0 0x16000>; > clocks =3D <&rpmhcc RPMH_CXO_CLK>; > #clock-cells =3D <1>; > #reset-cells =3D <1>; > #power-domain-cells =3D <1>; > }; > > Isn't this clock controller missing at least one power-domain ? > > camcc: clock-controller@ad00000 { > compatible =3D "qcom,sm6350-camcc"; > reg =3D <0x0 0x0ad00000 0x0 0x16000>; > clocks =3D <&rpmhcc RPMH_CXO_CLK>; > + power-domains =3D <&rpmhpd SM6350_CX>; > #clock-cells =3D <1>; > #reset-cells =3D <1>; > #power-domain-cells =3D <1>; > }; > > Hmm but CX should already be on realistically.. Downstream does reference both CX and MX in the camcc-lagoon.c driver static DEFINE_VDD_REGULATORS(vdd_cx, VDD_NUM, 1, vdd_corner); static DEFINE_VDD_REGULATORS(vdd_mx, VDD_NUM, 1, vdd_corner); I'd expect both to be enabled at boot though, CX and MX is at least both used for display (which is already on from bootloader). Also adding "power-domains =3D <&rpmhpd SM6350_MX>;" to camcc unsurprisingly doesn't change anything. Regards Luca > > --- > bod