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Tue, 02 Dec 2025 08:53:02 -0800 (PST) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 02 Dec 2025 11:52:59 -0500 Message-Id: To: "David Lechner" , "Kurt Borja" , "Jonathan Cameron" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Tobias Sperling" Cc: =?utf-8?q?Nuno_S=C3=A1?= , "Andy Shevchenko" , , , , "Jonathan Cameron" Subject: Re: [PATCH v3 2/2] iio: adc: Add ti-ads1018 driver From: "Kurt Borja" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20251128-ads1x18-v3-0-a6ebab815b2d@gmail.com> <20251128-ads1x18-v3-2-a6ebab815b2d@gmail.com> In-Reply-To: On Mon Dec 1, 2025 at 6:09 PM -05, David Lechner wrote: ... >> +static int ads1018_buffer_preenable(struct iio_dev *indio_dev) >> +{ >> + struct ads1018 *ads1018 =3D iio_priv(indio_dev); >> + const struct ads1018_chip_info *chip_info =3D ads1018->chip_info; >> + unsigned int pga, drate, addr; >> + u16 cfg; >> + >> + addr =3D find_first_bit(indio_dev->active_scan_mask, iio_get_masklengt= h(indio_dev)); >> + pga =3D ads1018_get_pga_mode(ads1018, addr); >> + drate =3D ads1018_get_data_rate_mode(ads1018, addr); >> + >> + cfg =3D ADS1018_CFG_VALID; >> + cfg |=3D FIELD_PREP(ADS1018_CFG_MUX_MASK, addr); >> + cfg |=3D FIELD_PREP(ADS1018_CFG_PGA_MASK, pga); >> + cfg |=3D FIELD_PREP(ADS1018_CFG_MODE_MASK, ADS1018_MODE_CONTINUOUS); >> + cfg |=3D FIELD_PREP(ADS1018_CFG_DRATE_MASK, drate); >> + >> + if (chip_info->channels[addr].type =3D=3D IIO_TEMP) >> + cfg |=3D ADS1018_CFG_TS_MODE_EN; >> + >> + ads1018->tx_buf[0] =3D cpu_to_be16(cfg); >> + ads1018->tx_buf[1] =3D 0; > > Seems like we could use 16-bit cycles here too? > Just realized, we can't use it here because we would need a CS de-assert in between (16-bit) words and also keep it asserted after that for drdy IRQ. The 32-bit cycle simplifies things a lot in buffer mode. --=20 ~ Kurt