[PATCH 0/5] Enable Bluetooth and WiFi on Fairphone (Gen. 6)

[PATCH 0/5] Enable Bluetooth and WiFi on Fairphone (Gen. 6)

[Luca Weiss]

Add the required bits to enable Bluetooth and WiFi on the Milos
SoC-based Fairphone (Gen. 6) smartphone.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
Luca Weiss (5):
      soc: qcom: pd-mapper: Add Milos compatible
      arm64: dts: qcom: milos: Split up uart11 pinctrl
      arm64: dts: qcom: milos: Add WCN6750 WiFi node
      arm64: dts: qcom: milos-fairphone-fp6: Enable Bluetooth
      arm64: dts: qcom: milos-fairphone-fp6: Enable WiFi

 arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 191 +++++++++++++++++++++++
 arch/arm64/boot/dts/qcom/milos.dtsi              |  72 +++++++--
 drivers/soc/qcom/qcom_pd_mapper.c                |   1 +
 3 files changed, 253 insertions(+), 11 deletions(-)
---
base-commit: ef1c7b875741bef0ff37ae8ab8a9aaf407dc141c
change-id: 20260116-milos-fp6-bt-wifi-22faa7b15e8c

Best regards,
-- 
Luca Weiss <luca.weiss@fairphone.com>

[PATCH 1/5] soc: qcom: pd-mapper: Add Milos compatible

[Luca Weiss]

Add support for the Qualcomm Milos SoC to the protection domain mapper.
Milos shares the same protection domain configuration as SM8550, so
reuse the existing SM8550 domain data.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
 drivers/soc/qcom/qcom_pd_mapper.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/soc/qcom/qcom_pd_mapper.c b/drivers/soc/qcom/qcom_pd_mapper.c
index 1bcbe69688d2..e6f525813b32 100644
--- a/drivers/soc/qcom/qcom_pd_mapper.c
+++ b/drivers/soc/qcom/qcom_pd_mapper.c
@@ -562,6 +562,7 @@ static const struct of_device_id qcom_pdm_domains[] __maybe_unused = {
 	{ .compatible = "qcom,apq8084", .data = NULL, },
 	{ .compatible = "qcom,apq8096", .data = msm8996_domains, },
 	{ .compatible = "qcom,kaanapali", .data = kaanapali_domains, },
+	{ .compatible = "qcom,milos", .data = sm8550_domains, },
 	{ .compatible = "qcom,msm8226", .data = NULL, },
 	{ .compatible = "qcom,msm8909", .data = NULL, },
 	{ .compatible = "qcom,msm8916", .data = NULL, },

-- 
2.52.0

Re: [PATCH 1/5] soc: qcom: pd-mapper: Add Milos compatible

[Dmitry Baryshkov]

On Fri, Jan 16, 2026 at 03:50:47PM +0100, Luca Weiss wrote:
> Add support for the Qualcomm Milos SoC to the protection domain mapper.
> Milos shares the same protection domain configuration as SM8550, so
> reuse the existing SM8550 domain data.
> 
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
>  drivers/soc/qcom/qcom_pd_mapper.c | 1 +
>  1 file changed, 1 insertion(+)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


-- 
With best wishes
Dmitry

[PATCH 2/5] arm64: dts: qcom: milos: Split up uart11 pinctrl

[Luca Weiss]

In order to set the pinctrl for the individual CTS, RTS, TX and RX pins,
split up the pinctrl configuration into 4 nodes so that boards can set
some properties separately.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
 arch/arm64/boot/dts/qcom/milos.dtsi | 26 +++++++++++++++-----------
 1 file changed, 15 insertions(+), 11 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index 0f69deabb60c..024e1c9992fe 100644
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -915,7 +915,7 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
 				interconnect-names = "qup-core",
 						     "qup-config";
 
-				pinctrl-0 = <&qup_uart11_default>, <&qup_uart11_cts_rts>;
+				pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
 				pinctrl-names = "default";
 
 				status = "disabled";
@@ -1835,20 +1835,24 @@ qup_uart5_default: qup-uart5-default-state {
 				bias-disable;
 			};
 
-			qup_uart11_default: qup-uart11-default-state {
-				/* TX, RX */
-				pins = "gpio50", "gpio51";
+			qup_uart11_cts: qup-uart11-cts-state {
+				pins = "gpio48";
 				function = "qup1_se4";
-				drive-strength = <2>;
-				bias-pull-up;
 			};
 
-			qup_uart11_cts_rts: qup-uart11-cts-rts-state {
-				/* CTS, RTS */
-				pins = "gpio48", "gpio49";
+			qup_uart11_rts: qup-uart11-rts-state {
+				pins = "gpio49";
+				function = "qup1_se4";
+			};
+
+			qup_uart11_tx: qup-uart11-tx-state {
+				pins = "gpio50";
+				function = "qup1_se4";
+			};
+
+			qup_uart11_rx: qup-uart11-rx-state {
+				pins = "gpio51";
 				function = "qup1_se4";
-				drive-strength = <2>;
-				bias-pull-down;
 			};
 
 			sdc2_default: sdc2-default-state {

-- 
2.52.0

Re: [PATCH 2/5] arm64: dts: qcom: milos: Split up uart11 pinctrl

[Konrad Dybcio]

On 1/16/26 3:50 PM, Luca Weiss wrote:
> In order to set the pinctrl for the individual CTS, RTS, TX and RX pins,
> split up the pinctrl configuration into 4 nodes so that boards can set
> some properties separately.
> 
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
>  arch/arm64/boot/dts/qcom/milos.dtsi | 26 +++++++++++++++-----------
>  1 file changed, 15 insertions(+), 11 deletions(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
> index 0f69deabb60c..024e1c9992fe 100644
> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
> @@ -915,7 +915,7 @@ &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>,
>  				interconnect-names = "qup-core",
>  						     "qup-config";
>  
> -				pinctrl-0 = <&qup_uart11_default>, <&qup_uart11_cts_rts>;
> +				pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>;
>  				pinctrl-names = "default";
>  
>  				status = "disabled";
> @@ -1835,20 +1835,24 @@ qup_uart5_default: qup-uart5-default-state {
>  				bias-disable;
>  			};
>  
> -			qup_uart11_default: qup-uart11-default-state {
> -				/* TX, RX */
> -				pins = "gpio50", "gpio51";
> +			qup_uart11_cts: qup-uart11-cts-state {
> +				pins = "gpio48";
>  				function = "qup1_se4";
> -				drive-strength = <2>;
> -				bias-pull-up;
>  			};

I think the best setup is

qup_uart11_default: foo-state {
	qup_uart11_tx: bar-pins {
		...
	};
};

qup_uart11_cts_rts: foo-state {
	qup_uart11_rts: bar-pins {
		...
	};
};

Since  there's a lower amount of references at the user (default vs
cts/rts still makes sense as that's a wiring difference) but we still
keep a label for customizing the properties

Konrad

[PATCH 3/5] arm64: dts: qcom: milos: Add WCN6750 WiFi node

[Luca Weiss]

Add a node for the WCN6750 WiFi found with the Milos SoC.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
 arch/arm64/boot/dts/qcom/milos.dtsi | 46 +++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index 024e1c9992fe..80feb3e9d3e2 100644
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -2043,6 +2043,52 @@ gic_its: msi-controller@17140000 {
 			};
 		};
 
+		wifi: wifi@17110040 {
+			compatible = "qcom,wcn6750-wifi";
+			reg = <0x0 0x17110040 0x0 0x0>;
+
+			iommus = <&apps_smmu 0x1400 0x1>;
+
+			interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 769 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 770 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 771 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 772 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 773 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 774 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 775 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 776 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 777 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 778 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 779 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 780 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 781 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 782 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 783 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 784 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 785 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 786 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 787 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 788 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 789 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 790 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 791 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 792 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 793 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 794 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 795 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 796 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 797 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 798 IRQ_TYPE_EDGE_RISING 0>,
+				     <GIC_SPI 799 IRQ_TYPE_EDGE_RISING 0>;
+
+			qcom,rproc = <&remoteproc_wpss>;
+			qcom,smem-states = <&smp2p_wlan_out 0>;
+			qcom,smem-state-names = "wlan-smp2p-out";
+
+			status = "disabled";
+		};
+
 		timer@17420000 {
 			compatible = "arm,armv7-timer-mem";
 			reg = <0x0 0x17420000 0x0 0x1000>;

-- 
2.52.0

Re: [PATCH 3/5] arm64: dts: qcom: milos: Add WCN6750 WiFi node

[Dmitry Baryshkov]

On Fri, Jan 16, 2026 at 03:50:49PM +0100, Luca Weiss wrote:
> Add a node for the WCN6750 WiFi found with the Milos SoC.
> 
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
>  arch/arm64/boot/dts/qcom/milos.dtsi | 46 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 46 insertions(+)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


-- 
With best wishes
Dmitry

Re: [PATCH 3/5] arm64: dts: qcom: milos: Add WCN6750 WiFi node

[Konrad Dybcio]

On 1/16/26 3:50 PM, Luca Weiss wrote:
> Add a node for the WCN6750 WiFi found with the Milos SoC.
> 
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
>  arch/arm64/boot/dts/qcom/milos.dtsi | 46 +++++++++++++++++++++++++++++++++++++
>  1 file changed, 46 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
> index 024e1c9992fe..80feb3e9d3e2 100644
> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
> @@ -2043,6 +2043,52 @@ gic_its: msi-controller@17140000 {
>  			};
>  		};
>  
> +		wifi: wifi@17110040 {
> +			compatible = "qcom,wcn6750-wifi";
> +			reg = <0x0 0x17110040 0x0 0x0>;

This reg doesn't.. sound.. very.. good..

The size being 0 is of course wrong, but perhaps more interestingly
the base address is a register within the GIC..

> +			iommus = <&apps_smmu 0x1400 0x1>;

And this is a PCIe stream

But I see kodiak has the exact same setup..

After digging a little into the driver, that 'reg' is apparently
indeed consumed, as a base for PCI MSIs.. I feel like there should be
some better way to express this.. non-everyday setup

There's this commit message:

commit 00fd24089b8154ddf5b3e724e2c4c9974b9ba91e
Author: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
Date:   Fri Apr 29 22:34:54 2022 +0530

    dt: bindings: net: add bindings of WCN6750 for ath11k
    
    WCN6750 is the WLAN chip on Qualcomm Snapdragon SoC SC7280;
    Though being a PCIe based solution, it is not attached to
    the APSS processor (Application Processor SubSystem), it is
    instead attached to another tiny processor called WPSS Q6
    processor (Wireless Processor SubSystem) on the SC7280 MSM,
    where the WLAN firmware runs, and it is the WLAN firmware
    running on the Q6 processor which enumerates WCN6750, as a
    result APPS processor would never know such a device being
    present in the system and would not detect the WCN6750
    hardware unless and otherwise WCN6750 is registered as a
    platform device. This is the reason behind adding WCN6750
    WLAN node in the device tree.
    
    Add WCN6750 wireless driver support, its based on ath11k driver.

Sorry to hijack this patch, but I am not comfortable with this binding
as-is..

Adding +Jeff in case he has any thoughts

Konrad

Re: [PATCH 3/5] arm64: dts: qcom: milos: Add WCN6750 WiFi node

[Luca Weiss]

Hi Konrad,

On Tue Jan 20, 2026 at 3:39 PM CET, Konrad Dybcio wrote:
> On 1/16/26 3:50 PM, Luca Weiss wrote:
>> Add a node for the WCN6750 WiFi found with the Milos SoC.
>> 
>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>> ---
>>  arch/arm64/boot/dts/qcom/milos.dtsi | 46 +++++++++++++++++++++++++++++++++++++
>>  1 file changed, 46 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
>> index 024e1c9992fe..80feb3e9d3e2 100644
>> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
>> @@ -2043,6 +2043,52 @@ gic_its: msi-controller@17140000 {
>>  			};
>>  		};
>>  
>> +		wifi: wifi@17110040 {
>> +			compatible = "qcom,wcn6750-wifi";
>> +			reg = <0x0 0x17110040 0x0 0x0>;
>
> This reg doesn't.. sound.. very.. good..
>
> The size being 0 is of course wrong, but perhaps more interestingly
> the base address is a register within the GIC..
>
>> +			iommus = <&apps_smmu 0x1400 0x1>;
>
> And this is a PCIe stream
>
> But I see kodiak has the exact same setup..
>
> After digging a little into the driver, that 'reg' is apparently
> indeed consumed, as a base for PCI MSIs.. I feel like there should be
> some better way to express this.. non-everyday setup
>
> There's this commit message:
>
> commit 00fd24089b8154ddf5b3e724e2c4c9974b9ba91e
> Author: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
> Date:   Fri Apr 29 22:34:54 2022 +0530
>
>     dt: bindings: net: add bindings of WCN6750 for ath11k
>     
>     WCN6750 is the WLAN chip on Qualcomm Snapdragon SoC SC7280;
>     Though being a PCIe based solution, it is not attached to
>     the APSS processor (Application Processor SubSystem), it is
>     instead attached to another tiny processor called WPSS Q6
>     processor (Wireless Processor SubSystem) on the SC7280 MSM,
>     where the WLAN firmware runs, and it is the WLAN firmware
>     running on the Q6 processor which enumerates WCN6750, as a
>     result APPS processor would never know such a device being
>     present in the system and would not detect the WCN6750
>     hardware unless and otherwise WCN6750 is registered as a
>     platform device. This is the reason behind adding WCN6750
>     WLAN node in the device tree.
>     
>     Add WCN6750 wireless driver support, its based on ath11k driver.
>
> Sorry to hijack this patch, but I am not comfortable with this binding
> as-is..
>
> Adding +Jeff in case he has any thoughts

To be honest I find it a bit discouraging to get this relatively simple
patch with existing bindings blocked. Yes, the bindings are probably bad
(not that I can really judge) but sc7280/kodiak already uses them and
it's functional, so I don't know what I would need to change.

Re-designing the bindings and driver seems a bit overkill to get milos
wifi upstream.

Regards
Luca

Re: [PATCH 3/5] arm64: dts: qcom: milos: Add WCN6750 WiFi node

[Konrad Dybcio]

On 2/13/26 2:42 PM, Luca Weiss wrote:
> Hi Konrad,
> 
> On Tue Jan 20, 2026 at 3:39 PM CET, Konrad Dybcio wrote:
>> On 1/16/26 3:50 PM, Luca Weiss wrote:
>>> Add a node for the WCN6750 WiFi found with the Milos SoC.
>>>
>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>> ---
>>>  arch/arm64/boot/dts/qcom/milos.dtsi | 46 +++++++++++++++++++++++++++++++++++++
>>>  1 file changed, 46 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
>>> index 024e1c9992fe..80feb3e9d3e2 100644
>>> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
>>> @@ -2043,6 +2043,52 @@ gic_its: msi-controller@17140000 {
>>>  			};
>>>  		};
>>>  
>>> +		wifi: wifi@17110040 {
>>> +			compatible = "qcom,wcn6750-wifi";
>>> +			reg = <0x0 0x17110040 0x0 0x0>;
>>
>> This reg doesn't.. sound.. very.. good..
>>
>> The size being 0 is of course wrong, but perhaps more interestingly
>> the base address is a register within the GIC..
>>
>>> +			iommus = <&apps_smmu 0x1400 0x1>;
>>
>> And this is a PCIe stream
>>
>> But I see kodiak has the exact same setup..
>>
>> After digging a little into the driver, that 'reg' is apparently
>> indeed consumed, as a base for PCI MSIs.. I feel like there should be
>> some better way to express this.. non-everyday setup
>>
>> There's this commit message:
>>
>> commit 00fd24089b8154ddf5b3e724e2c4c9974b9ba91e
>> Author: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
>> Date:   Fri Apr 29 22:34:54 2022 +0530
>>
>>     dt: bindings: net: add bindings of WCN6750 for ath11k
>>     
>>     WCN6750 is the WLAN chip on Qualcomm Snapdragon SoC SC7280;
>>     Though being a PCIe based solution, it is not attached to
>>     the APSS processor (Application Processor SubSystem), it is
>>     instead attached to another tiny processor called WPSS Q6
>>     processor (Wireless Processor SubSystem) on the SC7280 MSM,
>>     where the WLAN firmware runs, and it is the WLAN firmware
>>     running on the Q6 processor which enumerates WCN6750, as a
>>     result APPS processor would never know such a device being
>>     present in the system and would not detect the WCN6750
>>     hardware unless and otherwise WCN6750 is registered as a
>>     platform device. This is the reason behind adding WCN6750
>>     WLAN node in the device tree.
>>     
>>     Add WCN6750 wireless driver support, its based on ath11k driver.
>>
>> Sorry to hijack this patch, but I am not comfortable with this binding
>> as-is..
>>
>> Adding +Jeff in case he has any thoughts
> 
> To be honest I find it a bit discouraging to get this relatively simple
> patch with existing bindings blocked. Yes, the bindings are probably bad
> (not that I can really judge) but sc7280/kodiak already uses them and
> it's functional, so I don't know what I would need to change.
> 
> Re-designing the bindings and driver seems a bit overkill to get milos
> wifi upstream.

I was *really* hoping this would attract more attention from the Atheros
folks, but that seems not to have happened..

With that in mind, I think the way to go for now is to go forward with
this is to simply roll with it, especially given we need to carry this
setup for kodiak regardless.

Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad

Re: [PATCH 3/5] arm64: dts: qcom: milos: Add WCN6750 WiFi node

[Dmitry Baryshkov]

On Tue, Jan 20, 2026 at 03:39:44PM +0100, Konrad Dybcio wrote:
> On 1/16/26 3:50 PM, Luca Weiss wrote:
> > Add a node for the WCN6750 WiFi found with the Milos SoC.
> > 
> > Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> > ---
> >  arch/arm64/boot/dts/qcom/milos.dtsi | 46 +++++++++++++++++++++++++++++++++++++
> >  1 file changed, 46 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
> > index 024e1c9992fe..80feb3e9d3e2 100644
> > --- a/arch/arm64/boot/dts/qcom/milos.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
> > @@ -2043,6 +2043,52 @@ gic_its: msi-controller@17140000 {
> >  			};
> >  		};
> >  
> > +		wifi: wifi@17110040 {
> > +			compatible = "qcom,wcn6750-wifi";
> > +			reg = <0x0 0x17110040 0x0 0x0>;
> 
> This reg doesn't.. sound.. very.. good..
> 
> The size being 0 is of course wrong, but perhaps more interestingly
> the base address is a register within the GIC..
> 
> > +			iommus = <&apps_smmu 0x1400 0x1>;
> 
> And this is a PCIe stream
> 
> But I see kodiak has the exact same setup..
> 
> After digging a little into the driver, that 'reg' is apparently
> indeed consumed, as a base for PCI MSIs.. I feel like there should be
> some better way to express this.. non-everyday setup

I wonder, why are we using it directly instead of relying on GIC? I
guess it is because we need to map MSI registers over the PCIe IOMMU and
then let the other side write to them. How is it being handled in the
normal PCIe case?

> 
> There's this commit message:
> 
> commit 00fd24089b8154ddf5b3e724e2c4c9974b9ba91e
> Author: Manikanta Pubbisetty <quic_mpubbise@quicinc.com>
> Date:   Fri Apr 29 22:34:54 2022 +0530
> 
>     dt: bindings: net: add bindings of WCN6750 for ath11k
>     
>     WCN6750 is the WLAN chip on Qualcomm Snapdragon SoC SC7280;
>     Though being a PCIe based solution, it is not attached to
>     the APSS processor (Application Processor SubSystem), it is
>     instead attached to another tiny processor called WPSS Q6
>     processor (Wireless Processor SubSystem) on the SC7280 MSM,
>     where the WLAN firmware runs, and it is the WLAN firmware
>     running on the Q6 processor which enumerates WCN6750, as a
>     result APPS processor would never know such a device being
>     present in the system and would not detect the WCN6750
>     hardware unless and otherwise WCN6750 is registered as a
>     platform device. This is the reason behind adding WCN6750
>     WLAN node in the device tree.
>     
>     Add WCN6750 wireless driver support, its based on ath11k driver.
> 
> Sorry to hijack this patch, but I am not comfortable with this binding
> as-is..
> 
> Adding +Jeff in case he has any thoughts
> 
> Konrad

-- 
With best wishes
Dmitry

Re: [PATCH 3/5] arm64: dts: qcom: milos: Add WCN6750 WiFi node

[Konrad Dybcio]

On 2/13/26 3:31 PM, Dmitry Baryshkov wrote:
> On Tue, Jan 20, 2026 at 03:39:44PM +0100, Konrad Dybcio wrote:
>> On 1/16/26 3:50 PM, Luca Weiss wrote:
>>> Add a node for the WCN6750 WiFi found with the Milos SoC.
>>>
>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>> ---
>>>  arch/arm64/boot/dts/qcom/milos.dtsi | 46 +++++++++++++++++++++++++++++++++++++
>>>  1 file changed, 46 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
>>> index 024e1c9992fe..80feb3e9d3e2 100644
>>> --- a/arch/arm64/boot/dts/qcom/milos.dtsi
>>> +++ b/arch/arm64/boot/dts/qcom/milos.dtsi
>>> @@ -2043,6 +2043,52 @@ gic_its: msi-controller@17140000 {
>>>  			};
>>>  		};
>>>  
>>> +		wifi: wifi@17110040 {
>>> +			compatible = "qcom,wcn6750-wifi";
>>> +			reg = <0x0 0x17110040 0x0 0x0>;
>>
>> This reg doesn't.. sound.. very.. good..
>>
>> The size being 0 is of course wrong, but perhaps more interestingly
>> the base address is a register within the GIC..
>>
>>> +			iommus = <&apps_smmu 0x1400 0x1>;
>>
>> And this is a PCIe stream
>>
>> But I see kodiak has the exact same setup..
>>
>> After digging a little into the driver, that 'reg' is apparently
>> indeed consumed, as a base for PCI MSIs.. I feel like there should be
>> some better way to express this.. non-everyday setup
> 
> I wonder, why are we using it directly instead of relying on GIC? I
> guess it is because we need to map MSI registers over the PCIe IOMMU and
> then let the other side write to them. How is it being handled in the
> normal PCIe case?

Looking at the recent r3g2 patches with the second switch enabled on
PCIe1, it seems not to be an issue there

Konrad

[PATCH 4/5] arm64: dts: qcom: milos-fairphone-fp6: Enable Bluetooth

[Luca Weiss]

Add the nodes to describe the WCN6755 chip with its PMU and Bluetooth
parts.

Thanks to Alexander Koskovich for helping with the bringup, adding
'clocks' to the PMU node to make Bluetooth work.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
 arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 174 +++++++++++++++++++++++
 1 file changed, 174 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
index 52895dd9e4fa..cbe1507b0aaa 100644
--- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
+++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
@@ -24,6 +24,7 @@ / {
 
 	aliases {
 		serial0 = &uart5;
+		serial1 = &uart11;
 	};
 
 	gpio-keys {
@@ -215,6 +216,67 @@ trip1 {
 			};
 		};
 	};
+
+	wcn6750-pmu {
+		compatible = "qcom,wcn6750-pmu"; /* WCN6755 */
+
+		vddaon-supply = <&vreg_s3b>;
+		vddasd-supply = <&vreg_l7b>;
+		vddpmu-supply = <&vreg_s3b>;
+		vddrfa0p8-supply = <&vreg_s3b>;
+		vddrfa1p2-supply = <&vreg_s2b>;
+		vddrfa1p7-supply = <&vreg_s1b>;
+		vddrfa2p2-supply = <&vreg_s1j>;
+
+		bt-enable-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>;
+
+		clocks = <&rpmhcc RPMH_RF_CLK1>;
+
+		pinctrl-0 = <&bluetooth_enable_default>;
+		pinctrl-names = "default";
+
+		regulators {
+			vreg_pmu_rfa_cmn: ldo0 {
+				regulator-name = "vreg_pmu_rfa_cmn";
+			};
+
+			vreg_pmu_aon_0p59: ldo1 {
+				regulator-name = "vreg_pmu_aon_0p59";
+			};
+
+			vreg_pmu_wlcx_0p8: ldo2 {
+				regulator-name = "vreg_pmu_wlcx_0p8";
+			};
+
+			vreg_pmu_wlmx_0p85: ldo3 {
+				regulator-name = "vreg_pmu_wlmx_0p85";
+			};
+
+			vreg_pmu_btcmx_0p85: ldo4 {
+				regulator-name = "vreg_pmu_btcmx_0p85";
+			};
+
+			vreg_pmu_rfa_0p8: ldo5 {
+				regulator-name = "vreg_pmu_rfa_0p8";
+			};
+
+			vreg_pmu_rfa_1p2: ldo6 {
+				regulator-name = "vreg_pmu_rfa_1p2";
+			};
+
+			vreg_pmu_rfa_1p7: ldo7 {
+				regulator-name = "vreg_pmu_rfa_1p7";
+			};
+
+			vreg_pmu_pcie_0p9: ldo8 {
+				regulator-name = "vreg_pmu_pcie_0p9";
+			};
+
+			vreg_pmu_pcie_1p8: ldo9 {
+				regulator-name = "vreg_pmu_pcie_1p8";
+			};
+		};
+	};
 };
 
 &apps_rsc {
@@ -690,6 +752,39 @@ &pon_resin {
 	status = "okay";
 };
 
+&qup_uart11_cts {
+	/*
+	 * Configure a bias-bus-hold on CTS to lower power
+	 * usage when Bluetooth is turned off. Bus hold will
+	 * maintain a low power state regardless of whether
+	 * the Bluetooth module drives the pin in either
+	 * direction or leaves the pin fully unpowered.
+	 */
+	bias-bus-hold;
+};
+
+&qup_uart11_rts {
+	/* We'll drive RTS, so no pull */
+	drive-strength = <2>;
+	bias-disable;
+};
+
+&qup_uart11_rx {
+	/*
+	 * Configure a pull-up on RX. This is needed to avoid
+	 * garbage data when the TX pin of the Bluetooth module is
+	 * in tri-state (module powered off or not driving the
+	 * signal yet).
+	 */
+	bias-pull-up;
+};
+
+&qup_uart11_tx {
+	/* We'll drive TX, so no pull */
+	drive-strength = <2>;
+	bias-disable;
+};
+
 &qupv3_id_0 {
 	status = "okay";
 };
@@ -748,6 +843,59 @@ &tlmm {
 			       <13 1>, /* NC */
 			       <63 2>; /* WLAN UART */
 
+	qup_uart11_sleep_cts: qup-uart11-sleep-cts-state {
+		pins = "gpio48";
+		function = "gpio";
+		/*
+		 * Configure a bias-bus-hold on CTS to lower power
+		 * usage when Bluetooth is turned off. Bus hold will
+		 * maintain a low power state regardless of whether
+		 * the Bluetooth module drives the pin in either
+		 * direction or leaves the pin fully unpowered.
+		 */
+		bias-bus-hold;
+	};
+
+	qup_uart11_sleep_rts: qup-uart11-sleep-rts-state {
+		pins = "gpio49";
+		function = "gpio";
+		/*
+		 * Configure pull-down on RTS. As RTS is active low
+		 * signal, pull it low to indicate the BT SoC that it
+		 * can wakeup the system anytime from suspend state by
+		 * pulling RX low (by sending wakeup bytes).
+		 */
+		bias-pull-down;
+	};
+
+	qup_uart11_sleep_tx: qup-uart11-sleep-tx-state {
+		pins = "gpio50";
+		function = "gpio";
+		/*
+		 * Configure pull-up on TX when it isn't actively driven
+		 * to prevent BT SoC from receiving garbage during sleep.
+		 */
+		bias-pull-up;
+	};
+
+	qup_uart11_sleep_rx: qup-uart11-sleep-rx-state {
+		pins = "gpio51";
+		function = "gpio";
+		/*
+		 * Configure a pull-up on RX. This is needed to avoid
+		 * garbage data when the TX pin of the Bluetooth module
+		 * is floating which may cause spurious wakeups.
+		 */
+		bias-pull-up;
+	};
+
+	bluetooth_enable_default: bluetooth-enable-default-state {
+		pins = "gpio53";
+		function = "gpio";
+		output-low;
+		bias-disable;
+	};
+
 	sdc2_card_det_n: sdc2-card-det-state {
 		pins = "gpio65";
 		function = "gpio";
@@ -767,6 +915,32 @@ &uart5 {
 	status = "okay";
 };
 
+&uart11 {
+	/delete-property/ interrupts;
+	interrupts-extended = <&intc GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH 0>,
+			      <&tlmm 51 IRQ_TYPE_EDGE_FALLING>;
+
+	pinctrl-1 =  <&qup_uart11_sleep_cts>,
+		     <&qup_uart11_sleep_rts>,
+		     <&qup_uart11_sleep_tx>,
+		     <&qup_uart11_sleep_rx>;
+	pinctrl-names = "default",
+			"sleep";
+
+	status = "okay";
+
+	bluetooth {
+		compatible = "qcom,wcn6750-bt"; /* WCN6755 */
+
+		vddrfacmn-supply = <&vreg_pmu_rfa_cmn>;
+		vddaon-supply = <&vreg_pmu_aon_0p59>;
+		vddbtcmx-supply = <&vreg_pmu_btcmx_0p85>;
+		vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>;
+		vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>;
+		vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>;
+	};
+};
+
 &usb_1 {
 	dr_mode = "otg";
 

-- 
2.52.0

Re: [PATCH 4/5] arm64: dts: qcom: milos-fairphone-fp6: Enable Bluetooth

[Dmitry Baryshkov]

On Fri, Jan 16, 2026 at 03:50:50PM +0100, Luca Weiss wrote:
> Add the nodes to describe the WCN6755 chip with its PMU and Bluetooth
> parts.
> 
> Thanks to Alexander Koskovich for helping with the bringup, adding
> 'clocks' to the PMU node to make Bluetooth work.
> 
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
>  arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 174 +++++++++++++++++++++++
>  1 file changed, 174 insertions(+)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


-- 
With best wishes
Dmitry

Re: [PATCH 4/5] arm64: dts: qcom: milos-fairphone-fp6: Enable Bluetooth

[Konrad Dybcio]

On 1/16/26 3:50 PM, Luca Weiss wrote:
> Add the nodes to describe the WCN6755 chip with its PMU and Bluetooth
> parts.
> 
> Thanks to Alexander Koskovich for helping with the bringup, adding
> 'clocks' to the PMU node to make Bluetooth work.
> 
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
>  arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 174 +++++++++++++++++++++++
>  1 file changed, 174 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
> index 52895dd9e4fa..cbe1507b0aaa 100644
> --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
> +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
> @@ -24,6 +24,7 @@ / {
>  
>  	aliases {
>  		serial0 = &uart5;
> +		serial1 = &uart11;
>  	};
>  
>  	gpio-keys {
> @@ -215,6 +216,67 @@ trip1 {
>  			};
>  		};
>  	};
> +
> +	wcn6750-pmu {
> +		compatible = "qcom,wcn6750-pmu"; /* WCN6755 */

I think a fallback compatible would be in order, if the data matches
exactly

> +	bluetooth_enable_default: bluetooth-enable-default-state {
> +		pins = "gpio53";
> +		function = "gpio";
> +		output-low;
> +		bias-disable;
> +	};

Not sure if we need to drive that pin.. perhaps a pull-down would
suffice?

[...]

> +	bluetooth {
> +		compatible = "qcom,wcn6750-bt"; /* WCN6755 */

Likewise

Konrad

Re: [PATCH 4/5] arm64: dts: qcom: milos-fairphone-fp6: Enable Bluetooth

[Luca Weiss]

On Wed Jan 21, 2026 at 12:52 PM CET, Konrad Dybcio wrote:
> On 1/16/26 3:50 PM, Luca Weiss wrote:
>> Add the nodes to describe the WCN6755 chip with its PMU and Bluetooth
>> parts.
>> 
>> Thanks to Alexander Koskovich for helping with the bringup, adding
>> 'clocks' to the PMU node to make Bluetooth work.
>> 
>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>> ---
>>  arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 174 +++++++++++++++++++++++
>>  1 file changed, 174 insertions(+)
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>> index 52895dd9e4fa..cbe1507b0aaa 100644
>> --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>> +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>> @@ -24,6 +24,7 @@ / {
>>  
>>  	aliases {
>>  		serial0 = &uart5;
>> +		serial1 = &uart11;
>>  	};
>>  
>>  	gpio-keys {
>> @@ -215,6 +216,67 @@ trip1 {
>>  			};
>>  		};
>>  	};
>> +
>> +	wcn6750-pmu {
>> +		compatible = "qcom,wcn6750-pmu"; /* WCN6755 */
>
> I think a fallback compatible would be in order, if the data matches
> exactly

That'd give us these changes

milos.dtsi:

    -+                  compatible = "qcom,wcn6750-wifi";
    ++                  compatible = "qcom,wcn6755-wifi", "qcom,wcn6750-wifi";

milos-fairphone-fp6.dts:

    -+          compatible = "qcom,wcn6750-pmu"; /* WCN6755 */
    ++          compatible = "qcom,wcn6755-pmu", "qcom,wcn6750-pmu";

    -+          compatible = "qcom,wcn6750-bt"; /* WCN6755 */
    ++          compatible = "qcom,wcn6755-bt", "qcom,wcn6750-bt";

Plus 3 new patches for dt-bindings, with commit message something like

Document the WCN6755 WiFi using a fallback to WCN6750 since the two
chips seem to be completely pin and software compatible. In fact the
original downstream kernel just pretends the WCN6755 is a WCN6750.

Does this sound okay?

>
>> +	bluetooth_enable_default: bluetooth-enable-default-state {
>> +		pins = "gpio53";
>> +		function = "gpio";
>> +		output-low;
>> +		bias-disable;
>> +	};
>
> Not sure if we need to drive that pin.. perhaps a pull-down would
> suffice?

I'll give it a shot, this pinctrl is coming from downstream but perhaps
the downstream btpower.c driver is differing in behavior to the upstream
PMU driver.

Regards
Luca

>
> [...]
>
>> +	bluetooth {
>> +		compatible = "qcom,wcn6750-bt"; /* WCN6755 */
>
> Likewise
>
> Konrad

Re: [PATCH 4/5] arm64: dts: qcom: milos-fairphone-fp6: Enable Bluetooth

[Konrad Dybcio]

On 3/13/26 11:40 AM, Luca Weiss wrote:
> On Wed Jan 21, 2026 at 12:52 PM CET, Konrad Dybcio wrote:
>> On 1/16/26 3:50 PM, Luca Weiss wrote:
>>> Add the nodes to describe the WCN6755 chip with its PMU and Bluetooth
>>> parts.
>>>
>>> Thanks to Alexander Koskovich for helping with the bringup, adding
>>> 'clocks' to the PMU node to make Bluetooth work.
>>>
>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>> ---
>>>  arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 174 +++++++++++++++++++++++
>>>  1 file changed, 174 insertions(+)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>>> index 52895dd9e4fa..cbe1507b0aaa 100644
>>> --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>>> +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>>> @@ -24,6 +24,7 @@ / {
>>>  
>>>  	aliases {
>>>  		serial0 = &uart5;
>>> +		serial1 = &uart11;
>>>  	};
>>>  
>>>  	gpio-keys {
>>> @@ -215,6 +216,67 @@ trip1 {
>>>  			};
>>>  		};
>>>  	};
>>> +
>>> +	wcn6750-pmu {
>>> +		compatible = "qcom,wcn6750-pmu"; /* WCN6755 */
>>
>> I think a fallback compatible would be in order, if the data matches
>> exactly
> 
> That'd give us these changes
> 
> milos.dtsi:
> 
>     -+                  compatible = "qcom,wcn6750-wifi";
>     ++                  compatible = "qcom,wcn6755-wifi", "qcom,wcn6750-wifi";
> 
> milos-fairphone-fp6.dts:
> 
>     -+          compatible = "qcom,wcn6750-pmu"; /* WCN6755 */
>     ++          compatible = "qcom,wcn6755-pmu", "qcom,wcn6750-pmu";
> 
>     -+          compatible = "qcom,wcn6750-bt"; /* WCN6755 */
>     ++          compatible = "qcom,wcn6755-bt", "qcom,wcn6750-bt";
> 
> Plus 3 new patches for dt-bindings, with commit message something like
> 
> Document the WCN6755 WiFi using a fallback to WCN6750 since the two
> chips seem to be completely pin and software compatible. In fact the
> original downstream kernel just pretends the WCN6755 is a WCN6750.
> 
> Does this sound okay?

To me yes, but I have zero insight into what's the actual difference/
whether there's any. Maybe +Jeff could spare some details

Konrad

Re: [PATCH 4/5] arm64: dts: qcom: milos-fairphone-fp6: Enable Bluetooth

[Luca Weiss]

On Fri Mar 13, 2026 at 11:40 AM CET, Luca Weiss wrote:
> On Wed Jan 21, 2026 at 12:52 PM CET, Konrad Dybcio wrote:
>> On 1/16/26 3:50 PM, Luca Weiss wrote:
>>> Add the nodes to describe the WCN6755 chip with its PMU and Bluetooth
>>> parts.
>>> 
>>> Thanks to Alexander Koskovich for helping with the bringup, adding
>>> 'clocks' to the PMU node to make Bluetooth work.
>>> 
>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>> ---
>>>  arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 174 +++++++++++++++++++++++
>>>  1 file changed, 174 insertions(+)
>>> 
>>> diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>>> index 52895dd9e4fa..cbe1507b0aaa 100644
>>> --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>>> +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts

<snip>

>>> +	bluetooth_enable_default: bluetooth-enable-default-state {
>>> +		pins = "gpio53";
>>> +		function = "gpio";
>>> +		output-low;
>>> +		bias-disable;
>>> +	};
>>
>> Not sure if we need to drive that pin.. perhaps a pull-down would
>> suffice?
>
> I'll give it a shot, this pinctrl is coming from downstream but perhaps
> the downstream btpower.c driver is differing in behavior to the upstream
> PMU driver.

Seems to work, but honestly I'm not sure what the actual effects of this
change are?

-               output-low;
-               bias-disable;
+               bias-pull-down;

Regards
Luca

Re: [PATCH 4/5] arm64: dts: qcom: milos-fairphone-fp6: Enable Bluetooth

[Konrad Dybcio]

On 3/13/26 3:00 PM, Luca Weiss wrote:
> On Fri Mar 13, 2026 at 11:40 AM CET, Luca Weiss wrote:
>> On Wed Jan 21, 2026 at 12:52 PM CET, Konrad Dybcio wrote:
>>> On 1/16/26 3:50 PM, Luca Weiss wrote:
>>>> Add the nodes to describe the WCN6755 chip with its PMU and Bluetooth
>>>> parts.
>>>>
>>>> Thanks to Alexander Koskovich for helping with the bringup, adding
>>>> 'clocks' to the PMU node to make Bluetooth work.
>>>>
>>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>>> ---
>>>>  arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 174 +++++++++++++++++++++++
>>>>  1 file changed, 174 insertions(+)
>>>>
>>>> diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>>>> index 52895dd9e4fa..cbe1507b0aaa 100644
>>>> --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>>>> +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
> 
> <snip>
> 
>>>> +	bluetooth_enable_default: bluetooth-enable-default-state {
>>>> +		pins = "gpio53";
>>>> +		function = "gpio";
>>>> +		output-low;
>>>> +		bias-disable;
>>>> +	};
>>>
>>> Not sure if we need to drive that pin.. perhaps a pull-down would
>>> suffice?
>>
>> I'll give it a shot, this pinctrl is coming from downstream but perhaps
>> the downstream btpower.c driver is differing in behavior to the upstream
>> PMU driver.
> 
> Seems to work, but honestly I'm not sure what the actual effects of this
> change are?

output-low actually actively drives the pin low, while bias-pull-down
connects it to an internal pull-down circuit, which is weaker, but also
saves power (because the pin isn't actually driven)

Konrad

[PATCH 5/5] arm64: dts: qcom: milos-fairphone-fp6: Enable WiFi

[Luca Weiss]

Configure and enable the WiFi node, and add the required pinctrl to
provide the sleep clock from the PMK8550 (PMK7635) to WCN6755.

Thanks to Alexander Koskovich for helping with the bringup, adding
the missing pinctrl to make the WPSS stop crashing.

Link: https://lore.kernel.org/linux-arm-msm/DBF7OWAWQ94M.FSCP4DPF8ZJY@fairphone.com/
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
 arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 19 ++++++++++++++++++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
index cbe1507b0aaa..75f2b3a3e572 100644
--- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
+++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
@@ -232,7 +232,7 @@ wcn6750-pmu {
 
 		clocks = <&rpmhcc RPMH_RF_CLK1>;
 
-		pinctrl-0 = <&bluetooth_enable_default>;
+		pinctrl-0 = <&bluetooth_enable_default>, <&pmk8550_sleep_clk_default>;
 		pinctrl-names = "default";
 
 		regulators {
@@ -704,6 +704,17 @@ &pmiv0104_eusb2_repeater {
 	qcom,tune-usb2-preem = /bits/ 8 <0x6>;
 };
 
+&pmk8550_gpios {
+	pmk8550_sleep_clk_default: sleep-clk-default-state {
+		pins = "gpio5";
+		function = "func1";
+		input-disable;
+		output-enable;
+		bias-disable;
+		power-source = <0>;
+	};
+};
+
 &pmr735b_gpios {
 	s1j_enable_default: s1j-enable-default-state {
 		pins = "gpio1";
@@ -962,3 +973,9 @@ &usb_1_hsphy {
 
 	status = "okay";
 };
+
+&wifi {
+	qcom,calibration-variant = "Fairphone_Gen_6";
+
+	status = "okay";
+};

-- 
2.52.0

Re: [PATCH 5/5] arm64: dts: qcom: milos-fairphone-fp6: Enable WiFi

[Dmitry Baryshkov]

On Fri, Jan 16, 2026 at 03:50:51PM +0100, Luca Weiss wrote:
> Configure and enable the WiFi node, and add the required pinctrl to
> provide the sleep clock from the PMK8550 (PMK7635) to WCN6755.
> 
> Thanks to Alexander Koskovich for helping with the bringup, adding
> the missing pinctrl to make the WPSS stop crashing.
> 
> Link: https://lore.kernel.org/linux-arm-msm/DBF7OWAWQ94M.FSCP4DPF8ZJY@fairphone.com/
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
>  arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 19 ++++++++++++++++++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
> 
> @@ -962,3 +973,9 @@ &usb_1_hsphy {
>  
>  	status = "okay";
>  };
> +
> +&wifi {
> +	qcom,calibration-variant = "Fairphone_Gen_6";

With the hope of getting the board data submitted to ath11k@


Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>



> +
> +	status = "okay";
> +};
> 
> -- 
> 2.52.0
> 

-- 
With best wishes
Dmitry

Re: [PATCH 5/5] arm64: dts: qcom: milos-fairphone-fp6: Enable WiFi

[Konrad Dybcio]

On 1/16/26 3:50 PM, Luca Weiss wrote:
> Configure and enable the WiFi node, and add the required pinctrl to
> provide the sleep clock from the PMK8550 (PMK7635) to WCN6755.
> 
> Thanks to Alexander Koskovich for helping with the bringup, adding
> the missing pinctrl to make the WPSS stop crashing.
> 
> Link: https://lore.kernel.org/linux-arm-msm/DBF7OWAWQ94M.FSCP4DPF8ZJY@fairphone.com/
> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
> ---
>  arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 19 ++++++++++++++++++-
>  1 file changed, 18 insertions(+), 1 deletion(-)
> 
> diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
> index cbe1507b0aaa..75f2b3a3e572 100644
> --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
> +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
> @@ -232,7 +232,7 @@ wcn6750-pmu {
>  
>  		clocks = <&rpmhcc RPMH_RF_CLK1>;
>  
> -		pinctrl-0 = <&bluetooth_enable_default>;
> +		pinctrl-0 = <&bluetooth_enable_default>, <&pmk8550_sleep_clk_default>;
>  		pinctrl-names = "default";
>  
>  		regulators {
> @@ -704,6 +704,17 @@ &pmiv0104_eusb2_repeater {
>  	qcom,tune-usb2-preem = /bits/ 8 <0x6>;
>  };
>  
> +&pmk8550_gpios {
> +	pmk8550_sleep_clk_default: sleep-clk-default-state {
> +		pins = "gpio5";

I'm thinking how to best reflect that. Perhaps gpio-gate-clock which
would be consumed by the PMU?

FWIW PMK8550 can reportedly output this clock from GPIO3 and GPIO5
(not sure if at once) if set to FUNC1

Konrad

Re: [PATCH 5/5] arm64: dts: qcom: milos-fairphone-fp6: Enable WiFi

[Luca Weiss]

On Wed Jan 21, 2026 at 12:50 PM CET, Konrad Dybcio wrote:
> On 1/16/26 3:50 PM, Luca Weiss wrote:
>> Configure and enable the WiFi node, and add the required pinctrl to
>> provide the sleep clock from the PMK8550 (PMK7635) to WCN6755.
>> 
>> Thanks to Alexander Koskovich for helping with the bringup, adding
>> the missing pinctrl to make the WPSS stop crashing.
>> 
>> Link: https://lore.kernel.org/linux-arm-msm/DBF7OWAWQ94M.FSCP4DPF8ZJY@fairphone.com/
>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>> ---
>>  arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 19 ++++++++++++++++++-
>>  1 file changed, 18 insertions(+), 1 deletion(-)
>> 
>> diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>> index cbe1507b0aaa..75f2b3a3e572 100644
>> --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>> +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>> @@ -232,7 +232,7 @@ wcn6750-pmu {
>>  
>>  		clocks = <&rpmhcc RPMH_RF_CLK1>;
>>  
>> -		pinctrl-0 = <&bluetooth_enable_default>;
>> +		pinctrl-0 = <&bluetooth_enable_default>, <&pmk8550_sleep_clk_default>;
>>  		pinctrl-names = "default";
>>  
>>  		regulators {
>> @@ -704,6 +704,17 @@ &pmiv0104_eusb2_repeater {
>>  	qcom,tune-usb2-preem = /bits/ 8 <0x6>;
>>  };
>>  
>> +&pmk8550_gpios {
>> +	pmk8550_sleep_clk_default: sleep-clk-default-state {
>> +		pins = "gpio5";
>
> I'm thinking how to best reflect that. Perhaps gpio-gate-clock which
> would be consumed by the PMU?

This way of doing it already has a precedent with sm8550-hdk.dts and
sm8550-qrd.dts at least.

Regards
Luca

>
> FWIW PMK8550 can reportedly output this clock from GPIO3 and GPIO5
> (not sure if at once) if set to FUNC1
>
> Konrad

Re: [PATCH 5/5] arm64: dts: qcom: milos-fairphone-fp6: Enable WiFi

[Konrad Dybcio]

On 2/13/26 3:24 PM, Luca Weiss wrote:
> On Wed Jan 21, 2026 at 12:50 PM CET, Konrad Dybcio wrote:
>> On 1/16/26 3:50 PM, Luca Weiss wrote:
>>> Configure and enable the WiFi node, and add the required pinctrl to
>>> provide the sleep clock from the PMK8550 (PMK7635) to WCN6755.
>>>
>>> Thanks to Alexander Koskovich for helping with the bringup, adding
>>> the missing pinctrl to make the WPSS stop crashing.
>>>
>>> Link: https://lore.kernel.org/linux-arm-msm/DBF7OWAWQ94M.FSCP4DPF8ZJY@fairphone.com/
>>> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
>>> ---
>>>  arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts | 19 ++++++++++++++++++-
>>>  1 file changed, 18 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>>> index cbe1507b0aaa..75f2b3a3e572 100644
>>> --- a/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>>> +++ b/arch/arm64/boot/dts/qcom/milos-fairphone-fp6.dts
>>> @@ -232,7 +232,7 @@ wcn6750-pmu {
>>>  
>>>  		clocks = <&rpmhcc RPMH_RF_CLK1>;
>>>  
>>> -		pinctrl-0 = <&bluetooth_enable_default>;
>>> +		pinctrl-0 = <&bluetooth_enable_default>, <&pmk8550_sleep_clk_default>;
>>>  		pinctrl-names = "default";
>>>  
>>>  		regulators {
>>> @@ -704,6 +704,17 @@ &pmiv0104_eusb2_repeater {
>>>  	qcom,tune-usb2-preem = /bits/ 8 <0x6>;
>>>  };
>>>  
>>> +&pmk8550_gpios {
>>> +	pmk8550_sleep_clk_default: sleep-clk-default-state {
>>> +		pins = "gpio5";
>>
>> I'm thinking how to best reflect that. Perhaps gpio-gate-clock which
>> would be consumed by the PMU?
> 
> This way of doing it already has a precedent with sm8550-hdk.dts and
> sm8550-qrd.dts at least.

OK I thought it was "new" (quotes because some wifi cards required this back
in the 8994 times).

Konrad

Re: (subset) [PATCH 0/5] Enable Bluetooth and WiFi on Fairphone (Gen. 6)

[Bjorn Andersson]

On Fri, 16 Jan 2026 15:50:46 +0100, Luca Weiss wrote:
> Add the required bits to enable Bluetooth and WiFi on the Milos
> SoC-based Fairphone (Gen. 6) smartphone.
> 
> 

Applied, thanks!

[1/5] soc: qcom: pd-mapper: Add Milos compatible
      commit: 678647c26e317d8d1de4d630ee9ffa7ecad637fe

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>