From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from out-185.mta0.migadu.com (out-185.mta0.migadu.com [91.218.175.185]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D39912BF006 for ; Mon, 23 Feb 2026 14:40:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.218.175.185 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771857624; cv=none; b=TVVdgjae95WY9AsOKndDQ6R4rKbJAyQMmeb72han87a2HfvP3J3ECMMdqLPTJDhhLjfSn8Tw8w0MZ/cFBaBb4oCjop8jo7lhjqsEK5JkqX+Y+jkbPDvd8RDCHoMh8qJ4x9K6okM8rdH/nGvFrck2/2rODVNhCc/bzvJA9a9EGHw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771857624; c=relaxed/simple; bh=q9gO9g6GAbxiUvlliWF9Tl7BEjGnbmpJ6tFjS/ahug0=; h=Mime-Version:Content-Type:Date:Message-Id:To:Cc:Subject:From: References:In-Reply-To; b=HdpukdT8pvRWCiXImEiJ9Qj06iCmky7Bt+t4l7ZmYJ9Uai0wLpeZ2EX7u2txa7Kz6gx7Vqph9ye3OGAY6Nq4YO2l4ZwFt0Gxy76J90Ef1yc/PxgansZ9Lv+BgPm+ym5OMYpZ0xxD7WhzeKHakO8YHZYRt+XLxV3LPb9wVfw5KpY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=cknow-tech.com; spf=pass smtp.mailfrom=cknow-tech.com; dkim=pass (2048-bit key) header.d=cknow-tech.com header.i=@cknow-tech.com header.b=K7PJH590; arc=none smtp.client-ip=91.218.175.185 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=cknow-tech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=cknow-tech.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=cknow-tech.com header.i=@cknow-tech.com header.b="K7PJH590" Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=cknow-tech.com; s=key1; t=1771857609; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gMw6gf/oTSSqQro1Zpiosb4Vw6V7R5A1fyETNWZeN+E=; b=K7PJH590JkvaDXDSFyhWY/LA9PkPKekKf738AGPatQKh8iq85Hc8h/vy4twZj70vWljspl nlQZwhndSsBDcdVIaX0u9MAXXt7FuCeqT8aISrgrchStN8NytmQP2Dv6Gs2HJx38zwnnJ+ 4KCZ9V+R+L7SkwIy4gPve9dGbD1rylnIC6bJ80B29RgLhOemXH2lrBNdtE9vzM8TY5nbW0 OwsiUM4wURlwid38th3rn61jD4pRxL2YmPvcB7tin1mh3WGRX1icKn8e+Eaj9LwbjeMugO y5l0gQLK5PqGKFEZcAzcz7CFjJqnoqAonA/WzkHLXVDIJAeXGJ8kOdybeCqfJA== Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 23 Feb 2026 15:39:56 +0100 Message-Id: To: "Sebastian Reichel" , "Cristian Ciocaltea" Cc: "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Heiko Stuebner" , "Detlev Casanova" , , , , , Subject: Re: [PATCH] arm64: dts: rockchip: Fix vdec register blocks order on RK3576 X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. From: "Diederik de Haas" References: <20260223-vdec-reg-order-rk3576-v1-1-560976566bd3@collabora.com> In-Reply-To: X-Migadu-Flow: FLOW_OUT On Mon Feb 23, 2026 at 3:31 PM CET, Sebastian Reichel wrote: > On Mon, Feb 23, 2026 at 02:25:05PM +0200, Cristian Ciocaltea wrote: >> When building device trees for the RK3576 based boards, DTC shows the >> following complaint: >>=20 >> rk3576.dtsi:1282.30-1304.5: Warning (simple_bus_reg): /soc/video-codec= @27b00000: simple-bus unit address format error, expected "27b00100" >>=20 >> Provide the register blocks in the expected address-based order. >>=20 >> Fixes: da0de806d8b4 ("arm64: dts: rockchip: Add the vdpu383 Video Decode= r on rk3576") >> Signed-off-by: Cristian Ciocaltea >> --- > > This fixes this warning, but instead creates a new one, because the > reg-names order is fixed in the DT binding: > > reg: > minItems: 1 > items: > - description: The function configuration registers base > - description: The link table configuration registers base > - description: The cache configuration registers base > =20 > reg-names: > items: > - const: function > - const: link > - const: cache See also the prior discussion wrt this: https://lore.kernel.org/linux-rockchip/edabca63-594e-44ae-8a3d-0f60987a8664= @collabora.com/ > > Greetings, > > -- Sebastian > >> arch/arm64/boot/dts/rockchip/rk3576.dtsi | 6 +++--- >> 1 file changed, 3 insertions(+), 3 deletions(-) >>=20 >> diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/= dts/rockchip/rk3576.dtsi >> index 49ccdf12ef7e..45eb0d053a6f 100644 >> --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi >> +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi >> @@ -1281,10 +1281,10 @@ gpu: gpu@27800000 { >> =20 >> vdec: video-codec@27b00000 { >> compatible =3D "rockchip,rk3576-vdec"; >> - reg =3D <0x0 0x27b00100 0x0 0x500>, >> - <0x0 0x27b00000 0x0 0x100>, >> + reg =3D <0x0 0x27b00000 0x0 0x100>, >> + <0x0 0x27b00100 0x0 0x500>, >> <0x0 0x27b00600 0x0 0x100>; >> - reg-names =3D "function", "link", "cache"; >> + reg-names =3D "link", "function", "cache"; >> interrupts =3D ; >> clocks =3D <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>, >> <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>, >>=20 >> --- >> base-commit: 6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f >> change-id: 20260223-vdec-reg-order-rk3576-cc2ec6e05e98 >>=20