Re: [PATCH v1 2/2] riscv: dts: spacemit: add DeepComputing FML13V05 board device tree

曹珊珊
2026-04-01T07:38:37Z

Hi Troy,

> From: "Troy Mitchell"<troy.mitchell@linux.spacemit.com>
> Date:  Wed, Apr 1, 2026, 14:42

> On Wed Apr 1, 2026 at 2:10 PM CST, 曹珊珊 wrote:
> > Hi Lan,
> >
> >> From: "Yixun Lan"<dlan@kernel.org>
> >> Hi Sandie,
> >>
> >> On 11:46 Tue 31 Mar     , Sandie Cao wrote:
> >> > From: sandiecao <sandie.cao@deepcomputing.io>
> >> >
> >> > The FML13V05 board from DeepComputing incorporates a SpacemiT K3 RISC-V
> >> > SoC.It is a mainboard designed for the Framework Laptop 13 Chassis,
> >> > which has (Framework) SKU FRANHQ0001.
> >> >
> >> > The FML13V05 board features:
> >> > - SpacemiT K3 RISC-V SoC
> >> > - LPDDR5 16GB or 32GB
> >> > - eMMC 32GB ~128GB (Optional)
> >> > - UFS 3.1 256G (Optional)
> >> > - QSPI Flash
> >> > - MicroSD Slot
> >> > - PCIe-based Wi-Fi
> >> > - 4 USB-C Ports
> >> >  - Port 1: PD 3.0 (65W Max), USB 3.2 Gen 1
> >> >  - Port 2: PD 3.0 (65W Max), USB 3.2 Gen 1, DP 1.4 (4K@60Hz)
> >> >  - Port 3 & 4: USB 3.2 Gen 1
> >> >
> >> > This minimal device tree enables booting into a serial console with UART
> >> > output.
> >> >
> >> > Signed-off-by: sandiecao <sandie.cao@deepcomputing.io>
> >> > Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
> >> > +&uart0 {
> >> Can you also add pinctrl data explicitly?
> >
> > To avoid conflict,  the common pinctrl table "k3-pinctrl.dtsi" should be uploaded by spacemit.
> > Then we will add the pinctrl data after k3-pico-itx.dts. That should be another patch.
> > Sandie
> I think you don't understand what Yixun said.
> You should add pinctrl properties here like:
> pinctrl-0 = xxx;
> pinctrl-names = "default";
>
> While the bootloader is expected to initialize the UART pins, explicitly adding the pinctrl properties
> ensures hardware state consistency.
>
>                                       - Troy
>

Yes, I know this.
If I add
pinctrl-names = "default";
pinctrl-0 = <&uart0_0_cfg>;
Then also need to add
&pinctrl {
uart0_0_cfg: uart0-0-cfg {
uart0-0-pins {
pinmux = <K3_PADCONF(149, 2)>,        /* uart0 tx */
<K3_PADCONF(150, 2)>;        /* uart0 rx */

bias-pull-up;                        /* normal pull-up */
drive-strength = <25>;                /* DS8 */
};
};
};
But this part is common, it should be defined in common pinctrl table "k3-pinctrl.dtsi". And this part hasn't comed to Upstream.
If I add it currently,  When k3-pinctrl.dtsi is accepted by Upstream, we need to remove it again.
So we just empty it for simple.
Sandie