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Wed, 08 Apr 2026 07:30:57 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 08 Apr 2026 15:30:56 +0100 Message-Id: From: "Alexey Klimov" To: =?utf-8?q?Andr=C3=A9_Draszik?= , "Sam Protsenko" , , "Krzysztof Kozlowski" , "Peter Griffin" , "Conor Dooley" , "Alim Akhtar" Cc: "Tudor Ambarus" , "Rob Herring" , "Krzysztof Kozlowski" , , , Subject: Re: [PATCH v2 2/7] dt-bindings: soc: samsung: exynos-pmu: add samsung,pmu-intr-gen phandle X-Mailer: aerc 0.20.0 References: <20260401-exynos850-cpuhotplug-v2-0-c5a760a3e259@linaro.org> <20260401-exynos850-cpuhotplug-v2-2-c5a760a3e259@linaro.org> <01ffe5d3aca040edcedb084386ab6e195cb93013.camel@linaro.org> In-Reply-To: <01ffe5d3aca040edcedb084386ab6e195cb93013.camel@linaro.org> Hi Andr=C3=A9, On Fri Apr 3, 2026 at 11:17 AM BST, Andr=C3=A9 Draszik wrote: > Hi Alexey, > > On Wed, 2026-04-01 at 05:51 +0100, Alexey Klimov wrote: >> Some Exynos-based SoCs, for instance Exynos850, require access >> to the pmu interrupt generation register region which is exposed >> as a syscon. Update the exynos-pmu bindings documentation to >> reflect this. > > You could mention that this is similar to the existing google,... > one due to same requirement, hence a new and more general property. Ok. Thanks. >> Signed-off-by: Alexey Klimov >> --- >> =C2=A0.../devicetree/bindings/soc/samsung/exynos-pmu.yaml=C2=A0=C2=A0=C2= =A0 | 18 ++++++++++++++++++ >> =C2=A01 file changed, 18 insertions(+) >>=20 >> diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.ya= ml b/Documentation/devicetree/bindings/soc/samsung/exynos- >> pmu.yaml >> index 76ce7e98c10f..92acdfd5d44e 100644 >> --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml >> +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml >> @@ -110,6 +110,11 @@ properties: >> =C2=A0=C2=A0=C2=A0=C2=A0 description: >> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Node for reboot method >> =C2=A0 >> +=C2=A0 samsung,pmu-intr-gen-syscon: >> +=C2=A0=C2=A0=C2=A0 $ref: /schemas/types.yaml#/definitions/phandle >> +=C2=A0=C2=A0=C2=A0 description: >> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 Phandle to PMU interrupt generation inte= rface. >> + >> =C2=A0=C2=A0 google,pmu-intr-gen-syscon: > > Please keep alphabetical order of vendors. Sure. Thanks for noticing this. Best regards, Alexey