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[144.178.202.138]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c15ad821666sm1005757166b.4.2026.07.13.07.57.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 13 Jul 2026 07:57:40 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 13 Jul 2026 16:57:40 +0200 Message-Id: Cc: "Ajit Pandey" , "Imran Shaik" , "Jagadeesh Kona" , , , , , , , "Krzysztof Kozlowski" , "Konrad Dybcio" Subject: Re: [PATCH v7 03/10] arm64: dts: qcom: milos: Add power-domains for camcc and videocc From: "Luca Weiss" To: "Taniya Das" , "Bjorn Andersson" , "Michael Turquette" , "Stephen Boyd" , "Brian Masney" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Luca Weiss" , "Konrad Dybcio" , "Maxime Coquelin" , "Alexandre Torgue" , "Dmitry Baryshkov" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260713-b4-eliza_mm_cc_v6-v7-0-4d91bcef50eb@oss.qualcomm.com> <20260713-b4-eliza_mm_cc_v6-v7-3-4d91bcef50eb@oss.qualcomm.com> In-Reply-To: <20260713-b4-eliza_mm_cc_v6-v7-3-4d91bcef50eb@oss.qualcomm.com> Hi Taniya, On Mon Jul 13, 2026 at 4:53 PM CEST, Taniya Das wrote: > The Milos camera and video clock controllers operate on the CX and MX > power rails, and require these power domains along with their > associated performance state votes to be specified for accessing the > clock controller and its GDSC. Add the 'power-domains' and > 'required-opps' properties to the camcc and videocc nodes. > > Fixes: d9d59d105f98 ("arm64: dts: qcom: Add initial Milos dtsi") > Signed-off-by: Taniya Das > --- > arch/arm64/boot/dts/qcom/milos.dtsi | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qc= om/milos.dtsi > index 8c92329889538f0d79f7af436898e3ee278e361c..7c42d6c89829e4bf5a2ade640= 18623e49623462c 100644 > --- a/arch/arm64/boot/dts/qcom/milos.dtsi > +++ b/arch/arm64/boot/dts/qcom/milos.dtsi > @@ -1892,6 +1892,11 @@ videocc: clock-controller@aaf0000 { > <&sleep_clk>, > <&gcc GCC_VIDEO_AHB_CLK>; > =20 > + power-domains =3D <&rpmhpd RPMHPD_CX>, > + <&rpmhpd RPMHPD_MX>; > + required-opps =3D <&rpmhpd_opp_low_svs>, > + <&rpmhpd_opp_low_svs>; > + > #clock-cells =3D <1>; > #reset-cells =3D <1>; > #power-domain-cells =3D <1>; > @@ -1971,6 +1976,11 @@ camcc: clock-controller@adb0000 { > <&sleep_clk>, > <&gcc GCC_CAMERA_AHB_CLK>; > =20 > + power-domains =3D <&rpmhpd RPMHPD_CX>, > + <&rpmhpd RPMHPD_MX>; > + required-opps =3D <&rpmhpd_opp_low_svs>, > + <&rpmhpd_opp_low_svs>; At least looking at downstream drivers (camcc-volcano.c and videocc-volcano.c), both have static DEFINE_VDD_REGULATORS(vdd_cx, VDD_HIGH + 1, 1, vdd_corner); static DEFINE_VDD_REGULATORS(vdd_mx, VDD_HIGH + 1, 1, vdd_corner); so from what I can tell based on that, your change seems correct. I'm sure you have better documentation than that at hand though! Regards Luca