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Thu, 23 Jul 2026 00:54:32 -0400 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="UTF-8" Date: Thu, 23 Jul 2026 12:54:23 +0800 Message-ID: CC: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , "Andy Shevchenko" , Michael Hennerich , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , "Philipp Zabel" , , , , Subject: Re: [PATCH v2 4/4] iio: dac: ad3530r: add support for AD5710R/AD5711R From: Kim Seer Paller To: Andy Shevchenko X-Mailer: aerc 0.8.2 References: <20260721-iio-ad5710r-upstream-v2-0-324949dc72da@analog.com> <20260721-iio-ad5710r-upstream-v2-4-324949dc72da@analog.com> In-Reply-To: X-ADIRuleOP-NewSCL: Rule Triggered X-Proofpoint-GUID: nP8IqFsj4tKebq06AjOU2ZEer7Q5KwYc X-Proofpoint-ORIG-GUID: nP8IqFsj4tKebq06AjOU2ZEer7Q5KwYc X-Proofpoint-Spam-Info: AW1haW4tMjYwNzIzMDA0NiBTYWx0ZWRfX6SqIQVsnySyx h8vZXhxkpidNzzlqcU1ajkcseB1GMEVVknRksSeSyfOjB+awzAhl+UK6W6vj4A9vGWZKxc03xRj bLwj0j9mxE4iOQWyXScjH0VJqhvORd5xqgbRgklL7APIW8w9GH7q X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzIzMDA0NiBTYWx0ZWRfX5MzTgB5DRfYr oW7BXh4M6VLpKxbU0K96NW/0uVfUuVTCnTpepbQGY/3mJ5SeTuaL2KM8jh1BYg7g+6ghAr2ILAy JGDim5Fm6xfx2ufhWuIfW5Nqh5IF5Uewc+OTEYD1K73DH4lXVLi0b2cTtpHkrD1paWCh6TfGahB 59qUlKHHn1hOszUsgJZCh4VLAlyOIALneJPl2XY5vES38e8IIm/is4nPJT/8WrQSqhYiw3N2bsW enyMEyJxlQaKPJgyE4kImaQMsSDyGZiXyuxu8wTlnIDBP18FQcRqZfK/qCuwoSHA6L9JR93Pqt0 X8M5FkLOfNzTYTUd5MIHR4O1sBlFHu9vZ33CbU7Vj6CTZn4UjBTqp+aPJkvZ/+HgY9FZhCwB5De iFtS45e2oXZql1qygX7V0Ozl9CgqhO2iCmtd+cB2+c9fCaOxranbLnY0aetV/BaMVHAWLnab1v2 qCBPNXyCaqvvuOggVQQ== X-Authority-Analysis: v=2.4 cv=WIpPmHsR c=1 sm=1 tr=0 ts=6a619e9a cx=c_pps a=3WNzaoukacrqR9RwcOSAdA==:117 a=3WNzaoukacrqR9RwcOSAdA==:17 a=IkcTkHD0fZMA:10 a=RAioF0-LDSMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=0sLvza09kfJOxVLZPwjg:22 a=N--XFCr6TIEc_64PeIT2:22 a=VeLFCf2KXPs7WgRmu0EA:9 a=QEXdDO2ut3YA:10 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-23_01,2026-07-22_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 impostorscore=0 suspectscore=0 clxscore=1015 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607230046 On Tue Jul 21, 2026 at 6:38 PM PST, Andy Shevchenko wrote: > On Tue, Jul 21, 2026 at 04:47:13PM +0800, Kim Seer Paller wrote: > > Add support for the AD5710R/AD5711R, 8-channel 16-/12-bit configurable > > IDAC/VDAC parts. They share the AD3530R register map and access model, > > so fold them into this driver. > >=20 > > Each channel is configured as voltage or current output from its DT > > channel@N node via adi,ch-func, building the iio_chan_spec dynamically. > > Voltage channels enable VMODE_EN and report the reference-derived scale= , > > current channels report the 50 mA internal Iref scale. The powerdown > > mode is read-only and derived from the channel's configured type. > > ... > > > * AD3530R/AD3530 8-channel, 16-bit Voltage Output DAC Driver > > * AD3531R/AD3531 4-channel, 16-bit Voltage Output DAC Driver > > * AD3532R/AD3532 16-channel, 16-bit Voltage Output DAC Driver > > + * AD5710R/AD5711R 8-channel, 16-/12-bit Configurable IDAC/VDAC Driver > > In the above only a single data width is mentioned, maybe split this one? I agree, will split this into 2 lines. > > ... > > > #define AD3531R_MAX_CHANNELS 4 > > #define AD3532R_MAX_CHANNELS 16 > > +#define AD5710R_NUM_CHANNELS 8 > > Why NUM and not MAX? I think this can be drop since it was only used once in ad3530r_parse_chann= el_cfg() and that check can used chip_info->num_channels instead. > > ... > > > +static int ad5710r_get_powerdown_mode(struct iio_dev *indio_dev, > > + const struct iio_chan_spec *chan) > > +{ > > + struct ad3530r_state *st =3D iio_priv(indio_dev); > > + unsigned int val; > > + int ret; > > + > > + ret =3D regmap_read(st->regmap, AD5710R_CHN_VMODE_EN, &val); > > + if (ret) > > + return ret; > > + > > + return !(val & AD5710R_CHN_VMODE_EN_BIT(chan->channel)); > > regmap_test_bits() > > > +} > > ... > > > +static ssize_t ad5710r_get_dac_powerdown(struct iio_dev *indio_dev, > > + uintptr_t private, > > + const struct iio_chan_spec *chan, > > + char *buf) > > +{ > > + struct ad3530r_state *st =3D iio_priv(indio_dev); > > + unsigned int reg_offset, ch_in_reg, reg, mode, mask; > > + int ret; > > + > > + reg_offset =3D chan->channel / AD3530R_CH_PER_REG; > > + ch_in_reg =3D chan->channel % AD3530R_CH_PER_REG; > > + reg =3D AD3530R_OUTPUT_OPERATING_MODE_0 + reg_offset; > > + mask =3D AD3530R_OP_MODE_CHAN_MSK(ch_in_reg); > > + > > + ret =3D regmap_read(st->regmap, reg, &mode); > > + if (ret) > > + return ret; > > + > > + return sysfs_emit(buf, "%d\n", !!(mode & mask)); > > Ditto. > > > +} > > ... > > > +static const struct regmap_config ad5710r_regmap_config =3D { > > + .reg_bits =3D 16, > > + .val_bits =3D 8, > > + .max_register =3D AD5710R_CHN_VMODE_EN, > > +}; > > No cache? The existing ad3530r/ad3532r regmap configs don't use a cache either, so kept this one consistent. Can add it as a separate cleanup across all 3 configs if preferred. > > ... > > > +static int ad3530r_parse_channel_cfg(struct ad3530r_state *st) > > +{ > > + struct device *dev =3D regmap_get_device(st->regmap); > > + struct iio_chan_spec *channels; > > + int ret, num_chan; > > Why is 'num_chan' signed? > > > > + int i =3D 0; > > Signed? Also, split assignment and move it closer to its first user. > > > + u32 reg; > > + > > + num_chan =3D device_get_child_node_count(dev); > > + if (!num_chan) > > + return dev_err_probe(dev, -ENODEV, "No channels configured\n"); > > + > > + channels =3D devm_kcalloc(dev, num_chan, sizeof(*channels), GFP_KERNE= L); > > + if (!channels) > > + return -ENOMEM; > > > i =3D 0; > > > + device_for_each_child_node_scoped(dev, child) { > > + unsigned int reg_offset, ch_in_reg, mode_reg, mode_mask, ch_func; > > + enum iio_chan_type chan_type; > > + > > + ret =3D fwnode_property_read_u32(child, "reg", ®); > > + if (ret) > > + return dev_err_probe(dev, ret, > > + "Failed to read reg property of %pfwP\n", > > + child); > > + > > + if (reg >=3D AD5710R_NUM_CHANNELS) > > + return dev_err_probe(dev, -EINVAL, > > + "reg out of range in %pfwP\n", > > + child); > > + > > + ret =3D fwnode_property_read_u32(child, "adi,ch-func", &ch_func); > > + if (ret) > > + return dev_err_probe(dev, ret, > > + "Missing adi,ch-func property for %pfwP\n", > > + child); > > + > > + switch (ch_func) { > > + case CH_FUNC_VOLTAGE_OUTPUT: > > + ret =3D regmap_set_bits(st->regmap, AD5710R_CHN_VMODE_EN, > > + AD5710R_CHN_VMODE_EN_BIT(reg)); > > + if (ret) > > + return dev_err_probe(dev, ret, > > + "Failed to set voltage output for %pfwP\n", > > + child); > > + > > + chan_type =3D IIO_VOLTAGE; > > + break; > > + case CH_FUNC_CURRENT_OUTPUT: > > + chan_type =3D IIO_CURRENT; > > + break; > > + default: > > + return dev_err_probe(dev, -EINVAL, > > + "Invalid adi,ch-func %u for %pfwP\n", > > + ch_func, child); > > + } > > + > > + channels[i] =3D ad5710r_channels[reg]; > > + channels[i].type =3D chan_type; > > + i++; > > + > > + reg_offset =3D reg / AD3530R_CH_PER_REG; > > + ch_in_reg =3D reg % AD3530R_CH_PER_REG; > > + mode_reg =3D AD3530R_OUTPUT_OPERATING_MODE_0 + reg_offset; > > + mode_mask =3D AD3530R_OP_MODE_CHAN_MSK(ch_in_reg); > > + > > + /* Enable the channel in normal operation mode */ > > + ret =3D regmap_update_bits(st->regmap, mode_reg, mode_mask, > > + field_prep(mode_mask, AD3530R_NORMAL_OP)); > > + if (ret) > > + return dev_err_probe(dev, ret, > > + "Failed to set normal operating mode for %pfwP\n", > > + child); > > + } > > + > > + st->channels =3D channels; > > + st->num_channels =3D num_chan; > > + > > + return 0; > > +} > > --=20 > With Best Regards, > Andy Shevchenko