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Tue, 11 Aug 2026 13:28:50 -0700 (PDT) Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Tue, 11 Aug 2026 15:28:47 -0500 Message-Id: Subject: Re: [PATCH v3 2/9] iio: adc: add the ti-ads1262 driver From: "Kurt Borja" To: "David Lechner" , "Kurt Borja" , "Jonathan Cameron" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Linus Walleij" , "Bartosz Golaszewski" Cc: =?utf-8?q?Nuno_S=C3=A1?= , "Andy Shevchenko" , , , , X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260807-ads126x-v3-0-f89925d72792@gmail.com> <20260807-ads126x-v3-2-f89925d72792@gmail.com> <7a42a318-780d-4bd0-baf1-55d030b39233@baylibre.com> In-Reply-To: <7a42a318-780d-4bd0-baf1-55d030b39233@baylibre.com> On Mon Aug 10, 2026 at 11:42 AM -05, David Lechner wrote: > On 8/9/26 3:26 AM, Kurt Borja wrote: >> On Sat Aug 8, 2026 at 1:39 PM -05, David Lechner wrote: >>> On 8/7/26 10:58 PM, Kurt Borja wrote: >>>> Add the ti-ads1262 driver with initial support for the primary ADC >>>> (ADC1). The ADS1263 auxiliary ADC (ADC2) is handled by a separate driv= er >>>> and interoperability considerations were taken into account. >>> > > ... > >>>> +static int ads1262_dev_reset(struct ads1262 *st) >>>> +{ >>>> + int ret; >>>> + >>>> + if (st->reset_gpiod) { >>>> + ret =3D gpiod_set_value_cansleep(st->reset_gpiod, 1); >>>> + if (ret) >>>> + return ret; >>>> + >>>> + /* >>>> + * The RESET pulse timing requirement is 4 clock cycles, at the >>>> + * minimum clock rate this is 4 microseconds. >>>> + */ >>>> + fsleep(4); >>> >>> How long do we have to hold reset before the chip powers down? >>=20 >> For power down 65536 clk cycles. Less than that is simple reset. > > How long is 65536 clk cycles in microseconds at the fasted clock rate? > Hopefully won't accidentally shut down the chip here even if fsleep() > goes significantly longer than requested. That would be 8192 microseconds. Do you think there is a risk we end up turning off the device? > >>=20 >> [...] >>=20 >>>> +static int ads1262_wait_for_conversion(struct ads1262 *st) >>>> +{ >>>> + u64 max_lat_ms; >>>> + long ret; >>>> + >>>> + /* >>>> + * The first conversion latency is affected by the channel's data ra= te, >>>> + * filter, the configurable conversion delay and whether chop mode >>>> + * and/or IDAC rotation mode are enabled. >>>> + * >>>> + * The worst possible latency is calculated by taking the lowest dat= a >>>> + * rate (2.5 SPS) and the sinc4 filter. This gives a latency of 1600= ms >>>> + * (Table 9-13). Then we scale it by the actual clock rate and multi= ply >>>> + * by 4 to account for chop and IDAC rotation modes (Equation 20). >>>> + */ >>>> + max_lat_ms =3D 4 * div_u64(mul_u32_u32(1600, 7372800), st->clk_rate)= ; >>> >>> These are constant values, so don't need mul_u32_u32(). Also, given the= wide >>> range of possible sampling rates, I would include the current sampling = rate >>> in the calculation. No need to wate 1.6 seconds for something that shou= ld >>> take a few 10s of microseconds. >>=20 >> Can we leave it like this until I implement the settlingtime? That way I >> can calculate the actual first conversion latency. >>=20 > Sure. Just maybe mention it below the --- in the comment message on the > next revision to remind us. Sure! --=20 Thanks, ~ Kurt