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Mon, 02 Nov 2026 11:44:39 -0800 (PST) Received: from localhost ([151.40.161.170]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e71b80333sm23147608f8f.32.2026.11.02.11.44.38 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 02 Nov 2026 11:44:39 -0800 (PST) X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 02 Nov 2026 20:44:38 +0100 Message-Id: Cc: "Aaro Koskinen" , "Kevin Hilman" , "Roger Quadros" , "Tony Lindgren" , "Rob Herring" , "Krzysztof Kozlowski" , "Conor Dooley" , "Christopher Obbard" , "Andrew Goodbody" , "Paul Walmsley" , "Russell King" , "Rouven Czerwinski" , , , , Subject: Re: [PATCH v2 5/9] ARM: dts: omap: dm816x: Correct speed for sysclk5 From: "Ettore Chimenti" To: "Andreas Kemnade" , "Ettore Chimenti" X-Mailer: aerc 0.22.0-0-gc2f86b7abde3 References: <20261028-patch-ektor5-dm8168-dts-v2-0-4544429251e2@linaro.org> <20261028-patch-ektor5-dm8168-dts-v2-5-4544429251e2@linaro.org> <20261101222942.1a78c6fb@kemnade.info> In-Reply-To: <20261101222942.1a78c6fb@kemnade.info> Hi Andreas, On Sun Nov 1, 2026 at 10:29 PM CET, Andreas Kemnade wrote: > On Wed, 28 Oct 2026 17:06:06 +0100 > Ettore Chimenti wrote: > >> From: Andrew Goodbody >>=20 >> The default code for setting up the clocks results in sysclk5 running at >> 1.6GHz whereas it is expected to run at half that ie 813MHz. Force the >> divider to be /2 to achieve the 813MHz speed. >>=20 >> Signed-off-by: Andrew Goodbody >> Signed-off-by: Ettore Chimenti >> --- >> arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >>=20 >> diff --git a/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi b/arch/arm/boo= t/dts/ti/omap/dm816x-clocks.dtsi >> index 76ebc6c3c3e5..cb990773b098 100644 >> --- a/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi >> +++ b/arch/arm/boot/dts/ti/omap/dm816x-clocks.dtsi >> @@ -144,7 +144,7 @@ sysclk5_ck: sysclk5_ck@310 { >> #clock-cells =3D <0>; >> compatible =3D "ti,divider-clock"; >> clocks =3D <&sysclk4_ck>; >> - ti,max-div =3D <1>; >> + ti,dividers =3D <2>; > > so this changes register value 0 is intepreted as divider 1 > to divider 2. Sounds strange. It just changes the interpretation of the > register values, not the setting. Maybe checkout the register value from > user space with tools like devmem. The original interpretation was right. > So this change does not make any sense. I think sysclk5 still runs at > 1.6Ghz, but it is displayed as 813Mhz. > > I would expect some assigned-clocks / assigned-clock-rates pair somewhere > in this patch instead. > We tested on EVM with devmem and this patch correctly sets bit 0 to 1 (which is /2 in the manual). However, should ti,max-div in this case be <2> (and all the other clocks that supports two dividers)?=20 I tested to set `ti,max-div =3D <2>;` and it seems to correctly set the /2 divider as well, but without specifying any assigned-clock{s,-rates}, so I'm missing the rationale of how the divider is selected. I'll drop this patch from the series for now, I think it needs more investigation to figure out why it behaves like this. Thanks, Ettore