[FOR DISCUSSION 0/9] Dove PMU support

[FOR DISCUSSION 0/9] Dove PMU support

[Russell King - ARM Linux]

This is a re-posting of the patch set which I posted almost 10 months
ago to support the Dove PMU, with a few additional changes.  This set
is based upon 3.19.

In this set are:

* two patches which Rafael originally acked, but there was indecision
  last time around how to handle them due to potential conflicts with
  work that Ulf was doing.  These patches have been updated to apply
  cleanly to 3.19.  I don't know if people want to take these as
  fixes to the PM domain code or not (hence why I'm posting this
  series during the merge window - if it weren't for this, I'd hold
  it off.)

* what I regard as a fix to the PM domain code; as a result of a
  previous commit, the PM domain code mismatches the runtime PM state,
  which leads to the PM domain being unexpectedly left on.  This patch
  has been re-worked to try an alternative approach, syncing the PM
  domain state with the runtime PM state after the probe has completed.

* the addition of the core Dove PMU driver, which consists of a reset,
  IRQ controller, and power domains.  The reset and power domain code
  has to be closely related due to the power up/down requirements of
  the GPU/VPU subsystems needing to be performed atomically.  (This
  requirement prevents it using the MFD infrastructure, because we
  would need to hold spinlocks while calling several different
  sub-drivers.)

* addition of the RTC interrupt, so we can now receive and act on
  alarms generated by the Dove RTC.

* addition of the DT descriptions for the GPU and VPU power domains.
  These patches do not themselves add the DT descriptions for these
  units, so these patches serve as illustrations how these should be
  described.

I've also included the DT binding documentation as a separate patch this
time around, and moved the PMU driver to drivers/soc/dove.

There are some gotchas with it - PM domains need to be created prior
to any device which uses them being probed, so it is best if the driver
is initialised early in the kernel boot.  We may be able to get away
with a core_initcall() or a postcore_initcall().

I'd ideally like to get these queued for merging in the _next_ merge
window if at all possible, if only to reduce the number of patches I've
been carrying for the last few years.  Failing that, if at least the
patches which Rafael has already acked could be applied, that would at
least get /some/ form of forward progress.

 Documentation/devicetree/bindings/soc/dove/pmu.txt |  49 +++
 arch/arm/boot/dts/dove.dtsi                        |  25 ++
 arch/arm/mach-mvebu/Kconfig                        |   1 +
 drivers/base/platform.c                            |   2 +
 drivers/base/power/common.c                        |  15 +
 drivers/base/power/domain.c                        |  33 +-
 drivers/soc/Makefile                               |   1 +
 drivers/soc/dove/Makefile                          |   1 +
 drivers/soc/dove/pmu.c                             | 399 +++++++++++++++++++++
 include/linux/pm.h                                 |   1 +
 include/linux/pm_domain.h                          |   4 +
 include/linux/soc/dove/pmu.h                       |   6 +
 12 files changed, 532 insertions(+), 5 deletions(-)

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[PATCH 4/9] dt-bindings: add Marvell PMU documentation

[Russell King]

Add the required DT binding documentation for the Marvell PMU driver.

Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
---
 Documentation/devicetree/bindings/soc/dove/pmu.txt | 49 ++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/dove/pmu.txt

diff --git a/Documentation/devicetree/bindings/soc/dove/pmu.txt b/Documentation/devicetree/bindings/soc/dove/pmu.txt
new file mode 100644
index 000000000000..9617aa298dd4
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/dove/pmu.txt
@@ -0,0 +1,49 @@
+Device Tree bindings for Marvell PMU
+
+Required properties:
+ - compatible: value should be "marvell,dove-pmu".
+ - reg: two base addresses and sizes of the PM controller and PMU.
+ - interrupts: single interrupt number for the PMU interrupt
+ - interrupt-controller: must be specified as the PMU itself is an
+    interrupt controller.
+ - #interrupt-cells: must be 1.
+ - #reset-cells: must be 1.
+
+Optional properties:
+ - None
+
+Domain descriptions are listed as child nodes of the power management
+node.  Each domain has the following properties:
+
+Required properties:
+ - #power-domain-cells: must be 0.
+
+Optional properties:
+ - marvell,pmu_pwr_mask: specifies the mask value for PMU power register
+ - marvell,pmu_iso_mask: specifies the mask value for PMU isolation register
+ - resets: points to the reset manager (PMU node) and reset index.
+
+Example:
+
+	pmu: power-management@d0000 {
+		compatible = "marvell,dove-pmu";
+		reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
+		interrupts = <33>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		#reset-cells = <1>;
+
+		vpu_domain: vpu-domain {
+			#power-domain-cells = <0>;
+			marvell,pmu_pwr_mask = <0x00000008>;
+			marvell,pmu_iso_mask = <0x00000001>;
+			resets = <&pmu 16>;
+		};
+
+		gpu_domain: gpu-domain {
+			#power-domain-cells = <0>;
+			marvell,pmu_pwr_mask = <0x00000004>;
+			marvell,pmu_iso_mask = <0x00000002>;
+			resets = <&pmu 18>;
+		};
+	};
-- 
1.8.3.1

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Re: [PATCH 4/9] dt-bindings: add Marvell PMU documentation

[Rob Herring]

On Thu, Mar 12, 2015 at 1:31 PM, Russell King
<rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> wrote:
> Add the required DT binding documentation for the Marvell PMU driver.
>
> Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
> ---
>  Documentation/devicetree/bindings/soc/dove/pmu.txt | 49 ++++++++++++++++++++++
>  1 file changed, 49 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/dove/pmu.txt
>
> diff --git a/Documentation/devicetree/bindings/soc/dove/pmu.txt b/Documentation/devicetree/bindings/soc/dove/pmu.txt
> new file mode 100644
> index 000000000000..9617aa298dd4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/dove/pmu.txt
> @@ -0,0 +1,49 @@
> +Device Tree bindings for Marvell PMU
> +
> +Required properties:
> + - compatible: value should be "marvell,dove-pmu".
> + - reg: two base addresses and sizes of the PM controller and PMU.
> + - interrupts: single interrupt number for the PMU interrupt
> + - interrupt-controller: must be specified as the PMU itself is an
> +    interrupt controller.

Is it always an interrupt controller or just in low power modes like
ones typically tacked on to GICs?

> + - #interrupt-cells: must be 1.
> + - #reset-cells: must be 1.
> +
> +Optional properties:
> + - None
> +
> +Domain descriptions are listed as child nodes of the power management

"Power domain descriptions..." just to be clear.

> +node.  Each domain has the following properties:
> +
> +Required properties:
> + - #power-domain-cells: must be 0.
> +
> +Optional properties:
> + - marvell,pmu_pwr_mask: specifies the mask value for PMU power register
> + - marvell,pmu_iso_mask: specifies the mask value for PMU isolation register
> + - resets: points to the reset manager (PMU node) and reset index.
> +
> +Example:
> +
> +       pmu: power-management@d0000 {
> +               compatible = "marvell,dove-pmu";
> +               reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
> +               interrupts = <33>;
> +               interrupt-controller;
> +               #interrupt-cells = <1>;
> +               #reset-cells = <1>;
> +
> +               vpu_domain: vpu-domain {
> +                       #power-domain-cells = <0>;
> +                       marvell,pmu_pwr_mask = <0x00000008>;
> +                       marvell,pmu_iso_mask = <0x00000001>;
> +                       resets = <&pmu 16>;
> +               };
> +
> +               gpu_domain: gpu-domain {
> +                       #power-domain-cells = <0>;
> +                       marvell,pmu_pwr_mask = <0x00000004>;
> +                       marvell,pmu_iso_mask = <0x00000002>;
> +                       resets = <&pmu 18>;
> +               };
> +       };
> --
> 1.8.3.1
>
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Re: [PATCH 4/9] dt-bindings: add Marvell PMU documentation

[Russell King - ARM Linux]

On Thu, Mar 12, 2015 at 04:32:07PM -0500, Rob Herring wrote:
> On Thu, Mar 12, 2015 at 1:31 PM, Russell King
> <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> wrote:
> > Add the required DT binding documentation for the Marvell PMU driver.
> >
> > Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
> > ---
> >  Documentation/devicetree/bindings/soc/dove/pmu.txt | 49 ++++++++++++++++++++++
> >  1 file changed, 49 insertions(+)
> >  create mode 100644 Documentation/devicetree/bindings/soc/dove/pmu.txt
> >
> > diff --git a/Documentation/devicetree/bindings/soc/dove/pmu.txt b/Documentation/devicetree/bindings/soc/dove/pmu.txt
> > new file mode 100644
> > index 000000000000..9617aa298dd4
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/soc/dove/pmu.txt
> > @@ -0,0 +1,49 @@
> > +Device Tree bindings for Marvell PMU
> > +
> > +Required properties:
> > + - compatible: value should be "marvell,dove-pmu".
> > + - reg: two base addresses and sizes of the PM controller and PMU.
> > + - interrupts: single interrupt number for the PMU interrupt
> > + - interrupt-controller: must be specified as the PMU itself is an
> > +    interrupt controller.
> 
> Is it always an interrupt controller or just in low power modes like
> ones typically tacked on to GICs?

Always.  It's an interrupt controller: it takes interrupts from other
parts of the system with individual status and masks, and forwards it
on as a single interrupt input to the upstream interrupt controller.

> > + - #interrupt-cells: must be 1.
> > + - #reset-cells: must be 1.
> > +
> > +Optional properties:
> > + - None
> > +
> > +Domain descriptions are listed as child nodes of the power management
> 
> "Power domain descriptions..." just to be clear.

Ok.

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Re: [PATCH 4/9] dt-bindings: add Marvell PMU documentation

[Arnd Bergmann]

On Thursday 12 March 2015 18:31:10 Russell King wrote:
> Add the required DT binding documentation for the Marvell PMU driver.
> 
> Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
> 

The binding and DT nodes look ok to me, I'm definitely fine
with taking those through the arm-soc tree, regardless of how
we merge the other changes. The actual driver should probably
go the same way, unless you want to put them in a branch with
the drivers/base changes and have them merged through Rafael's
tree.

Who is picking up patches for mach-dove at the moment? I
know that Gregory Clement has taken over the mvebu git tree
from Jason for the time being, but he's not listed as a maintainer
for dove/mv78xx0/orion and wasn't on Cc to these mails as a
consequence (I've added him for the discussion here).

	Arnd
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[PATCH 6/9] ARM: dt: dove: add Dove PMU DT entry to dove.dtsi

[Russell King]

Add the PMU description to the Dove DT file.  The PMU provides multiple
features, including an interrupt, reset, power and isolation controller.

Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
---
 arch/arm/boot/dts/dove.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index a5441d5482a6..43d4ebf414be 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -380,6 +380,15 @@
 				status = "disabled";
 			};
 
+			pmu: power-management@d0000 {
+				compatible = "marvell,dove-pmu";
+				reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
+				interrupts = <33>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				#reset-cells = <1>;
+			};
+
 			thermal: thermal-diode@d001c {
 				compatible = "marvell,dove-thermal";
 				reg = <0xd001c 0x0c>, <0xd005c 0x08>;
-- 
1.8.3.1

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Re: [PATCH 6/9] ARM: dt: dove: add Dove PMU DT entry to dove.dtsi

[Thomas Petazzoni]

Dear Russell King,

On Thu, 12 Mar 2015 18:31:21 +0000, Russell King wrote:

> +			pmu: power-management@d0000 {
> +				compatible = "marvell,dove-pmu";
> +				reg = <0xd0000 0x8000>, <0xd8000 0x8000>;

If I'm not wrong, the registers of the RTC are at 0xd8500, which is
also covered by this new pmu node. It does work because you're using
of_iomap(), but it isn't really ideal.

Maybe some sort of syscon/regmap thing should be used?

Best regards,

Thomas
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Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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Re: [PATCH 6/9] ARM: dt: dove: add Dove PMU DT entry to dove.dtsi

[Russell King - ARM Linux]

On Fri, Mar 13, 2015 at 01:30:38PM +0100, Thomas Petazzoni wrote:
> Dear Russell King,
> 
> On Thu, 12 Mar 2015 18:31:21 +0000, Russell King wrote:
> 
> > +			pmu: power-management@d0000 {
> > +				compatible = "marvell,dove-pmu";
> > +				reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
> 
> If I'm not wrong, the registers of the RTC are at 0xd8500, which is
> also covered by this new pmu node. It does work because you're using
> of_iomap(), but it isn't really ideal.
> 
> Maybe some sort of syscon/regmap thing should be used?

Please look at the locking that would require and the locking required
for PM domains (and as I've previously explained, apparently the hardware
requires a specific sequence of writes.)

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Re: [PATCH 6/9] ARM: dt: dove: add Dove PMU DT entry to dove.dtsi

[Gregory CLEMENT]

Hi Russell,

On 12/03/2015 19:31, Russell King wrote:
> Add the PMU description to the Dove DT file.  The PMU provides multiple
> features, including an interrupt, reset, power and isolation controller.
> 
> Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
> ---
>  arch/arm/boot/dts/dove.dtsi | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
> index a5441d5482a6..43d4ebf414be 100644
> --- a/arch/arm/boot/dts/dove.dtsi
> +++ b/arch/arm/boot/dts/dove.dtsi
> @@ -380,6 +380,15 @@
>  				status = "disabled";
>  			};
>  
> +			pmu: power-management@d0000 {
> +				compatible = "marvell,dove-pmu";
> +				reg = <0xd0000 0x8000>, <0xd8000 0x8000>;

Here you overlap some other nodes such as the thermal one (from 0xd001c to 0xd0028),
the clock gate one (from 0xd0038 to 0xd003c), the gpio one, the pinctrl one ...

Could you be more specific?

Thanks,

Gregory

> +				interrupts = <33>;
> +				interrupt-controller;
> +				#interrupt-cells = <1>;
> +				#reset-cells = <1>;
> +			};
> +
>  			thermal: thermal-diode@d001c {
>  				compatible = "marvell,dove-thermal";
>  				reg = <0xd001c 0x0c>, <0xd005c 0x08>;
> 


-- 
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development, consulting, training and support.
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Re: [PATCH 6/9] ARM: dt: dove: add Dove PMU DT entry to dove.dtsi

[Russell King - ARM Linux]

On Mon, Mar 16, 2015 at 07:27:30PM +0100, Gregory CLEMENT wrote:
> > +			pmu: power-management@d0000 {
> > +				compatible = "marvell,dove-pmu";
> > +				reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
> 
> Here you overlap some other nodes such as the thermal one (from 0xd001c
> to 0xd0028), the clock gate one (from 0xd0038 to 0xd003c), the gpio one,
> the pinctrl one ...

Yes, I'm well aware of that, but here's the thing...

I'm describing the hardware here.

The real problem is that Dove (etc) went down the path of breaking up
the PMU device into multiple smaller devices each specifying a sub-set
of the register range.  By doing that, Dove moved away from describing
the hardware - instead, we've described the Linux _implementation_ with
its separate (sub-)devices - its the implementation's choice that we'd
break up the PMU into these separate devices, almost to the point of
specifying each individual register.

What could be done to work around this oversight is to mvoe these
devices beneath the PMU node, which IMHO makes complete sense as these
are sub-devices of the PMU/PMC rather than separate devices.

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Re: [PATCH 6/9] ARM: dt: dove: add Dove PMU DT entry to dove.dtsi

[Sebastian Hesselbarth]

On 03/17/2015 02:43 PM, Russell King - ARM Linux wrote:
> On Mon, Mar 16, 2015 at 07:27:30PM +0100, Gregory CLEMENT wrote:
>>> +			pmu: power-management@d0000 {
>>> +				compatible = "marvell,dove-pmu";
>>> +				reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
>>
>> Here you overlap some other nodes such as the thermal one (from 0xd001c
>> to 0xd0028), the clock gate one (from 0xd0038 to 0xd003c), the gpio one,
>> the pinctrl one ...
>
> Yes, I'm well aware of that, but here's the thing...
>
> I'm describing the hardware here.
>
> The real problem is that Dove (etc) went down the path of breaking up
> the PMU device into multiple smaller devices each specifying a sub-set
> of the register range.  By doing that, Dove moved away from describing

Russell,

I totally agree that from today's point-of-view having a single pmu
node with sub-nodes would have been the better approach.

> the hardware - instead, we've described the Linux _implementation_ with
> its separate (sub-)devices - its the implementation's choice that we'd
> break up the PMU into these separate devices, almost to the point of
> specifying each individual register.
>
> What could be done to work around this oversight is to mvoe these
> devices beneath the PMU node, which IMHO makes complete sense as these
> are sub-devices of the PMU/PMC rather than separate devices.

If we do this, we should have a look at syscon and potentially also
simple-mfd which will allow us to share the registers and register
platform_devices for the sub-nodes.

The current pmu power/reset/irq can still use the extra locking
and directly access MMIO registers - but for the others we should
really look into using regmaps.

The only thing here is that power domain descriptions are also encoded
as direct sub-nodes of the pmu node, right?

Sebastian


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Re: [PATCH 6/9] ARM: dt: dove: add Dove PMU DT entry to dove.dtsi

[Russell King - ARM Linux]

On Tue, Mar 17, 2015 at 04:09:19PM +0100, Sebastian Hesselbarth wrote:
> If we do this, we should have a look at syscon and potentially also
> simple-mfd which will allow us to share the registers and register
> platform_devices for the sub-nodes.
> 
> The current pmu power/reset/irq can still use the extra locking
> and directly access MMIO registers - but for the others we should
> really look into using regmaps.
> 
> The only thing here is that power domain descriptions are also encoded
> as direct sub-nodes of the pmu node, right?

Yes, I've been debating about putting those under a domains { } sub-node,
like we do with the ports { } sub-node for of-graph stuff.

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Re: [PATCH 6/9] ARM: dt: dove: add Dove PMU DT entry to dove.dtsi

[Linus Walleij]

On Tue, Mar 17, 2015 at 4:09 PM, Sebastian Hesselbarth
<sebastian.hesselbarth-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:

> If we do this, we should have a look at syscon and potentially also
> simple-mfd which will allow us to share the registers and register
> platform_devices for the sub-nodes.

I've just sent a pull request for simple-mfd to the ARM SoC
maintainers. I see that you Free Electron guys make good use
of it.

Yours,
Linus Walleij
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[PATCH 7/9] ARM: dt: dove: wire up RTC interrupt

[Russell King]

Now that we have a PMU driver, we can wire up the RTC interrupt in the
DT description for Dove.

Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
---
 arch/arm/boot/dts/dove.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 43d4ebf414be..7e80407bdcf8 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -624,6 +624,8 @@
 			rtc: real-time-clock@d8500 {
 				compatible = "marvell,orion-rtc";
 				reg = <0xd8500 0x20>;
+				interrupt-parent = <&pmu>;
+				interrupts = <5>;
 			};
 
 			gconf: global-config@e802c {
-- 
1.8.3.1

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[PATCH 8/9] ARM: dt: dove: add video decoder power domain description

[Russell King]

Add the description of the video decoder power domain to the PMU DT
entry.

Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
---
 arch/arm/boot/dts/dove.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 7e80407bdcf8..3dcf5322bf0e 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -387,6 +387,13 @@
 				interrupt-controller;
 				#interrupt-cells = <1>;
 				#reset-cells = <1>;
+
+				vpu_domain: vpu-domain {
+					#power-domain-cells = <0>;
+					marvell,pmu_pwr_mask = <0x00000008>;
+					marvell,pmu_iso_mask = <0x00000001>;
+					resets = <&pmu 16>;
+				};
 			};
 
 			thermal: thermal-diode@d001c {
-- 
1.8.3.1

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[PATCH 9/9] ARM: dt: dove: add GPU power domain description

[Russell King]

Add the description of the GPU power domain to the PMU DT entry.

Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
---
 arch/arm/boot/dts/dove.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 3dcf5322bf0e..d273552ada8a 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -394,6 +394,13 @@
 					marvell,pmu_iso_mask = <0x00000001>;
 					resets = <&pmu 16>;
 				};
+
+				gpu_domain: gpu-domain {
+					#power-domain-cells = <0>;
+					marvell,pmu_pwr_mask = <0x00000004>;
+					marvell,pmu_iso_mask = <0x00000002>;
+					resets = <&pmu 18>;
+				};
 			};
 
 			thermal: thermal-diode@d001c {
-- 
1.8.3.1

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Re: [FOR DISCUSSION 0/9] Dove PMU support

[Arnd Bergmann]

On Thursday 12 March 2015 18:30:21 Russell King - ARM Linux wrote:
> This is a re-posting of the patch set which I posted almost 10 months
> ago to support the Dove PMU, with a few additional changes.  This set
> is based upon 3.19.
> 
> In this set are:
> 
> * two patches which Rafael originally acked, but there was indecision
>   last time around how to handle them due to potential conflicts with
>   work that Ulf was doing.  These patches have been updated to apply
>   cleanly to 3.19.  I don't know if people want to take these as
>   fixes to the PM domain code or not (hence why I'm posting this
>   series during the merge window - if it weren't for this, I'd hold
>   it off.)

I don't seem to have received the first three patches for some reason.
Can you check if you got them back from the mailing list?

> 
>  Documentation/devicetree/bindings/soc/dove/pmu.txt |  49 +++
>  arch/arm/boot/dts/dove.dtsi                        |  25 ++
>  arch/arm/mach-mvebu/Kconfig                        |   1 +
>  drivers/base/platform.c                            |   2 +
>  drivers/base/power/common.c                        |  15 +
>  drivers/base/power/domain.c                        |  33 +-
>  drivers/soc/Makefile                               |   1 +
>  drivers/soc/dove/Makefile                          |   1 +
>  drivers/soc/dove/pmu.c                             | 399 +++++++++++++++++++++
>  include/linux/pm.h                                 |   1 +
>  include/linux/pm_domain.h                          |   4 +
>  include/linux/soc/dove/pmu.h                       |   6 +
>  12 files changed, 532 insertions(+), 5 deletions(-)

I see add the header file and the global dove_init_pmu() function,
but I don't see a caller of that function. Is that intentional, or
did you accidentally leave out another patch that you meant to include?

	Arnd
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Re: [FOR DISCUSSION 0/9] Dove PMU support

[Russell King - ARM Linux]

On Fri, Mar 13, 2015 at 12:57:11PM +0100, Arnd Bergmann wrote:
> On Thursday 12 March 2015 18:30:21 Russell King - ARM Linux wrote:
> > This is a re-posting of the patch set which I posted almost 10 months
> > ago to support the Dove PMU, with a few additional changes.  This set
> > is based upon 3.19.
> > 
> > In this set are:
> > 
> > * two patches which Rafael originally acked, but there was indecision
> >   last time around how to handle them due to potential conflicts with
> >   work that Ulf was doing.  These patches have been updated to apply
> >   cleanly to 3.19.  I don't know if people want to take these as
> >   fixes to the PM domain code or not (hence why I'm posting this
> >   series during the merge window - if it weren't for this, I'd hold
> >   it off.)
> 
> I don't seem to have received the first three patches for some reason.
> Can you check if you got them back from the mailing list?

That's because you're not listed as the maintainer for PM domain stuff,
and I forgot to ensure lakml was copied on all patches.

> >  Documentation/devicetree/bindings/soc/dove/pmu.txt |  49 +++
> >  arch/arm/boot/dts/dove.dtsi                        |  25 ++
> >  arch/arm/mach-mvebu/Kconfig                        |   1 +
> >  drivers/base/platform.c                            |   2 +
> >  drivers/base/power/common.c                        |  15 +
> >  drivers/base/power/domain.c                        |  33 +-
> >  drivers/soc/Makefile                               |   1 +
> >  drivers/soc/dove/Makefile                          |   1 +
> >  drivers/soc/dove/pmu.c                             | 399 +++++++++++++++++++++
> >  include/linux/pm.h                                 |   1 +
> >  include/linux/pm_domain.h                          |   4 +
> >  include/linux/soc/dove/pmu.h                       |   6 +
> >  12 files changed, 532 insertions(+), 5 deletions(-)
> 
> I see add the header file and the global dove_init_pmu() function,
> but I don't see a caller of that function. Is that intentional, or
> did you accidentally leave out another patch that you meant to include?

I kind'a did - it needs an explicit call from arch/arm/mach-mvebu/dove.c
which I haven't added even in my tree (because I don't use that path,
even when I test DT booting - I still use most of the arch/arm/mach-dove
code when DT booting.)  I'll add that now.

Of course, I also have a patch which adds legacy support to
arch/arm/mach-dove, but I've assumed you're not interested in that...

-- 
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Re: [FOR DISCUSSION 0/9] Dove PMU support

[Arnd Bergmann]

On Friday 13 March 2015 12:11:27 Russell King - ARM Linux wrote:
> On Fri, Mar 13, 2015 at 12:57:11PM +0100, Arnd Bergmann wrote:
> > On Thursday 12 March 2015 18:30:21 Russell King - ARM Linux wrote:
> > >  Documentation/devicetree/bindings/soc/dove/pmu.txt |  49 +++
> > >  arch/arm/boot/dts/dove.dtsi                        |  25 ++
> > >  arch/arm/mach-mvebu/Kconfig                        |   1 +
> > >  drivers/base/platform.c                            |   2 +
> > >  drivers/base/power/common.c                        |  15 +
> > >  drivers/base/power/domain.c                        |  33 +-
> > >  drivers/soc/Makefile                               |   1 +
> > >  drivers/soc/dove/Makefile                          |   1 +
> > >  drivers/soc/dove/pmu.c                             | 399 +++++++++++++++++++++
> > >  include/linux/pm.h                                 |   1 +
> > >  include/linux/pm_domain.h                          |   4 +
> > >  include/linux/soc/dove/pmu.h                       |   6 +
> > >  12 files changed, 532 insertions(+), 5 deletions(-)
> > 
> > I see add the header file and the global dove_init_pmu() function,
> > but I don't see a caller of that function. Is that intentional, or
> > did you accidentally leave out another patch that you meant to include?
> 
> I kind'a did - it needs an explicit call from arch/arm/mach-mvebu/dove.c
> which I haven't added even in my tree (because I don't use that path,
> even when I test DT booting - I still use most of the arch/arm/mach-dove
> code when DT booting.)  I'll add that now.
> 
> Of course, I also have a patch which adds legacy support to
> arch/arm/mach-dove, but I've assumed you're not interested in that...

You mean legacy support in mach-mvebu?

I don't mind that at all, it was the mvebu maintainers that decided
it would be best to combine the multiplatform and DT work in order
to simplify both. I've also sent a patch set that moves mach-dove
into multiplatform, which is a different way of doing the same thing.

	Arnd

Re: [FOR DISCUSSION 0/9] Dove PMU support

[Russell King - ARM Linux]

On Fri, Mar 13, 2015 at 01:26:17PM +0100, Arnd Bergmann wrote:
> On Friday 13 March 2015 12:11:27 Russell King - ARM Linux wrote:
> > On Fri, Mar 13, 2015 at 12:57:11PM +0100, Arnd Bergmann wrote:
> > > On Thursday 12 March 2015 18:30:21 Russell King - ARM Linux wrote:
> > > >  Documentation/devicetree/bindings/soc/dove/pmu.txt |  49 +++
> > > >  arch/arm/boot/dts/dove.dtsi                        |  25 ++
> > > >  arch/arm/mach-mvebu/Kconfig                        |   1 +
> > > >  drivers/base/platform.c                            |   2 +
> > > >  drivers/base/power/common.c                        |  15 +
> > > >  drivers/base/power/domain.c                        |  33 +-
> > > >  drivers/soc/Makefile                               |   1 +
> > > >  drivers/soc/dove/Makefile                          |   1 +
> > > >  drivers/soc/dove/pmu.c                             | 399 +++++++++++++++++++++
> > > >  include/linux/pm.h                                 |   1 +
> > > >  include/linux/pm_domain.h                          |   4 +
> > > >  include/linux/soc/dove/pmu.h                       |   6 +
> > > >  12 files changed, 532 insertions(+), 5 deletions(-)
> > > 
> > > I see add the header file and the global dove_init_pmu() function,
> > > but I don't see a caller of that function. Is that intentional, or
> > > did you accidentally leave out another patch that you meant to include?
> > 
> > I kind'a did - it needs an explicit call from arch/arm/mach-mvebu/dove.c
> > which I haven't added even in my tree (because I don't use that path,
> > even when I test DT booting - I still use most of the arch/arm/mach-dove
> > code when DT booting.)  I'll add that now.
> > 
> > Of course, I also have a patch which adds legacy support to
> > arch/arm/mach-dove, but I've assumed you're not interested in that...
> 
> You mean legacy support in mach-mvebu?

No.

As you'll see, this uses a platform device notifier to hook the devices
onto the appropriate PM domain, which is why the driver needs to be
registered early.  This also gets used in DT mode with one legacy
platform device which is dynamically registered (something which can't
happen with DT.)

 arch/arm/Kconfig                     |  1 +
 arch/arm/mach-dove/common.c          | 25 ++++++++++
 arch/arm/mach-dove/include/mach/pm.h | 17 -------
 arch/arm/mach-dove/irq.c             | 87 --------------------------------
 drivers/soc/Makefile                 |  1 +
 drivers/soc/dove/pmu.c               | 97 ++++++++++++++++++++++++++++++++++++
 include/linux/soc/dove/pmu.h         | 18 +++++++
 7 files changed, 142 insertions(+), 104 deletions(-)

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 97d07ed60a0b..08e7608d1c52 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -519,6 +519,7 @@ config ARCH_DOVE
 	select PINCTRL
 	select PINCTRL_DOVE
 	select PLAT_ORION_LEGACY
+	select PM_GENERIC_DOMAINS if PM
 	help
 	  Support for the Marvell Dove SoC 88AP510
 
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 0d1a89298ece..6f3887217674 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -16,6 +16,7 @@
 #include <linux/platform_data/dma-mv_xor.h>
 #include <linux/platform_data/usb-ehci-orion.h>
 #include <linux/platform_device.h>
+#include <linux/soc/dove/pmu.h>
 #include <asm/hardware/cache-tauros2.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
@@ -375,6 +376,29 @@ void __init dove_setup_cpu_wins(void)
 				    DOVE_SCRATCHPAD_SIZE);
 }
 
+static const struct dove_pmu_domain_initdata pmu_domains[] __initconst = {
+	{
+		.pwr_mask = PMU_PWR_VPU_PWR_DWN_MASK,
+		.rst_mask = PMU_SW_RST_VIDEO_MASK,
+		.iso_mask = PMU_ISO_VIDEO_MASK,
+		.name = "vpu-domain",
+	}, {
+		.pwr_mask = PMU_PWR_GPU_PWR_DWN_MASK,
+		.rst_mask = PMU_SW_RST_GPU_MASK,
+		.iso_mask = PMU_ISO_GPU_MASK,
+		.name = "gpu-domain",
+	}, {
+		/* sentinel */
+	},
+};
+
+static const struct dove_pmu_initdata pmu_data __initconst = {
+	.pmc_base = DOVE_PMU_VIRT_BASE,
+	.pmu_base = DOVE_PMU_VIRT_BASE + 0x8000,
+	.irq = IRQ_DOVE_PMU,
+	.domains = pmu_domains,
+};
+
 void __init dove_init(void)
 {
 	pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
@@ -389,6 +413,7 @@ void __init dove_init(void)
 	dove_clk_init();
 
 	/* internal devices that every board has */
+	dove_init_pmu_legacy(&pmu_data);
 	dove_rtc_init();
 	dove_xor0_init();
 	dove_xor1_init();
diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h
index b47f75038686..625a89c15c1f 100644
--- a/arch/arm/mach-dove/include/mach/pm.h
+++ b/arch/arm/mach-dove/include/mach/pm.h
@@ -51,22 +51,5 @@
 #define  CLOCK_GATING_GIGA_PHY_MASK	(1 << CLOCK_GATING_BIT_GIGA_PHY)
 
 #define PMU_INTERRUPT_CAUSE	(DOVE_PMU_VIRT_BASE + 0x50)
-#define PMU_INTERRUPT_MASK	(DOVE_PMU_VIRT_BASE + 0x54)
-
-static inline int pmu_to_irq(int pin)
-{
-	if (pin < NR_PMU_IRQS)
-		return pin + IRQ_DOVE_PMU_START;
-
-	return -EINVAL;
-}
-
-static inline int irq_to_pmu(int irq)
-{
-	if (IRQ_DOVE_PMU_START <= irq && irq < NR_IRQS)
-		return irq - IRQ_DOVE_PMU_START;
-
-	return -EINVAL;
-}
 
 #endif
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index 4a5a7aedcb76..924d8afe4597 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -7,86 +7,14 @@
  * License version 2.  This program is licensed "as is" without any
  * warranty of any kind, whether express or implied.
  */
-
-#include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/irq.h>
-#include <linux/gpio.h>
 #include <linux/io.h>
-#include <asm/mach/arch.h>
 #include <plat/irq.h>
-#include <asm/mach/irq.h>
-#include <mach/pm.h>
 #include <mach/bridge-regs.h>
 #include <plat/orion-gpio.h>
 #include "common.h"
 
-static void pmu_irq_mask(struct irq_data *d)
-{
-	int pin = irq_to_pmu(d->irq);
-	u32 u;
-
-	u = readl(PMU_INTERRUPT_MASK);
-	u &= ~(1 << (pin & 31));
-	writel(u, PMU_INTERRUPT_MASK);
-}
-
-static void pmu_irq_unmask(struct irq_data *d)
-{
-	int pin = irq_to_pmu(d->irq);
-	u32 u;
-
-	u = readl(PMU_INTERRUPT_MASK);
-	u |= 1 << (pin & 31);
-	writel(u, PMU_INTERRUPT_MASK);
-}
-
-static void pmu_irq_ack(struct irq_data *d)
-{
-	int pin = irq_to_pmu(d->irq);
-	u32 u;
-
-	/*
-	 * The PMU mask register is not RW0C: it is RW.  This means that
-	 * the bits take whatever value is written to them; if you write
-	 * a '1', you will set the interrupt.
-	 *
-	 * Unfortunately this means there is NO race free way to clear
-	 * these interrupts.
-	 *
-	 * So, let's structure the code so that the window is as small as
-	 * possible.
-	 */
-	u = ~(1 << (pin & 31));
-	u &= readl_relaxed(PMU_INTERRUPT_CAUSE);
-	writel_relaxed(u, PMU_INTERRUPT_CAUSE);
-}
-
-static struct irq_chip pmu_irq_chip = {
-	.name		= "pmu_irq",
-	.irq_mask	= pmu_irq_mask,
-	.irq_unmask	= pmu_irq_unmask,
-	.irq_ack	= pmu_irq_ack,
-};
-
-static void pmu_irq_handler(unsigned int irq, struct irq_desc *desc)
-{
-	unsigned long cause = readl(PMU_INTERRUPT_CAUSE);
-
-	cause &= readl(PMU_INTERRUPT_MASK);
-	if (cause == 0) {
-		do_bad_IRQ(irq, desc);
-		return;
-	}
-
-	for (irq = 0; irq < NR_PMU_IRQS; irq++) {
-		if (!(cause & (1 << irq)))
-			continue;
-		irq = pmu_to_irq(irq);
-		generic_handle_irq(irq);
-	}
-}
-
 static int __initdata gpio0_irqs[4] = {
 	IRQ_DOVE_GPIO_0_7,
 	IRQ_DOVE_GPIO_8_15,
@@ -142,8 +70,6 @@ __exception_irq_entry dove_legacy_handle_irq(struct pt_regs *regs)
 
 void __init dove_init_irq(void)
 {
-	int i;
-
 	orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
 	orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
 
@@ -162,17 +88,4 @@ void __init dove_init_irq(void)
 
 	orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
 			IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
-
-	/*
-	 * Mask and clear PMU interrupts
-	 */
-	writel(0, PMU_INTERRUPT_MASK);
-	writel(0, PMU_INTERRUPT_CAUSE);
-
-	for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
-		irq_set_chip_and_handler(i, &pmu_irq_chip, handle_level_irq);
-		irq_set_status_flags(i, IRQ_LEVEL);
-		set_irq_flags(i, IRQF_VALID);
-	}
-	irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
 }
diff --git a/drivers/soc/Makefile b/drivers/soc/Makefile
index 7382bfe92743..0e2b360c57d2 100644
--- a/drivers/soc/Makefile
+++ b/drivers/soc/Makefile
@@ -2,6 +2,7 @@
 # Makefile for the Linux Kernel SOC specific device drivers.
 #
 
+obj-$(CONFIG_ARCH_DOVE)		+= dove/
 obj-$(CONFIG_MACH_DOVE)		+= dove/
 obj-$(CONFIG_ARCH_QCOM)		+= qcom/
 obj-$(CONFIG_ARCH_TEGRA)	+= tegra/
diff --git a/drivers/soc/dove/pmu.c b/drivers/soc/dove/pmu.c
index 41539743ecf9..3f6a43fce8d3 100644
--- a/drivers/soc/dove/pmu.c
+++ b/drivers/soc/dove/pmu.c
@@ -305,6 +305,103 @@ static int __init dove_init_pmu_irq(struct pmu_data *pmu, int irq)
 	return 0;
 }
 
+static void pmu_add_genpd_name(const char *name, struct device *dev)
+{
+	while (1) {
+		if (pm_genpd_name_add_device(name, dev) != -EAGAIN)
+			break;
+		cond_resched();
+	}
+}
+
+static void pmu_remove_genpd(struct device *dev)
+{
+	struct generic_pm_domain *genpd = dev_to_genpd(dev);
+
+	while (1) {
+		if (pm_genpd_remove_device(genpd, dev) != -EAGAIN)
+			break;
+		cond_resched();
+	}
+}
+
+static int pmu_platform_call(struct notifier_block *nb,
+	unsigned long event, void *data)
+{
+	struct device *dev = data;
+	const char *name = NULL;
+
+	if (dev->of_node)
+		return NOTIFY_OK;
+
+	if (strcmp(dev_name(dev), "ap510-vmeta.0") == 0 ||
+	    strcmp(dev_name(dev), "ap510-vmeta") == 0)
+		name = "vpu-domain";
+	else if (strcmp(dev_name(dev), "galcore.0") == 0)
+		name = "gpu-domain";
+
+	switch (event) {
+	case BUS_NOTIFY_ADD_DEVICE:
+		if (name)
+			pmu_add_genpd_name(name, dev);
+		break;
+
+	case BUS_NOTIFY_DEL_DEVICE:
+		pmu_remove_genpd(dev);
+		break;
+	}
+	return NOTIFY_OK;
+}
+
+static struct notifier_block platform_nb = {
+	.notifier_call = pmu_platform_call,
+};
+
+int __init dove_init_pmu_legacy(const struct dove_pmu_initdata *initdata)
+{
+	const struct dove_pmu_domain_initdata *domain_initdata;
+	struct pmu_data *pmu;
+	int ret;
+
+	pmu = kzalloc(sizeof(*pmu), GFP_KERNEL);
+	if (!pmu)
+		return -ENOMEM;
+
+	spin_lock_init(&pmu->lock);
+	pmu->pmc_base = initdata->pmc_base;
+	pmu->pmu_base = initdata->pmu_base;
+
+	pmu_reset_init(pmu);
+	for (domain_initdata = initdata->domains; domain_initdata->name;
+	     domain_initdata++) {
+		struct pmu_domain *domain;
+
+		domain = kzalloc(sizeof(*domain), GFP_KERNEL);
+		if (domain) {
+			domain->pmu = pmu;
+			domain->pwr_mask = domain_initdata->pwr_mask;
+			domain->rst_mask = domain_initdata->rst_mask;
+			domain->iso_mask = domain_initdata->iso_mask;
+			domain->base.name = domain_initdata->name;
+
+			__pmu_domain_register(domain, NULL);
+		}
+	}
+	pm_genpd_poweroff_unused();
+
+	ret = dove_init_pmu_irq(pmu, initdata->irq);
+	if (ret)
+		pr_err("dove_init_pmu_irq() failed: %d\n", ret);
+
+	if (pmu->irq_domain)
+		irq_domain_associate_many(pmu->irq_domain, IRQ_DOVE_PMU_START,
+					  0, NR_PMU_IRQS);
+
+	bus_register_notifier(&platform_bus_type, &platform_nb);
+
+	return 0;
+}
+
 /*
  * pmu: power-manager@d0000 {
  *	compatible = "marvell,dove-pmu";
diff --git a/include/linux/soc/dove/pmu.h b/include/linux/soc/dove/pmu.h
index 9c99f84bcc0e..431dfac595e7 100644
--- a/include/linux/soc/dove/pmu.h
+++ b/include/linux/soc/dove/pmu.h
@@ -1,6 +1,24 @@
 #ifndef LINUX_SOC_DOVE_PMU_H
 #define LINUX_SOC_DOVE_PMU_H
 
+#include <linux/types.h>
+
+struct dove_pmu_domain_initdata {
+	u32 pwr_mask;
+	u32 rst_mask;
+	u32 iso_mask;
+	const char *name;
+};
+
+struct dove_pmu_initdata {
+	void __iomem *pmc_base;
+	void __iomem *pmu_base;
+	int irq;
+	const struct dove_pmu_domain_initdata *domains;
+};
+
+int dove_init_pmu_legacy(const struct dove_pmu_initdata *);
+
 int dove_init_pmu(void);
 
 #endif


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Re: [FOR DISCUSSION 0/9] Dove PMU support

[Arnd Bergmann]

On Friday 13 March 2015 12:32:11 Russell King - ARM Linux wrote:
> On Fri, Mar 13, 2015 at 01:26:17PM +0100, Arnd Bergmann wrote:
> > On Friday 13 March 2015 12:11:27 Russell King - ARM Linux wrote:
> > > Of course, I also have a patch which adds legacy support to
> > > arch/arm/mach-dove, but I've assumed you're not interested in that...
> > 
> > You mean legacy support in mach-mvebu?
> 
> No.
> 
> As you'll see, this uses a platform device notifier to hook the devices
> onto the appropriate PM domain, which is why the driver needs to be
> registered early.  This also gets used in DT mode with one legacy
> platform device which is dynamically registered (something which can't
> happen with DT.)

Ok, got it. I think that's fine too. If this helps you spend less
time on forward-porting your patches and in turn completing the
full dove support with DT faster, I'm all for merging this one too.

	Arnd

[PATCH 05/10] dt-bindings: add Marvell PMU documentation

[Russell King]

Add the required DT binding documentation for the Marvell PMU driver.

Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
---
 Documentation/devicetree/bindings/soc/dove/pmu.txt | 49 ++++++++++++++++++++++
 1 file changed, 49 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/soc/dove/pmu.txt

diff --git a/Documentation/devicetree/bindings/soc/dove/pmu.txt b/Documentation/devicetree/bindings/soc/dove/pmu.txt
new file mode 100644
index 000000000000..25d988e7ec35
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/dove/pmu.txt
@@ -0,0 +1,49 @@
+Device Tree bindings for Marvell PMU
+
+Required properties:
+ - compatible: value should be "marvell,dove-pmu".
+ - reg: two base addresses and sizes of the PM controller and PMU.
+ - interrupts: single interrupt number for the PMU interrupt
+ - interrupt-controller: must be specified as the PMU itself is an
+    interrupt controller.
+ - #interrupt-cells: must be 1.
+ - #reset-cells: must be 1.
+
+Optional properties:
+ - None
+
+Power domain descriptions are listed as child nodes of the power management
+node.  Each domain has the following properties:
+
+Required properties:
+ - #power-domain-cells: must be 0.
+
+Optional properties:
+ - marvell,pmu_pwr_mask: specifies the mask value for PMU power register
+ - marvell,pmu_iso_mask: specifies the mask value for PMU isolation register
+ - resets: points to the reset manager (PMU node) and reset index.
+
+Example:
+
+	pmu: power-management@d0000 {
+		compatible = "marvell,dove-pmu";
+		reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
+		interrupts = <33>;
+		interrupt-controller;
+		#interrupt-cells = <1>;
+		#reset-cells = <1>;
+
+		vpu_domain: vpu-domain {
+			#power-domain-cells = <0>;
+			marvell,pmu_pwr_mask = <0x00000008>;
+			marvell,pmu_iso_mask = <0x00000001>;
+			resets = <&pmu 16>;
+		};
+
+		gpu_domain: gpu-domain {
+			#power-domain-cells = <0>;
+			marvell,pmu_pwr_mask = <0x00000004>;
+			marvell,pmu_iso_mask = <0x00000002>;
+			resets = <&pmu 18>;
+		};
+	};
-- 
1.8.3.1

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Re: [PATCH 05/10] dt-bindings: add Marvell PMU documentation

[Rob Herring]

On Fri, Mar 13, 2015 at 11:23 AM, Russell King
<rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org> wrote:
> Add the required DT binding documentation for the Marvell PMU driver.
>
> Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>

Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>

> ---
>  Documentation/devicetree/bindings/soc/dove/pmu.txt | 49 ++++++++++++++++++++++
>  1 file changed, 49 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/soc/dove/pmu.txt
>
> diff --git a/Documentation/devicetree/bindings/soc/dove/pmu.txt b/Documentation/devicetree/bindings/soc/dove/pmu.txt
> new file mode 100644
> index 000000000000..25d988e7ec35
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soc/dove/pmu.txt
> @@ -0,0 +1,49 @@
> +Device Tree bindings for Marvell PMU
> +
> +Required properties:
> + - compatible: value should be "marvell,dove-pmu".
> + - reg: two base addresses and sizes of the PM controller and PMU.
> + - interrupts: single interrupt number for the PMU interrupt
> + - interrupt-controller: must be specified as the PMU itself is an
> +    interrupt controller.
> + - #interrupt-cells: must be 1.
> + - #reset-cells: must be 1.
> +
> +Optional properties:
> + - None
> +
> +Power domain descriptions are listed as child nodes of the power management
> +node.  Each domain has the following properties:
> +
> +Required properties:
> + - #power-domain-cells: must be 0.
> +
> +Optional properties:
> + - marvell,pmu_pwr_mask: specifies the mask value for PMU power register
> + - marvell,pmu_iso_mask: specifies the mask value for PMU isolation register
> + - resets: points to the reset manager (PMU node) and reset index.
> +
> +Example:
> +
> +       pmu: power-management@d0000 {
> +               compatible = "marvell,dove-pmu";
> +               reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
> +               interrupts = <33>;
> +               interrupt-controller;
> +               #interrupt-cells = <1>;
> +               #reset-cells = <1>;
> +
> +               vpu_domain: vpu-domain {
> +                       #power-domain-cells = <0>;
> +                       marvell,pmu_pwr_mask = <0x00000008>;
> +                       marvell,pmu_iso_mask = <0x00000001>;
> +                       resets = <&pmu 16>;
> +               };
> +
> +               gpu_domain: gpu-domain {
> +                       #power-domain-cells = <0>;
> +                       marvell,pmu_pwr_mask = <0x00000004>;
> +                       marvell,pmu_iso_mask = <0x00000002>;
> +                       resets = <&pmu 18>;
> +               };
> +       };
> --
> 1.8.3.1
>
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[PATCH 07/10] ARM: dt: dove: add Dove PMU DT entry to dove.dtsi

[Russell King]

Add the PMU description to the Dove DT file.  The PMU provides multiple
features, including an interrupt, reset, power and isolation controller.

Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
---
 arch/arm/boot/dts/dove.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index a5441d5482a6..43d4ebf414be 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -380,6 +380,15 @@
 				status = "disabled";
 			};
 
+			pmu: power-management@d0000 {
+				compatible = "marvell,dove-pmu";
+				reg = <0xd0000 0x8000>, <0xd8000 0x8000>;
+				interrupts = <33>;
+				interrupt-controller;
+				#interrupt-cells = <1>;
+				#reset-cells = <1>;
+			};
+
 			thermal: thermal-diode@d001c {
 				compatible = "marvell,dove-thermal";
 				reg = <0xd001c 0x0c>, <0xd005c 0x08>;
-- 
1.8.3.1

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[PATCH 08/10] ARM: dt: dove: wire up RTC interrupt

[Russell King]

Now that we have a PMU driver, we can wire up the RTC interrupt in the
DT description for Dove.

Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
---
 arch/arm/boot/dts/dove.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 43d4ebf414be..7e80407bdcf8 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -624,6 +624,8 @@
 			rtc: real-time-clock@d8500 {
 				compatible = "marvell,orion-rtc";
 				reg = <0xd8500 0x20>;
+				interrupt-parent = <&pmu>;
+				interrupts = <5>;
 			};
 
 			gconf: global-config@e802c {
-- 
1.8.3.1

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[PATCH 09/10] ARM: dt: dove: add video decoder power domain description

[Russell King]

Add the description of the video decoder power domain to the PMU DT
entry.

Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
---
 arch/arm/boot/dts/dove.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 7e80407bdcf8..3dcf5322bf0e 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -387,6 +387,13 @@
 				interrupt-controller;
 				#interrupt-cells = <1>;
 				#reset-cells = <1>;
+
+				vpu_domain: vpu-domain {
+					#power-domain-cells = <0>;
+					marvell,pmu_pwr_mask = <0x00000008>;
+					marvell,pmu_iso_mask = <0x00000001>;
+					resets = <&pmu 16>;
+				};
 			};
 
 			thermal: thermal-diode@d001c {
-- 
1.8.3.1

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[PATCH 10/10] ARM: dt: dove: add GPU power domain description

[Russell King]

Add the description of the GPU power domain to the PMU DT entry.

Signed-off-by: Russell King <rmk+kernel-lFZ/pmaqli7XmaaqVzeoHQ@public.gmane.org>
---
 arch/arm/boot/dts/dove.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
index 3dcf5322bf0e..d273552ada8a 100644
--- a/arch/arm/boot/dts/dove.dtsi
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -394,6 +394,13 @@
 					marvell,pmu_iso_mask = <0x00000001>;
 					resets = <&pmu 16>;
 				};
+
+				gpu_domain: gpu-domain {
+					#power-domain-cells = <0>;
+					marvell,pmu_pwr_mask = <0x00000004>;
+					marvell,pmu_iso_mask = <0x00000002>;
+					resets = <&pmu 18>;
+				};
 			};
 
 			thermal: thermal-diode@d001c {
-- 
1.8.3.1

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[FOR DISCUSSION 0/10] Dove PMU support

[Russell King - ARM Linux]

This is the third re-posting of the patch set which I posted almost 11
months ago to support the Dove PMU, with a few additional changes.
This set is based upon 3.19.

In this set are:

* one patch which Rafael originally acked, but there was indecision
  last time around how to handle them due to potential conflicts with
  work that Ulf was doing.  This patches have been updated to apply
  cleanly to 3.19.  This patch should be applied anyway.

* factor out code which gets a validated generic PM domain, which we
  will make use of in later patches. (new)

* improve the validation of the generic PM domain pointer passed into
  pm_genpd_remove_device(). (updated)

* synchronise the state of the generic PM domain after a device is
  probed.  Other solutions may be possible, but require a larger
  patch series to resolve. (updated for patch 2)

* DT binding documentation for the Dove PMU driver, updated with
  comments from Rob.

* the addition of the core Dove PMU driver, which consists of a reset,
  IRQ controller, and power domains.  The reset and power domain code
  has to be closely related due to the power up/down requirements of
  the GPU/VPU subsystems needing to be performed atomically.  (This
  requirement prevents it using the MFD/syscon infrastructure, because
  we would need to hold spinlocks while calling several different
  sub-drivers.)  This currently needs to be available early on in the
  init sequence, so an explicit initialisation call is added to
  mach-mvebu to achieve this. (updated)

* addition of the RTC interrupt, so we can now receive and act on
  alarms generated by the Dove RTC.

* addition of the DT descriptions for the GPU and VPU power domains.
  These patches do not themselves add the DT descriptions for these
  units, so these patches serve as illustrations how these should be
  described.

 Documentation/devicetree/bindings/soc/dove/pmu.txt |  49 +++
 arch/arm/boot/dts/dove.dtsi                        |  25 ++
 arch/arm/mach-mvebu/Kconfig                        |   1 +
 arch/arm/mach-mvebu/dove.c                         |   2 +
 drivers/amba/bus.c                                 |   4 +-
 drivers/base/platform.c                            |   2 +
 drivers/base/power/common.c                        |  15 +
 drivers/base/power/domain.c                        |  64 +++-
 drivers/i2c/i2c-core.c                             |   2 +
 drivers/soc/Makefile                               |   1 +
 drivers/soc/dove/Makefile                          |   1 +
 drivers/soc/dove/pmu.c                             | 406 +++++++++++++++++++++
 drivers/spi/spi.c                                  |   2 +
 include/linux/pm.h                                 |   1 +
 include/linux/pm_domain.h                          |   4 +
 include/linux/soc/dove/pmu.h                       |   6 +
 16 files changed, 564 insertions(+), 21 deletions(-)

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Re: [FOR DISCUSSION 0/9] Dove PMU support

[Rafael J. Wysocki]

On Thursday, March 12, 2015 06:30:21 PM Russell King - ARM Linux wrote:
> This is a re-posting of the patch set which I posted almost 10 months
> ago to support the Dove PMU, with a few additional changes.  This set
> is based upon 3.19.
> 
> In this set are:
> 
> * two patches which Rafael originally acked, but there was indecision
>   last time around how to handle them due to potential conflicts with
>   work that Ulf was doing.  These patches have been updated to apply
>   cleanly to 3.19.  I don't know if people want to take these as
>   fixes to the PM domain code or not (hence why I'm posting this
>   series during the merge window - if it weren't for this, I'd hold
>   it off.)
> 
> * what I regard as a fix to the PM domain code; as a result of a
>   previous commit, the PM domain code mismatches the runtime PM state,
>   which leads to the PM domain being unexpectedly left on.  This patch
>   has been re-worked to try an alternative approach, syncing the PM
>   domain state with the runtime PM state after the probe has completed.
> 
> * the addition of the core Dove PMU driver, which consists of a reset,
>   IRQ controller, and power domains.  The reset and power domain code
>   has to be closely related due to the power up/down requirements of
>   the GPU/VPU subsystems needing to be performed atomically.  (This
>   requirement prevents it using the MFD infrastructure, because we
>   would need to hold spinlocks while calling several different
>   sub-drivers.)
> 
> * addition of the RTC interrupt, so we can now receive and act on
>   alarms generated by the Dove RTC.
> 
> * addition of the DT descriptions for the GPU and VPU power domains.
>   These patches do not themselves add the DT descriptions for these
>   units, so these patches serve as illustrations how these should be
>   described.
> 

I can apply patches [1-3/9] from this series if that helps.

Rafael

Re: [FOR DISCUSSION 0/9] Dove PMU support

[Rafael J. Wysocki]

On Thursday, March 19, 2015 10:59:20 PM Rafael J. Wysocki wrote:
> On Thursday, March 12, 2015 06:30:21 PM Russell King - ARM Linux wrote:
> > This is a re-posting of the patch set which I posted almost 10 months
> > ago to support the Dove PMU, with a few additional changes.  This set
> > is based upon 3.19.
> > 
> > In this set are:
> > 
> > * two patches which Rafael originally acked, but there was indecision
> >   last time around how to handle them due to potential conflicts with
> >   work that Ulf was doing.  These patches have been updated to apply
> >   cleanly to 3.19.  I don't know if people want to take these as
> >   fixes to the PM domain code or not (hence why I'm posting this
> >   series during the merge window - if it weren't for this, I'd hold
> >   it off.)
> > 
> > * what I regard as a fix to the PM domain code; as a result of a
> >   previous commit, the PM domain code mismatches the runtime PM state,
> >   which leads to the PM domain being unexpectedly left on.  This patch
> >   has been re-worked to try an alternative approach, syncing the PM
> >   domain state with the runtime PM state after the probe has completed.
> > 
> > * the addition of the core Dove PMU driver, which consists of a reset,
> >   IRQ controller, and power domains.  The reset and power domain code
> >   has to be closely related due to the power up/down requirements of
> >   the GPU/VPU subsystems needing to be performed atomically.  (This
> >   requirement prevents it using the MFD infrastructure, because we
> >   would need to hold spinlocks while calling several different
> >   sub-drivers.)
> > 
> > * addition of the RTC interrupt, so we can now receive and act on
> >   alarms generated by the Dove RTC.
> > 
> > * addition of the DT descriptions for the GPU and VPU power domains.
> >   These patches do not themselves add the DT descriptions for these
> >   units, so these patches serve as illustrations how these should be
> >   described.
> > 
> 
> I can apply patches [1-3/9] from this series if that helps.

I mean from the next version of it ([FOR DISCUSSION 0/10] Dove PMU support).

These patches to be precise:

https://patchwork.kernel.org/patch/6006991/
https://patchwork.kernel.org/patch/6007001/
https://patchwork.kernel.org/patch/6007021/

unless there are objectsions (which I haven't seen).

Rafael

Re: [FOR DISCUSSION 0/9] Dove PMU support

[Russell King - ARM Linux]

On Thu, Mar 19, 2015 at 11:02:35PM +0100, Rafael J. Wysocki wrote:
> On Thursday, March 19, 2015 10:59:20 PM Rafael J. Wysocki wrote:
> > On Thursday, March 12, 2015 06:30:21 PM Russell King - ARM Linux wrote:
> > > This is a re-posting of the patch set which I posted almost 10 months
> > > ago to support the Dove PMU, with a few additional changes.  This set
> > > is based upon 3.19.
> > > 
> > > In this set are:
> > > 
> > > * two patches which Rafael originally acked, but there was indecision
> > >   last time around how to handle them due to potential conflicts with
> > >   work that Ulf was doing.  These patches have been updated to apply
> > >   cleanly to 3.19.  I don't know if people want to take these as
> > >   fixes to the PM domain code or not (hence why I'm posting this
> > >   series during the merge window - if it weren't for this, I'd hold
> > >   it off.)
> > > 
> > > * what I regard as a fix to the PM domain code; as a result of a
> > >   previous commit, the PM domain code mismatches the runtime PM state,
> > >   which leads to the PM domain being unexpectedly left on.  This patch
> > >   has been re-worked to try an alternative approach, syncing the PM
> > >   domain state with the runtime PM state after the probe has completed.
> > > 
> > > * the addition of the core Dove PMU driver, which consists of a reset,
> > >   IRQ controller, and power domains.  The reset and power domain code
> > >   has to be closely related due to the power up/down requirements of
> > >   the GPU/VPU subsystems needing to be performed atomically.  (This
> > >   requirement prevents it using the MFD infrastructure, because we
> > >   would need to hold spinlocks while calling several different
> > >   sub-drivers.)
> > > 
> > > * addition of the RTC interrupt, so we can now receive and act on
> > >   alarms generated by the Dove RTC.
> > > 
> > > * addition of the DT descriptions for the GPU and VPU power domains.
> > >   These patches do not themselves add the DT descriptions for these
> > >   units, so these patches serve as illustrations how these should be
> > >   described.
> > > 
> > 
> > I can apply patches [1-3/9] from this series if that helps.
> 
> I mean from the next version of it ([FOR DISCUSSION 0/10] Dove PMU support).

Kevin had some comments on patch 2 which I think ought to be addressed.
He's quite right that dev_to_genpd() should be hidden from view and
replaced with the safer pm_genpd_lookup_dev() version - even though
pm_genpd_lookup_dev() itself is not fully safe against the domain
on a device changing beneath it.

If you want to hold on, I'll respin with his comments there addressed,
or if you prefer to merge them as-is and fix Kevin's comments afterwards,
that's also fine by me.

I'd just be happy to see some progress on this series. :)

Thanks.

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Re: [FOR DISCUSSION 0/9] Dove PMU support

[Rafael J. Wysocki]

On Friday, March 20, 2015 12:16:59 PM Russell King - ARM Linux wrote:
> On Thu, Mar 19, 2015 at 11:02:35PM +0100, Rafael J. Wysocki wrote:
> > On Thursday, March 19, 2015 10:59:20 PM Rafael J. Wysocki wrote:
> > > On Thursday, March 12, 2015 06:30:21 PM Russell King - ARM Linux wrote:
> > > > This is a re-posting of the patch set which I posted almost 10 months
> > > > ago to support the Dove PMU, with a few additional changes.  This set
> > > > is based upon 3.19.
> > > > 
> > > > In this set are:
> > > > 
> > > > * two patches which Rafael originally acked, but there was indecision
> > > >   last time around how to handle them due to potential conflicts with
> > > >   work that Ulf was doing.  These patches have been updated to apply
> > > >   cleanly to 3.19.  I don't know if people want to take these as
> > > >   fixes to the PM domain code or not (hence why I'm posting this
> > > >   series during the merge window - if it weren't for this, I'd hold
> > > >   it off.)
> > > > 
> > > > * what I regard as a fix to the PM domain code; as a result of a
> > > >   previous commit, the PM domain code mismatches the runtime PM state,
> > > >   which leads to the PM domain being unexpectedly left on.  This patch
> > > >   has been re-worked to try an alternative approach, syncing the PM
> > > >   domain state with the runtime PM state after the probe has completed.
> > > > 
> > > > * the addition of the core Dove PMU driver, which consists of a reset,
> > > >   IRQ controller, and power domains.  The reset and power domain code
> > > >   has to be closely related due to the power up/down requirements of
> > > >   the GPU/VPU subsystems needing to be performed atomically.  (This
> > > >   requirement prevents it using the MFD infrastructure, because we
> > > >   would need to hold spinlocks while calling several different
> > > >   sub-drivers.)
> > > > 
> > > > * addition of the RTC interrupt, so we can now receive and act on
> > > >   alarms generated by the Dove RTC.
> > > > 
> > > > * addition of the DT descriptions for the GPU and VPU power domains.
> > > >   These patches do not themselves add the DT descriptions for these
> > > >   units, so these patches serve as illustrations how these should be
> > > >   described.
> > > > 
> > > 
> > > I can apply patches [1-3/9] from this series if that helps.
> > 
> > I mean from the next version of it ([FOR DISCUSSION 0/10] Dove PMU support).
> 
> Kevin had some comments on patch 2 which I think ought to be addressed.
> He's quite right that dev_to_genpd() should be hidden from view and
> replaced with the safer pm_genpd_lookup_dev() version - even though
> pm_genpd_lookup_dev() itself is not fully safe against the domain
> on a device changing beneath it.
> 
> If you want to hold on, I'll respin with his comments there addressed,
> or if you prefer to merge them as-is and fix Kevin's comments afterwards,
> that's also fine by me.

Both work for me, actually.  I think that Kevin has ACKed the patch despite
the comments, so it would be fine to apply it I guess.

> I'd just be happy to see some progress on this series. :)

Sure.

Re: [FOR DISCUSSION 0/9] Dove PMU support

[Russell King - ARM Linux]

On Fri, Mar 20, 2015 at 01:44:30PM +0100, Rafael J. Wysocki wrote:
> Both work for me, actually.  I think that Kevin has ACKed the patch despite
> the comments, so it would be fine to apply it I guess.

Here's the set of three - with the second one reworked.

 drivers/base/power/domain.c | 58 +++++++++++++++++++++++++++++----------------
 include/linux/pm_domain.h   |  6 ++---
 2 files changed, 40 insertions(+), 24 deletions(-)

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