Re: [PATCH RFC 3/7] clk: samsung: exynos542x: Add EPLL rate table

Krzysztof Kozlowski
2017-04-22T15:28:21Z

On Fri, Apr 21, 2017 at 07:19:47PM +0200, Sylwester Nawrocki wrote:
> A specific clock rate table is added for EPLL so it is possible
> to set frequency of the EPLL output clock as multiple of various
> audio sampling rates.
>
> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
> ---
> drivers/clk/samsung/clk-exynos5420.c | 20 ++++++++++++++++++--
> 1 file changed, 18 insertions(+), 2 deletions(-)
>

Looks correct although I didn't check the numbers.
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof