From mboxrd@z Thu Jan 1 00:00:00 1970 From: Warner Losh Subject: Re: [PATCH v3 4/9] of: mtd: add documentation for the ONFI NAND timing mode property Date: Wed, 12 Mar 2014 12:27:40 -0600 Message-ID: References: <1394647664-8258-1-git-send-email-b.brezillon.dev@gmail.com> <1394647664-8258-5-git-send-email-b.brezillon.dev@gmail.com> Mime-Version: 1.0 (Mac OS X Mail 7.2 \(1874\)) Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: In-Reply-To: <1394647664-8258-5-git-send-email-b.brezillon.dev@gmail.com> Sender: linux-doc-owner@vger.kernel.org To: Boris BREZILLON Cc: Maxime Ripard , Rob Herring , David Woodhouse , Grant Likely , Brian Norris , Jason Gunthorpe , Arnd Bergmann , devicetree@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mtd@lists.infradead.org, dev@linux-sunxi.org List-Id: devicetree@vger.kernel.org On Mar 12, 2014, at 12:07 PM, Boris BREZILLON wrote: > Add documentation for the ONFI NAND timing mode property. I don=92t see a Toggle/JEDEC mode timing property. Will that be defined= for Toshiba, Samsung and San Disk flash? Or will this be limited to Micron, Intel and Hynix = (the only ones supporting ONFI)? Warner > Signed-off-by: Boris BREZILLON > --- > Documentation/devicetree/bindings/mtd/nand.txt | 8 ++++++++ > 1 file changed, 8 insertions(+) >=20 > diff --git a/Documentation/devicetree/bindings/mtd/nand.txt b/Documen= tation/devicetree/bindings/mtd/nand.txt > index b53f92e..2046027 100644 > --- a/Documentation/devicetree/bindings/mtd/nand.txt > +++ b/Documentation/devicetree/bindings/mtd/nand.txt > @@ -19,3 +19,11 @@ errors per {size} bytes". > The interpretation of these parameters is implementation-defined, so = not all > implementations must support all possible combinations. However, impl= ementations > are encouraged to further specify the value(s) they support. > + > +- onfi,nand-timing-mode: an integer encoding the supported ONFI timi= ng modes of > + the NAND chip. Each supported mode is represented as a bit positio= n (i.e. : > + mode 0 and 1 =3D> (1 << 0) | (1 << 1) =3D 0x3). > + This is only used when the chip does not support the ONFI standard= =2E > + The last bit set represent the closest mode fulfilling the NAND ch= ip timings. > + For a full description of the different timing modes see this docu= ment: > + www.onfi.org/~/media/ONFI/specs/onfi_3_1_spec.pdf > --=20 > 1.7.9.5 >=20 > -- > To unsubscribe from this list: send the line "unsubscribe devicetree"= in > the body of a message to majordomo@vger.kernel.org > More majordomo info at http://vger.kernel.org/majordomo-info.html