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[125.103.213.40]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34e76de1e41sm10145504a91.2.2025.12.25.01.35.46 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Dec 2025 01:35:52 -0800 (PST) Content-Type: text/plain; charset=us-ascii Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3864.300.41.1.7\)) Subject: Re: [PATCH v4 2/9] dt-bindings: display: add verisilicon,dc From: "Han Gao (Revy)" In-Reply-To: <20251224161205.1132149-3-zhengxingda@iscas.ac.cn> Date: Thu, 25 Dec 2025 17:35:34 +0800 Cc: "Han Gao (Revy)" , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Drew Fustini , Guo Ren , Fu Wei , Philipp Zabel , Heiko Stuebner , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Michal Wilczynski , Yao Zi , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Icenowy Zheng Content-Transfer-Encoding: quoted-printable Message-Id: References: <20251224161205.1132149-1-zhengxingda@iscas.ac.cn> <20251224161205.1132149-3-zhengxingda@iscas.ac.cn> To: Icenowy Zheng X-Mailer: Apple Mail (2.3864.300.41.1.7) > On Dec 25, 2025, at 00:11, Icenowy Zheng = wrote: >=20 > From: Icenowy Zheng >=20 > Verisilicon has a series of display controllers prefixed with DC and > with self-identification facility like their GC series GPUs. >=20 > Add a device tree binding for it. >=20 > Depends on the specific DC model, it can have either one or two = display > outputs, and each display output could be set to DPI signal or "DP" > signal (which seems to be some plain parallel bus to HDMI = controllers). >=20 > Signed-off-by: Icenowy Zheng > Signed-off-by: Icenowy Zheng > --- > Changes in v4: > - Added a comment for "verisilicon,dc" that says the ID/revision is > discoverable via registers. > - Removed clock minItems constraint w/o specific compatible strings. >=20 > Changes in v3: > - Added SoC-specific compatible string, and arm the binding with clock = / > port checking for the specific SoC (with a 2-output DC). >=20 > Changes in v2: > - Fixed misspelt "versilicon" in title. > - Moved minItems in clock properties to be earlier than items. > - Re-aligned multi-line clocks and resets in example. >=20 > .../bindings/display/verisilicon,dc.yaml | 144 ++++++++++++++++++ > 1 file changed, 144 insertions(+) > create mode 100644 = Documentation/devicetree/bindings/display/verisilicon,dc.yaml >=20 > diff --git = a/Documentation/devicetree/bindings/display/verisilicon,dc.yaml = b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > new file mode 100644 > index 0000000000000..fe64cc1466690 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/verisilicon,dc.yaml > @@ -0,0 +1,144 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/verisilicon,dc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Verisilicon DC-series display controllers > + > +maintainers: > + - Icenowy Zheng > + > +properties: > + $nodename: > + pattern: "^display@[0-9a-f]+$" > + > + compatible: > + items: > + - enum: > + - thead,th1520-dc8200 > + - const: verisilicon,dc # DC IPs have discoverable ID/revision = registers > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + items: > + - description: DC Core clock > + - description: DMA AXI bus clock > + - description: Configuration AHB bus clock > + - description: Pixel clock of output 0 > + - description: Pixel clock of output 1 > + > + clock-names: > + items: > + - const: core > + - const: axi > + - const: ahb > + - const: pix0 > + - const: pix1 > + > + resets: > + items: > + - description: DC Core reset > + - description: DMA AXI bus reset > + - description: Configuration AHB bus reset > + > + reset-names: > + items: > + - const: core > + - const: axi > + - const: ahb > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: The first output channel , endpoint 0 should be > + used for DPI format output and endpoint 1 should be used > + for DP format output. > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: The second output channel if the DC variant > + supports. Follow the same endpoint addressing rule with > + the first port. > + > + required: > + - port@0 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + - clock-names > + - ports > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + const: thead,th1520-dc8200 > + then: > + properties: > + clocks: > + minItems: 5 > + ports: > + required: > + - port@0 > + - port@1 > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + soc { > + #address-cells =3D <2>; > + #size-cells =3D <2>; > + > + display@ffef600000 { > + compatible =3D "thead,th1520-dc8200", "verisilicon,dc"; > + reg =3D <0xff 0xef600000 0x0 0x100000>; > + interrupts =3D <93 IRQ_TYPE_LEVEL_HIGH>; > + clocks =3D <&clk_vo CLK_DPU_CCLK>, > + <&clk_vo CLK_DPU_ACLK>, > + <&clk_vo CLK_DPU_HCLK>, > + <&clk_vo CLK_DPU_PIXELCLK0>, > + <&clk_vo CLK_DPU_PIXELCLK1>; > + clock-names =3D "core", "axi", "ahb", "pix0", "pix1"; > + resets =3D <&rst TH1520_RESET_ID_DPU_CORE>, > + <&rst TH1520_RESET_ID_DPU_AXI>, > + <&rst TH1520_RESET_ID_DPU_AHB>; > + reset-names =3D "core", "axi", "ahb"; > + > + ports { > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + port@0 { > + reg =3D <0>; > + }; > + > + port@1 { > + reg =3D <1>; > + #address-cells =3D <1>; > + #size-cells =3D <0>; > + > + dpu_out_dp1: endpoint@1 { > + reg =3D <1>; > + remote-endpoint =3D <&hdmi_in>; > + }; > + }; > + }; > + }; > + }; > --=20 > 2.52.0 >=20 Tested-by: Han Gao >