From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 515A6C4321E for ; Thu, 13 Oct 2022 09:17:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229689AbiJMJRX (ORCPT ); Thu, 13 Oct 2022 05:17:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229513AbiJMJRW (ORCPT ); Thu, 13 Oct 2022 05:17:22 -0400 Received: from aposti.net (aposti.net [89.234.176.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D3E925FBC; Thu, 13 Oct 2022 02:17:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1665652637; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=QfKF6P//aPtt3yXkddZGb8gQhNXBSYeBQmboxbZCJlU=; b=Ip0NSVDD1AM8ZgtvW/VD87fTHoRfAC5ZKR4g5vCDTryKzaGimlZJoh+FC5CRuxEyrYuyOV zFio5aFohd39Q+mWiqCJyJxM7qdFhkFObmPHLG9/o7LYmzxzlFG4La4/m47ImlJB8FwZ5u kKRpu9SSwogossEIyH7SeLGOjn8wS2U= Date: Thu, 13 Oct 2022 10:17:04 +0100 From: Paul Cercueil Subject: Re: [PATCH 7/8] serial: 8250/ingenic: Add support for the JZ4750/JZ4755 SoCs To: Siarhei Volkau Cc: Arnd Bergmann , kernel test robot , kbuild-all@lists.01.org, Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Greg Kroah-Hartman , Thomas Bogendoerfer , Linus Walleij , Jiri Slaby , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-serial@vger.kernel.org, linux-mips@vger.kernel.org, GPIO SUBSYSTEM Message-Id: In-Reply-To: References: <20221009181338.2896660-8-lis8215@gmail.com> <202210100607.YdxoR0tD-lkp@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi, Le jeu., oct. 13 2022 at 08:46:39 +0200, Arnd Bergmann =20 a =C3=A9crit : > On Thu, Oct 13, 2022, at 8:37 AM, Siarhei Volkau wrote: >> =D0=BF=D0=BD, 10 =D0=BE=D0=BA=D1=82. 2022 =D0=B3. =D0=B2 01:29, kernel = test robot=20 >> : >>> config: ia64-allyesconfig >>> config: arm64-randconfig-r035-20221010 >>=20 >>> > 142 #define CGU_REG_CPCCR ((void *)CKSEG1ADDR(0x10000000)) >>=20 >>> 0-DAY CI Kernel Test Service >>=20 >> I know CKSEG1ADDR is MIPS specific, might be it needed to disable=20 >> COMPILE_TEST >> on the driver? >> Since early syscon isn't mainlined yet I don't see any other way at=20 >> the moment. >>=20 >> Any suggestions on that, folks? >=20 > This looks like some setup that belongs into the bootloader. If you=20 > are > handing over the console from bootloader to kernel, the hardware=20 > should > already be in a working state, with no need to touch it during early > boot. >=20 > If you are dealing with broken bootloaders that are not under your=20 > control, > having this code in the architecture specific early boot as a fixup > would be better than putting it into the driver. Agreed. I am not fond of having a driver poking into an unrelated=20 subsystem's memory area. Just disable the divider in ingenic_fixup_fdt() in=20 arch/mips/generic/board-ingenic.c. Cheers, -Paul