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[77.38.7.79]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a0018dcf59sm72964095e9.1.2026.09.27.04.44.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 27 Sep 2026 04:44:39 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Samuel Holland , Andre Przywara Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Per Larsson Subject: Re: [PATCH v2 1/2] arm64: dts: allwinner: a523: add EPHY 25MHz clock fanout pins Date: Sun, 27 Sep 2026 13:44:38 +0200 Message-ID: In-Reply-To: <20260926232142.5244-2-andre.przywara@arm.com> References: <20260926232142.5244-1-andre.przywara@arm.com> <20260926232142.5244-2-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne nedelja, 27. september 2026 ob 01:21:41 Srednjeevropski poletni =C4=8Da= s je Andre Przywara napisal(a): > The Allwinner A523 SoC family provides two clock fanout pins, which are > backed by gated clocks fixed to 25 MHz, divided down from the main > peripheral PLL. Those are meant to clock an Ethernet PHY, and allow to > save an external crystal oscillator typically employed for that purpose. >=20 > Add the pin descriptions of the two pins for those clocks, one is within > the RGMII0 pins, the other within the RGMII1 pins, although the clock > fanout works completely independently from the two MACs. >=20 > Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec Best regards, Jernej