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From: Paul Cercueil <paul@opendingux.net>
To: 周琰杰 <zhouyanjie@wanyeetech.com>
Cc: tsbogend@alpha.franken.de, robh+dt@kernel.org,
	linux-mips@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, dongsheng.qiu@ingenic.com,
	aric.pzqi@ingenic.com, rick.tyliu@ingenic.com,
	sihui.liu@ingenic.com, jun.jiang@ingenic.com,
	sernia.zhou@foxmail.com
Subject: Re: [PATCH 2/4] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs.
Date: Tue, 22 Jun 2021 13:31:33 +0100	[thread overview]
Message-ID: <L4S3VQ.7YL97HPASWY21@opendingux.net> (raw)
In-Reply-To: <1624347445-88070-3-git-send-email-zhouyanjie@wanyeetech.com>

Hi,

Le mar., juin 22 2021 at 15:37:23 +0800, 周琰杰 (Zhou Yanjie) 
<zhouyanjie@wanyeetech.com> a écrit :
> Add MAC syscon nodes for X1000 SoC and X1830 SoC from Ingenic.
> 
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>

Acked-by: Paul Cercueil <paul@crapouillou.net>

Cheers,
-Paul

> ---
>  arch/mips/boot/dts/ingenic/x1000.dtsi | 7 +++++++
>  arch/mips/boot/dts/ingenic/x1830.dtsi | 7 +++++++
>  2 files changed, 14 insertions(+)
> 
> diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi 
> b/arch/mips/boot/dts/ingenic/x1000.dtsi
> index aac9ded..dec7909 100644
> --- a/arch/mips/boot/dts/ingenic/x1000.dtsi
> +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
> @@ -80,6 +80,11 @@
> 
>  			status = "disabled";
>  		};
> +
> +		mac_phy_ctrl: mac-phy-ctrl@e8 {
> +			compatible = "syscon";
> +			reg = <0xe8 0x4>;
> +		};
>  	};
> 
>  	ost: timer@12000000 {
> @@ -347,6 +352,8 @@
>  		clocks = <&cgu X1000_CLK_MAC>;
>  		clock-names = "stmmaceth";
> 
> +		mode-reg = <&mac_phy_ctrl>;
> +
>  		status = "disabled";
> 
>  		mdio: mdio {
> diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi 
> b/arch/mips/boot/dts/ingenic/x1830.dtsi
> index 59ca3a8..215257f 100644
> --- a/arch/mips/boot/dts/ingenic/x1830.dtsi
> +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
> @@ -73,6 +73,11 @@
> 
>  			status = "disabled";
>  		};
> +
> +		mac_phy_ctrl: mac-phy-ctrl@e8 {
> +			compatible = "syscon";
> +			reg = <0xe8 0x4>;
> +		};
>  	};
> 
>  	ost: timer@12000000 {
> @@ -336,6 +341,8 @@
>  		clocks = <&cgu X1830_CLK_MAC>;
>  		clock-names = "stmmaceth";
> 
> +		mode-reg = <&mac_phy_ctrl>;
> +
>  		status = "disabled";
> 
>  		mdio: mdio {
> --
> 2.7.4
> 



  reply	other threads:[~2021-06-22 12:31 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-06-22  7:37 [PATCH 0/4] Misc Ingenic patches 周琰杰 (Zhou Yanjie)
2021-06-22  7:37 ` [PATCH 1/4] MIPS: X1830: Respect cell count of common properties 周琰杰 (Zhou Yanjie)
2021-06-22 12:30   ` Paul Cercueil
2021-06-22  7:37 ` [PATCH 2/4] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2021-06-22 12:31   ` Paul Cercueil [this message]
2021-06-22  7:37 ` [PATCH 3/4] MIPS: GCW0: Adjust pinctrl related code in device tree 周琰杰 (Zhou Yanjie)
2021-06-22 12:46   ` Paul Cercueil
2021-06-22 13:51     ` 周琰杰
2021-06-22 14:05       ` Paul Cercueil
2021-06-22 14:41         ` 周琰杰
2021-06-22  7:37 ` [PATCH 4/4] MIPS: CI20: Reduce MSC0 frequency and add second percpu timer for SMP 周琰杰 (Zhou Yanjie)
2021-06-22 12:39   ` Paul Cercueil
2021-06-22 13:55     ` 周琰杰

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