From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id CDE85C433EF for ; Tue, 5 Oct 2021 20:50:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9EE6F615A3 for ; Tue, 5 Oct 2021 20:50:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229920AbhJEUwR convert rfc822-to-8bit (ORCPT ); Tue, 5 Oct 2021 16:52:17 -0400 Received: from aposti.net ([89.234.176.197]:51698 "EHLO aposti.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235545AbhJEUwR (ORCPT ); Tue, 5 Oct 2021 16:52:17 -0400 Date: Tue, 05 Oct 2021 21:50:12 +0100 From: Paul Cercueil Subject: Re: [PATCH v5 5/7] MIPS: DTS: jz4780: Account for Synopsys HDMI driver and LCD controllers To: "H. Nikolaus Schaller" Cc: Rob Herring , Mark Rutland , Thomas Bogendoerfer , Geert Uytterhoeven , Kees Cook , "Eric W. Biederman" , Miquel Raynal , David Airlie , Daniel Vetter , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jernej Skrabec , Ezequiel Garcia , Harry Wentland , Sam Ravnborg , Maxime Ripard , Hans Verkuil , Liam Girdwood , Mark Brown , Paul Boddie , devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, letux-kernel@openphoenux.org, Jonas Karlman , dri-devel@lists.freedesktop.org Message-Id: In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1; format=flowed Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Nikolaus & Paul, Le mar., oct. 5 2021 at 14:29:17 +0200, H. Nikolaus Schaller a écrit : > From: Paul Boddie > > A specialisation of the generic Synopsys HDMI driver is employed for > JZ4780 > HDMI support. This requires a new driver, plus device tree and > configuration > modifications. > > Signed-off-by: Paul Boddie > Signed-off-by: H. Nikolaus Schaller > --- > arch/mips/boot/dts/ingenic/jz4780.dtsi | 45 > ++++++++++++++++++++++++++ > 1 file changed, 45 insertions(+) > > diff --git a/arch/mips/boot/dts/ingenic/jz4780.dtsi > b/arch/mips/boot/dts/ingenic/jz4780.dtsi > index 9e34f433b9b5..c3c18a59c377 100644 > --- a/arch/mips/boot/dts/ingenic/jz4780.dtsi > +++ b/arch/mips/boot/dts/ingenic/jz4780.dtsi > @@ -424,6 +424,51 @@ i2c4: i2c@10054000 { > status = "disabled"; > }; > > + hdmi: hdmi@10180000 { > + compatible = "ingenic,jz4780-dw-hdmi"; > + reg = <0x10180000 0x8000>; > + reg-io-width = <4>; > + > + clocks = <&cgu JZ4780_CLK_AHB0>, <&cgu JZ4780_CLK_HDMI>; > + clock-names = "iahb", "isfr"; > + > + assigned-clocks = <&cgu JZ4780_CLK_HDMI>; > + assigned-clock-rates = <27000000>; Any reason why this is set to 27 MHz? Is it even required? Because with the current ci20.dts, it won't be clocked at anything but 48 MHz. > + > + interrupt-parent = <&intc>; > + interrupts = <3>; > + > + /* ddc-i2c-bus = <&i2c4>; */ > + > + status = "disabled"; > + }; > + > + lcdc0: lcdc0@13050000 { > + compatible = "ingenic,jz4780-lcd"; > + reg = <0x13050000 0x1800>; > + > + clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>; > + clock-names = "lcd", "lcd_pclk"; > + > + interrupt-parent = <&intc>; > + interrupts = <31>; > + > + status = "disabled"; I think you can keep lcdc0 enabled by default (not lcdc1 though), since it is highly likely that you'd want that. Cheers, -Paul > + }; > + > + lcdc1: lcdc1@130a0000 { > + compatible = "ingenic,jz4780-lcd"; > + reg = <0x130a0000 0x1800>; > + > + clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD1PIXCLK>; > + clock-names = "lcd", "lcd_pclk"; > + > + interrupt-parent = <&intc>; > + interrupts = <31>; > + > + status = "disabled"; > + }; > + > nemc: nemc@13410000 { > compatible = "ingenic,jz4780-nemc", "simple-mfd"; > reg = <0x13410000 0x10000>; > -- > 2.33.0 >