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[178.165.167.132]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48dba1be42esm16537414f8f.5.2026.10.11.09.32.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Oct 2026 09:32:51 -0700 (PDT) From: Stefan =?UTF-8?B?RMO2c2luZ2Vy?= To: linux-arm-kernel@lists.infradead.org, Navid Ghahremani Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, arnd@arndb.de, linux@armlinux.org.uk, robh@kernel.org, krzk@kernel.org, Navid Ghahremani Subject: Re: [PATCH 20/24] spi: Add ZTE ZX279128S SPI flash controller Date: Sun, 11 Oct 2026 18:32:46 +0200 Message-ID: In-Reply-To: <20261010130024.177503-21-ghahramani.navid@gmail.com> References: <20261010130024.177503-1-ghahramani.navid@gmail.com> <20261010130024.177503-21-ghahramani.navid@gmail.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextPartl3bGPPFXTCGY5ZUHclgI1Q"; micalg="pgp-sha256"; protocol="application/pgp-signature" --nextPartl3bGPPFXTCGY5ZUHclgI1Q Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8"; protected-headers="v1" From: Stefan =?UTF-8?B?RMO2c2luZ2Vy?= Subject: Re: [PATCH 20/24] spi: Add ZTE ZX279128S SPI flash controller Date: Sun, 11 Oct 2026 18:32:46 +0200 Message-ID: In-Reply-To: <20261010130024.177503-21-ghahramani.navid@gmail.com> MIME-Version: 1.0 Hi, Am Samstag, 10. Oktober 2026, 14:59:58 Mitteleurop=C3=A4ische Sommerzeit sc= hrieb=20 Navid Ghahremani: > Execute bounded SPI-memory operations through the controller FIFO. Honor > device and operation clock limits through the CRPM divider and cap the > validated maximum at 50 MHz. The registers look identical (though with slightly different names) than th= e=20 quad SPI controller on my machines. I have a more advanced driver here: https://gitlab.com/stefandoesinger/zx297520-kernel/-/blob/dlink/drivers/spi/ spi-zx.c?ref_type=3Dheads Please give it a try on your hardware and see if it works. My driver has optional DMA support, which does allow measurable improvement= s=20 in situations where SPI access and CPU activity happen in parallel (althoug= h=20 DMA operation is slightly slower than PIO with an otherwise idle CPU) and I= =20 tuned PIO mode a bit (in particular avoiding redundant fifo size reads). The qspi driver is a bit down on my FIFO queue (I plan to take care of pinc= trl=20 and DMA first), but I can speed it up if your board gets to a point where S= PI=20 can be done reliably first. On the hardware otherwise, it can also raise IRQs when the read/write FIFOs= =20 are above/below a certain threshold. That allows PIO mode without constant= =20 polling. I found that it doesn't have an actual performance advantage over= =20 polling PIO mode even when pushing the CPU during SPI transfers. DMA mode h= as=20 clear advantages in this regard and I found no need to implement an IRQ dri= ven=20 PIO mode. If the performance characteristics on your board are different we= can=20 reconsider this. --nextPartl3bGPPFXTCGY5ZUHclgI1Q Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part. 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