[PATCH 0/4] Add RZ/G3E GPT clocks and resets

[PATCH 0/4] Add RZ/G3E GPT clocks and resets

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

The RZ/G3E GPT IP has multiple clocks and resets. It has bus and core
clocks. The bus clock is module clock and core clock is sourced from
the bus clock. So add support for module clock as parent reusing the
existing rzv2h_cpg_fixed_mod_status_clk_register().

Biju Das (4):
  clk: renesas: rzv2h: Refactor
    rzv2h_cpg_fixed_mod_status_clk_register()
  clk: renesas: rzv2h: Add support for parent mod clocks
  dt-bindings: clock: renesas,r9a09g047-cpg: Add GPT core clocks
  clk: renesas: r9a09g047: Add GPT clocks and resets

 drivers/clk/renesas/r9a09g047-cpg.c           | 10 ++-
 drivers/clk/renesas/rzv2h-cpg.c               | 74 ++++++++++++-------
 drivers/clk/renesas/rzv2h-cpg.h               | 22 ++++--
 .../dt-bindings/clock/renesas,r9a09g047-cpg.h |  2 +
 4 files changed, 75 insertions(+), 33 deletions(-)

-- 
2.43.0

[PATCH 3/4] dt-bindings: clock: renesas,r9a09g047-cpg: Add GPT core clocks

[Biju]

From: Biju Das <biju.das.jz@bp.renesas.com>

Add definitions for GPT core clocks in the R9A09G047 CPG DT bindings
header file.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
 include/dt-bindings/clock/renesas,r9a09g047-cpg.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
index a27132f9a6c8..ac0f1ce3c752 100644
--- a/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
+++ b/include/dt-bindings/clock/renesas,r9a09g047-cpg.h
@@ -20,5 +20,7 @@
 #define R9A09G047_SPI_CLK_SPI			9
 #define R9A09G047_GBETH_0_CLK_PTP_REF_I		10
 #define R9A09G047_GBETH_1_CLK_PTP_REF_I		11
+#define R9A09G047_GPT_0_CLKS_GPT		12
+#define R9A09G047_GPT_1_CLKS_GPT		13
 
 #endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G047_CPG_H__ */
-- 
2.43.0

Re: [PATCH 3/4] dt-bindings: clock: renesas,r9a09g047-cpg: Add GPT core clocks

[Conor Dooley]

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On Thu, Aug 14, 2025 at 01:48:26PM +0100, Biju wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Add definitions for GPT core clocks in the R9A09G047 CPG DT bindings
> header file.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Acked-by: Conor Dooley <conor.dooley@microchip.com>

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Re: [PATCH 0/4] Add RZ/G3E GPT clocks and resets

[Geert Uytterhoeven]

Hi Biju,

On Thu, 14 Aug 2025 at 14:48, Biju <biju.das.au@gmail.com> wrote:
> From: Biju Das <biju.das.jz@bp.renesas.com>
>
> The RZ/G3E GPT IP has multiple clocks and resets. It has bus and core
> clocks. The bus clock is module clock and core clock is sourced from
> the bus clock. So add support for module clock as parent reusing the
> existing rzv2h_cpg_fixed_mod_status_clk_register().

Thanks for your series!

> Biju Das (4):
>   clk: renesas: rzv2h: Refactor
>     rzv2h_cpg_fixed_mod_status_clk_register()
>   clk: renesas: rzv2h: Add support for parent mod clocks
>   dt-bindings: clock: renesas,r9a09g047-cpg: Add GPT core clocks
>   clk: renesas: r9a09g047: Add GPT clocks and resets

I think you are overcomplicating: according to the clock system diagram
and clock list sheets, gpt_[01]_pclk_sfr and gpt_[01]_clks_gpt_sfr
are really the same clocks (the same is true for rsci_[0-9]_pclk and
rsci_[0-9]_pclk_sfr).
So you can just describe gpt_[01]_pclk_sfr as normal module clocks,
and use them for both the core and bus blocks in DT, e.g.

    clocks = <&cpg CPG_MOD 0x31>, <&cpg CPG_MOD 0x31>;
    clock-names = "core", "bus";

Do you agree?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 0/4] Add RZ/G3E GPT clocks and resets

[Biju Das]

Hi Geert,

Thanks for the feedback.

> -----Original Message-----
> From: Geert Uytterhoeven <geert@linux-m68k.org>
> Sent: 19 August 2025 16:11
> Subject: Re: [PATCH 0/4] Add RZ/G3E GPT clocks and resets
> 
> Hi Biju,
> 
> On Thu, 14 Aug 2025 at 14:48, Biju <biju.das.au@gmail.com> wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > The RZ/G3E GPT IP has multiple clocks and resets. It has bus and core
> > clocks. The bus clock is module clock and core clock is sourced from
> > the bus clock. So add support for module clock as parent reusing the
> > existing rzv2h_cpg_fixed_mod_status_clk_register().
> 
> Thanks for your series!
> 
> > Biju Das (4):
> >   clk: renesas: rzv2h: Refactor
> >     rzv2h_cpg_fixed_mod_status_clk_register()
> >   clk: renesas: rzv2h: Add support for parent mod clocks
> >   dt-bindings: clock: renesas,r9a09g047-cpg: Add GPT core clocks
> >   clk: renesas: r9a09g047: Add GPT clocks and resets
> 
> I think you are overcomplicating: according to the clock system diagram and clock list sheets,
> gpt_[01]_pclk_sfr and gpt_[01]_clks_gpt_sfr are really the same clocks (the same is true for rsci_[0-
> 9]_pclk and rsci_[0-9]_pclk_sfr).

Thanks for correcting me. I got confused with CGC=GPT_0_pclk_sfr for the core clock
that made me to complicate the clks.

> So you can just describe gpt_[01]_pclk_sfr as normal module clocks, and use them for both the core and
> bus blocks in DT, e.g.
> 
>     clocks = <&cpg CPG_MOD 0x31>, <&cpg CPG_MOD 0x31>;
>     clock-names = "core", "bus";
> 
> Do you agree?

Yes, I agree.

Cheers,
Biju

Re: [PATCH 0/4] Add RZ/G3E GPT clocks and resets

[Geert Uytterhoeven]

On Tue, 19 Aug 2025 at 17:10, Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> I think you are overcomplicating: according to the clock system diagram
> and clock list sheets, gpt_[01]_pclk_sfr and gpt_[01]_clks_gpt_sfr

s/gpt_[01]_clks_gpt_sfr/gpt_[01]_clks_gpt/

> are really the same clocks (the same is true for rsci_[0-9]_pclk and
> rsci_[0-9]_pclk_sfr).

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH 3/4] dt-bindings: clock: renesas,r9a09g047-cpg: Add GPT core clocks

[Biju Das]

Hi Conor,

> -----Original Message-----
> From: Conor Dooley <conor@kernel.org>
> Sent: 14 August 2025 20:49
> Subject: Re: [PATCH 3/4] dt-bindings: clock: renesas,r9a09g047-cpg: Add GPT core clocks
> 
> On Thu, Aug 14, 2025 at 01:48:26PM +0100, Biju wrote:
> > From: Biju Das <biju.das.jz@bp.renesas.com>
> >
> > Add definitions for GPT core clocks in the R9A09G047 CPG DT bindings
> > header file.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Acked-by: Conor Dooley <conor.dooley@microchip.com>

I am dropping this patch based on [1]
[1] https://lore.kernel.org/all/TY3PR01MB113467CB44FFF5F65038153EA8633A@TY3PR01MB11346.jpnprd01.prod.outlook.com/

Cheers,
Biju