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[185.177.124.12]) by smtp.gmail.com with ESMTPSA id e13-20020adf9bcd000000b0020c5253d8basm11723098wrc.6.2022.05.04.05.57.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 May 2022 05:57:32 -0700 (PDT) Date: Wed, 04 May 2022 16:55:08 +0400 From: Yassine Oudjana Subject: Re: [PATCH 09/13] clk: mediatek: reset: Export mtk_register_reset_controller symbols To: Rex-BC Chen Cc: Matthias Brugger , Stephen Boyd , Michael Turquette , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Yassine Oudjana , Chun-Jie Chen , Chen-Yu Tsai , Tinghan Shen , AngeloGioacchino Del Regno , Weiyi Lu , Ikjoon Jang , Miles Chen , Sam Shih , Bartosz Golaszewski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Message-Id: In-Reply-To: References: <20220504122601.335495-1-y.oudjana@protonmail.com> <20220504122601.335495-10-y.oudjana@protonmail.com> X-Mailer: geary/40.0 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, May 4 2022 at 20:46:22 +0800, Rex-BC Chen wrote: > On Wed, 2022-05-04 at 16:25 +0400, Yassine Oudjana wrote: >> From: Yassine Oudjana >> >> Export mtk_register_reset_controller and >> mtk_register_reset_controller_set_clr to support building reset >> drivers as modules. >> >> Signed-off-by: Yassine Oudjana >> --- >> drivers/clk/mediatek/reset.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/drivers/clk/mediatek/reset.c >> b/drivers/clk/mediatek/reset.c >> index bcec4b89f449..6c2effe6afef 100644 >> --- a/drivers/clk/mediatek/reset.c >> +++ b/drivers/clk/mediatek/reset.c >> @@ -129,6 +129,7 @@ void mtk_register_reset_controller(struct >> device_node *np, >> mtk_register_reset_controller_common(np, num_regs, regofs, >> &mtk_reset_ops); >> } >> +EXPORT_SYMBOL_GPL(mtk_register_reset_controller); >> >> void mtk_register_reset_controller_set_clr(struct device_node *np, >> unsigned int num_regs, int regofs) >> @@ -136,5 +137,6 @@ void >> mtk_register_reset_controller_set_clr(struct >> device_node *np, >> mtk_register_reset_controller_common(np, num_regs, regofs, >> &mtk_reset_ops_set_clr); >> } >> +EXPORT_SYMBOL_GPL(mtk_register_reset_controller_set_clr); >> >> MODULE_LICENSE("GPL"); > > Hello Yassine, > > Thanks for your patch for mediatek clk reset. > But I have another series to cleanup mediatek clk reset drivers and > most of my patches are reviewed. > Please refer to > https://patchwork.kernel.org/project/linux-mediatek/list/?series=637849 Great! In that case I'll rebase my patches onto your series and see if anything is missing. Thanks, Yassine