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From:   Eric Biggers <ebiggers@kernel.org>
To:     Adrian Hunter <adrian.hunter@intel.com>
Cc:     linux-mmc@vger.kernel.org, linux-arm-msm@vger.kernel.org,
        devicetree@vger.kernel.org, linux-fscrypt@vger.kernel.org,
        Satya Tangirala <satyat@google.com>,
        Ulf Hansson <ulf.hansson@linaro.org>,
        Andy Gross <agross@kernel.org>,
        Bjorn Andersson <bjorn.andersson@linaro.org>,
        Ritesh Harjani <riteshh@codeaurora.org>,
        Asutosh Das <asutoshd@codeaurora.org>,
        Rob Herring <robh+dt@kernel.org>,
        Neeraj Soni <neersoni@codeaurora.org>,
        Barani Muthukumaran <bmuthuku@codeaurora.org>,
        Peng Zhou <peng.zhou@mediatek.com>,
        Stanley Chu <stanley.chu@mediatek.com>,
        Konrad Dybcio <konradybcio@gmail.com>
Subject: Re: [PATCH 8/8] mmc: sdhci-msm: add Inline Crypto Engine support
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References: <20201112194011.103774-1-ebiggers@kernel.org>
 <20201112194011.103774-9-ebiggers@kernel.org>
 <77142346-623e-3ca7-6c16-0adca68377f1@intel.com>
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On Wed, Dec 02, 2020 at 03:56:21PM +0200, Adrian Hunter wrote:
> > +/* Poll until all BIST (built-in self test) bits are reset */
> > +static int sdhci_msm_ice_wait_bist_status(struct sdhci_msm_host *msm_host)
> > +{
> > +	int count;
> > +	u32 reg;
> > +
> > +	for (count = 0; count < 100; count++) {
> > +		reg = sdhci_msm_ice_readl(msm_host, QCOM_ICE_REG_BIST_STATUS);
> > +		if (!(reg & QCOM_ICE_BIST_STATUS_MASK))
> > +			break;
> > +		udelay(50);
> 
> usleep_range ?
> 
> Also could use read_poll_timeout() here
> 

I'll change it to use readl_poll_timeout().

- Eric